FPGALab/ddr3_general_design
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2 Commits

Author SHA1 Message Date
UnbalancedCat
cf3f100d53 redo axi construction 2025-03-18 16:56:47 +08:00
UnbalancedCat
5436d507e7 most logic done (out has some issue, may has plenty of bugs) 2025-01-13 23:15:13 +08:00