resetn resetn clk clk cpu label if_stage label clk clk reset reset ds_allowin ds_allowin br_bus[32:0] br_bus[32:0] fs_to_ds_valid fs_to_ds_valid fs_to_ds_bus[63:0] fs_to_ds_bus[63:0] instr_ram_addr[31:0] instr_ram_addr[31:0] instr_ram_rdata[31:0] instr_ram_rdata[31:0] fs_valid fs_valid fs_ready_go fs_ready_go fs_allowin fs_allowin to_fs_valid to_fs_valid seq_pc[31:0] seq_pc[31:0] br_taken br_taken br_target[31:0] br_target[31:0] nextpc[31:0] nextpc[31:0] fs_instr[31:0] fs_instr[31:0] #FFD700 true fs_pc[31:0] fs_pc[31:0] #FFA500 true id_stage label clk clk reset reset es_allowin es_allowin ds_allowin ds_allowin fs_to_ds_valid fs_to_ds_valid fs_to_ds_bus[63:0] fs_to_ds_bus[63:0] ds_to_es_valid ds_to_es_valid ds_to_es_bus[177:0] ds_to_es_bus[177:0] ws_to_rf_bus[37:0] ws_to_rf_bus[37:0] ds_valid ds_valid ds_ready_go ds_ready_go fs_pc[31:0] fs_pc[31:0] fs_to_ds_bus_r[63:0] fs_to_ds_bus_r[63:0] rf_we rf_we rf_waddr[4:0] rf_waddr[4:0] rf_wdata[31:0] rf_wdata[31:0] ExtOp[4:0] ExtOp[4:0] BINARYRADIX ALUAsrc[1:0] ALUAsrc[1:0] BINARYRADIX ALUBsrc[2:0] ALUBsrc[2:0] BINARYRADIX ALUctr[10:0] ALUctr[10:0] BINARYRADIX Branch[5:0] Branch[5:0] Jump[1:0] Jump[1:0] MemtoReg MemtoReg MemWr MemWr RegWr RegWr rs1_value[31:0] rs1_value[31:0] rs2_value[31:0] rs2_value[31:0] op[6:0] op[6:0] BINARYRADIX func7[6:0] func7[6:0] BINARYRADIX func3[2:0] func3[2:0] BINARYRADIX rs2[4:0] rs2[4:0] rs1[4:0] rs1[4:0] rd[4:0] rd[4:0] immI[31:0] immI[31:0] immS[31:0] immS[31:0] immB[31:0] immB[31:0] immU[31:0] immU[31:0] immJ[31:0] immJ[31:0] imm[31:0] imm[31:0] #FFD700 true rf_raddr1[4:0] rf_raddr1[4:0] rf_raddr2[4:0] rf_raddr2[4:0] rf_rdata1[31:0] rf_rdata1[31:0] rf_rdata2[31:0] rf_rdata2[31:0] ds_instr[31:0] ds_instr[31:0] #FFD700 true ds_pc[31:0] ds_pc[31:0] #FFD700 true exe_stage label clk clk reset reset ms_allowin ms_allowin es_allowin es_allowin ds_to_es_valid ds_to_es_valid ds_to_es_bus[177:0] ds_to_es_bus[177:0] es_to_ms_valid es_to_ms_valid es_to_ms_bus[119:0] es_to_ms_bus[119:0] data_ram_en data_ram_en data_ram_wen[3:0] data_ram_wen[3:0] data_ram_addr[31:0] data_ram_addr[31:0] data_ram_wdata[31:0] data_ram_wdata[31:0] es_valid es_valid es_ready_go es_ready_go ds_to_es_bus_r[177:0] ds_to_es_bus_r[177:0] es_ALUAsrc[1:0] es_ALUAsrc[1:0] BINARYRADIX es_ALUBsrc[2:0] es_ALUBsrc[2:0] BINARYRADIX es_ALUctr[10:0] es_ALUctr[10:0] BINARYRADIX es_Branch[5:0] es_Branch[5:0] es_Jump[1:0] es_Jump[1:0] es_MemtoReg es_MemtoReg #FAAFBE true es_MemWr es_MemWr #FAAFBE true es_RegWr es_RegWr #FAAFBE true es_imm[31:0] es_imm[31:0] #FFD700 true es_rs1_value[31:0] es_rs1_value[31:0] es_rs2_value[31:0] es_rs2_value[31:0] es_rd[4:0] es_rd[4:0] br_target[31:0] br_target[31:0] es_alu_src1[31:0] es_alu_src1[31:0] #FFD700 true es_alu_src2[31:0] es_alu_src2[31:0] #FFD700 true es_alu_result[31:0] es_alu_result[31:0] #FFD700 true es_Zero es_Zero #FAAFBE true BusAFw[1:0] BusAFw[1:0] BusBFw[1:0] BusBFw[1:0] DiSrc DiSrc es_rs1_forward[31:0] es_rs1_forward[31:0] es_rs2_forward[31:0] es_rs2_forward[31:0] rf_wdata[31:0] rf_wdata[31:0] ms_alu_result[31:0] ms_alu_result[31:0] es_pc[31:0] es_pc[31:0] #FFD700 true mem_stage label clk clk reset reset ws_allowin ws_allowin ms_allowin ms_allowin es_to_ms_valid es_to_ms_valid es_to_ms_bus[119:0] es_to_ms_bus[119:0] ms_to_ws_valid ms_to_ws_valid ms_to_ws_bus[102:0] ms_to_ws_bus[102:0] br_bus[32:0] br_bus[32:0] data_ram_rdata[31:0] data_ram_rdata[31:0] ms_valid ms_valid ms_ready_go ms_ready_go es_to_ms_bus_r[119:0] es_to_ms_bus_r[119:0] ms_Branch[5:0] ms_Branch[5:0] ms_Jump[1:0] ms_Jump[1:0] ms_MemtoReg ms_MemtoReg #FAAFBE true ms_RegWr ms_RegWr #FAAFBE true ms_rd[4:0] ms_rd[4:0] #FFD700 true ms_alu_result[31:0] ms_alu_result[31:0] #FFD700 true br_target[31:0] br_target[31:0] ms_Zero ms_Zero #FAAFBE true mem_result[31:0] mem_result[31:0] br_taken br_taken #FAAFBE true ms_pc[31:0] ms_pc[31:0] #FFD700 true wb_stage label clk clk reset reset ws_allowin ws_allowin ms_to_ws_valid ms_to_ws_valid ms_to_ws_bus[102:0] ms_to_ws_bus[102:0] ws_to_rf_bus[37:0] ws_to_rf_bus[37:0] debug_wb_pc[31:0] debug_wb_pc[31:0] #F0E68C true debug_wb_rf_wen[3:0] debug_wb_rf_wen[3:0] #F0E68C true debug_wb_rf_wnum[4:0] debug_wb_rf_wnum[4:0] #F0E68C true debug_wb_rf_wdata[31:0] debug_wb_rf_wdata[31:0] #F0E68C true ws_valid ws_valid ws_ready_go ws_ready_go ms_to_ws_bus_r[102:0] ms_to_ws_bus_r[102:0] ws_MemtoReg ws_MemtoReg ws_RegWr ws_RegWr ws_rd[4:0] ws_rd[4:0] ws_alu_result[31:0] ws_alu_result[31:0] ws_pc[31:0] ws_pc[31:0] #FFD700 true rf_we rf_we rf_waddr[4:0] rf_waddr[4:0] rf_wdata[31:0] rf_wdata[31:0] alu label alu_op[10:0] alu_op[10:0] alu_src1[31:0] alu_src1[31:0] alu_src2[31:0] alu_src2[31:0] alu_result[31:0] alu_result[31:0] Carry Carry Sign Sign Overflow Overflow Zero Zero op_lui op_lui #FF00FF true op_add op_add #FF00FF true op_sub op_sub #FF00FF true op_or op_or #FF00FF true op_slt op_slt #FF00FF true op_sltu op_sltu #FF00FF true op_xor op_xor #FF00FF true op_and op_and #FF00FF true op_sll op_sll #FF00FF true op_srl op_srl #FF00FF true op_sra op_sra #FF00FF true lui_result[31:0] lui_result[31:0] add_sub_result[31:0] add_sub_result[31:0] slt_result[31:0] slt_result[31:0] sltu_result[31:0] sltu_result[31:0] xor_result[31:0] xor_result[31:0] or_result[31:0] or_result[31:0] and_result[31:0] and_result[31:0] sll_result[31:0] sll_result[31:0] sr64_result[31:0] sr64_result[31:0] sr_result[31:0] sr_result[31:0] adder_a[31:0] adder_a[31:0] adder_b[31:0] adder_b[31:0] adder_cin adder_cin adder_result[31:0] adder_result[31:0] adder_cout adder_cout ctrsignal label OP[6:0] OP[6:0] func3[2:0] func3[2:0] func7[6:0] func7[6:0] ExtOp[4:0] ExtOp[4:0] ALUAsrc[1:0] ALUAsrc[1:0] BINARYRADIX ALUBsrc[2:0] ALUBsrc[2:0] BINARYRADIX ALUctr[10:0] ALUctr[10:0] RegWr RegWr MemtoReg MemtoReg MemWr MemWr Branch[5:0] Branch[5:0] Jump[1:0] Jump[1:0] u_type u_type #FAAFBE true j_type j_type #FAAFBE true s_type s_type #FAAFBE true i_type i_type #FAAFBE true b_type b_type #FAAFBE true r_type r_type #FAAFBE true instr_lui instr_lui #FF00FF true instr_jal instr_jal #FF00FF true instr_beq instr_beq #FF00FF true instr_bne instr_bne #FF00FF true instr_blt instr_blt #FF00FF true instr_bge instr_bge #FF00FF true instr_bltu instr_bltu #FF00FF true instr_bgeu instr_bgeu #FF00FF true instr_lw instr_lw #FF00FF true instr_sw instr_sw #FF00FF true instr_ori instr_ori #FF00FF true instr_add instr_add #FF00FF true instr_sub instr_sub #FF00FF true instr_slt instr_slt #FF00FF true instr_sltu instr_sltu #FF00FF true instr_addi instr_addi #FF00FF true instr_xori instr_xori #FF00FF true instr_andi instr_andi #FF00FF true instr_xor instr_xor #FF00FF true instr_or instr_or #FF00FF true instr_and instr_and #FF00FF true forward label es_to_fw_bus[11:0] es_to_fw_bus[11:0] ms_to_fw_bus[5:0] ms_to_fw_bus[5:0] fw_to_es_bus[4:0] fw_to_es_bus[4:0] es_rs2[4:0] es_rs2[4:0] ms_rd[4:0] ms_rd[4:0] ms_RegWr ms_RegWr BusAFw[1:0] BusAFw[1:0] BusBFw[1:0] BusBFw[1:0] DiSrc DiSrc loaduse label clk clk reset reset ds_to_lu_bus[9:0] ds_to_lu_bus[9:0] es_to_lu_bus[9:0] es_to_lu_bus[9:0] ds_stall ds_stall es_flush es_flush ds_sr1[4:0] ds_sr1[4:0] ds_sr2[4:0] ds_sr2[4:0] es_Load[4:0] es_Load[4:0] es_rd[4:0] es_rd[4:0] stall stall pipctr label clk clk reset reset lu_flush lu_flush dh_flush dh_flush dh_stall dh_stall fs_stall fs_stall fs_flush fs_flush ds_flush ds_flush es_flush es_flush ms_flush ms_flush ws_flush ws_flush flush[7:0] flush[7:0] stall[1:0] stall[1:0] regfile label clk clk raddr1[4:0] raddr1[4:0] rdata1[31:0] rdata1[31:0] raddr2[4:0] raddr2[4:0] rdata2[31:0] rdata2[31:0] we we waddr[4:0] waddr[4:0] wdata[31:0] wdata[31:0] rf[31:0][31:0] rf[31:0][31:0] data_ram label clka clka ena ena wea[3:0] wea[3:0] addra[15:0] addra[15:0] dina[31:0] dina[31:0] douta[31:0] douta[31:0] instr_ram label clka clka ena ena wea[3:0] wea[3:0] addra[15:0] addra[15:0] dina[31:0] dina[31:0] douta[31:0] douta[31:0]