`timescale 1ns / 1ps

module soc_top(
    input         resetn, 
    input         clk,
    input  [ 4:0] switch,
    output [15:0] led
    );
    
    wire        cpu_clk;
    reg         cpu_resetn;
    wire [31:0] led32;
    assign led = led32[15:0];
    
    
    
    always @(posedge cpu_clk)
    begin
        cpu_resetn <= resetn;
    end
    
    pll u_pll(
        .clk_in1  (clk),
        .clk_out1 (cpu_clk)
    );

    
    //cpu instr ram
    wire        cpu_instr_en;
    wire [ 3:0] cpu_instr_wen;
    wire [31:0] cpu_instr_addr;
    wire [31:0] cpu_instr_wdata;
    wire [31:0] cpu_instr_rdata;
    //cpu data ram
    wire        cpu_data_en;
    wire [ 3:0] cpu_data_wen;
    wire [31:0] cpu_data_addr;
    wire [31:0] cpu_data_wdata;
    wire [31:0] cpu_data_rdata;
    //debug signals
    wire [31:0] debug_wb_pc;
    wire [ 3:0] debug_wb_rf_wen;
    wire [ 4:0] debug_wb_rf_wnum;
    wire [31:0] debug_wb_rf_wdata;
    
    cpu_top cpu(
        .clk              (cpu_clk   ),
        .resetn           (cpu_resetn),
    
        .instr_ram_en     (cpu_instr_en   ),
        .instr_ram_wen    (cpu_instr_wen  ),
        .instr_ram_addr   (cpu_instr_addr ),
        .instr_ram_wdata  (cpu_instr_wdata),
        .instr_ram_rdata  (cpu_instr_rdata),
        
        .data_ram_en     (cpu_data_en   ),
        .data_ram_wen    (cpu_data_wen  ),
        .data_ram_addr   (cpu_data_addr ),
        .data_ram_wdata  (cpu_data_wdata),
        .data_ram_rdata  (cpu_data_rdata),
        
        //debug
        .debug_wb_pc      (debug_wb_pc      ),
        .debug_wb_rf_wen  (debug_wb_rf_wen  ),
        .debug_wb_rf_wnum (debug_wb_rf_wnum ),
        .debug_wb_rf_wdata(debug_wb_rf_wdata),
        
        .rf_raddr         (switch           ),
        .rf_rdata         (led32            )
    );
    
    //instr ram
    instr_ram instr_ram
    (
        .clka  (cpu_clk             ),   
        .ena   (cpu_instr_en        ),
        .wea   (cpu_instr_wen       ),   //3:0
        .addra (cpu_instr_addr[17:2]),   //15:0
        .dina  (cpu_instr_wdata     ),   //31:0
        .douta (cpu_instr_rdata     )    //31:0
    );
    
    
    //data ram
    data_ram data_ram
    (
        .clka  (cpu_clk             ),   
        .ena   (cpu_data_en         ),
        .wea   (cpu_data_wen        ),   //3:0
        .addra (cpu_data_addr[17:2] ),   //15:0
        .dina  (cpu_data_wdata      ),   //31:0
        .douta (cpu_data_rdata      )    //31:0
    );

endmodule
