355 lines
14 KiB
Verilog
355 lines
14 KiB
Verilog
`include "csr.hv"
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module csr(
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input clk,
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input reset,
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input stall,
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input [31:0] pc,
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input [31:0] src1,
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input stallreq_axi,
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input [31:0] error_va,
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input csr_we,
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input [63:0] csr_vec,
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input [ 6:0] csr_op,
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input [13:0] csr_addr,
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input csr_wdata_sel,
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input [31:0] csr_wdata,
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output [31:0] csr_rdata,
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output except_en,
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output [31:0] new_pc,
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output [ 1:0] plv_out,
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output has_int_out
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);
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reg [31:0] crmd; // ??????
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reg [31:0] prmd; // ???????
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reg [31:0] euen; // ??????
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reg [31:0] ecfg; // ????
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reg [31:0] estat; // ????
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reg [31:0] era; // ??????
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reg [31:0] badv; // ?????
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reg [31:0] eentry; // ??????
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reg [31:0] tlbidx; // TLB ??
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reg [31:0] tlbehi; // TLB ?????
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reg [31:0] tlbelo0; // TLB ???? 0
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reg [31:0] tlbelo1; // TLB ???? 1
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reg [31:0] asid; // ???????
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reg [31:0] pgdl; // ????????????
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reg [31:0] pgdh; // ????????????
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reg [31:0] pgd; // ??????
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reg [31:0] cpuid; // ?????
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reg [31:0] save0; // ????0
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reg [31:0] save1; // ????1
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reg [31:0] save2; // ????2
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reg [31:0] save3; // ????3
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reg [31:0] tid; // ?????
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reg [31:0] tcfg; // ?????
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reg [31:0] tval; // ????
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reg [31:0] ticlr; // ??????
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reg [31:0] llbctl; // LLbit ??
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reg [31:0] tlbrentry; // TLB ????????
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reg [31:0] ctag; // ??????
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reg [31:0] dmw0; // ????????0
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reg [31:0] dmw1; // ????????1
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reg [31:0] csr_rdata_r;
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reg timer_en;
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reg [63:0] timer_64;
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// reg has_int_r;
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// reg [ 1:0] plv_r;
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wire inst_sc_w;
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wire inst_csrrd;
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wire inst_csrwr;
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wire inst_csrxchg;
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wire inst_rdcntid_w;
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wire inst_rdcntvl_w;
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wire inst_rdcntvh_w;
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wire has_int;
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wire excp_ale;
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wire excp_adef;
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wire excp_ipe;
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wire excp_ine;
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wire inst_break;
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wire inst_syscall;
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wire inst_ertn;
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wire [31:0] csr_wdata_temp;
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wire [ 5:0] ecode;
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wire [ 8:0] esubcode;
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wire va_error;
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wire [31:0] bad_va;
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// always @(posedge clk) begin
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// if(reset) begin
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// has_int_r <= 0;
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// plv_r <= 0;
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// end
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// else begin
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// has_int_r <= ((ecfg[`LIE] & estat[`IS]) != 13'b0) & crmd[`IE];
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// plv_r <= except_en & !inst_ertn ? 2'b0 :
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// inst_ertn ? prmd[`PPLV] :
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// csr_we && (csr_addr == `CRMD_ADDR) ? csr_wdata[`PLV] :
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// crmd[`PLV];
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// end
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// end
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// out TODO!
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assign has_int_out = ((ecfg[`LIE] & estat[`IS]) != 13'b0) & crmd[`IE];
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assign plv_out = except_en & !inst_ertn ? 2'b0 :
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inst_ertn ? prmd[`PPLV] :
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csr_we && (csr_addr == `CRMD_ADDR) ? csr_wdata[`PLV] :
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crmd[`PLV];
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assign {excp_ale,
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excp_adef,
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excp_ipe,
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excp_ine,
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inst_break,
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inst_syscall,
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inst_ertn,
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has_int
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} = csr_vec[7:0];
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assign {ecode, esubcode, va_error, bad_va} = excp_adef ? {`ECODE_ADEF, `ESUBCODE_ADEF, 1'b1, pc } :
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has_int ? {`ECODE_INT , 9'b0 , 1'b0, 32'b0 } :
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inst_syscall ? {`ECODE_SYS , 9'b0 , 1'b0, 32'b0 } :
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inst_break ? {`ECODE_BRK , 9'b0 , 1'b0, 32'b0 } :
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excp_ine ? {`ECODE_INE , 9'b0 , 1'b0, 32'b0 } :
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excp_ipe ? {`ECODE_IPE , 9'b0 , 1'b0, 32'b0 } :
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excp_ale ? {`ECODE_ALE , 9'b0 , 1'b1, error_va} :
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0;
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assign csr_rdata = csr_rdata_r;
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always @(*) begin
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if(|csr_op[6:4]) begin
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case(csr_addr)
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`CRMD_ADDR : csr_rdata_r <= crmd;
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`PRMD_ADDR : csr_rdata_r <= prmd;
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`EUEN_ADDR : csr_rdata_r <= euen;
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`ECFG_ADDR : csr_rdata_r <= ecfg;
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`ESTAT_ADDR : csr_rdata_r <= estat;
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`ERA_ADDR : csr_rdata_r <= era;
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`BADV_ADDR : csr_rdata_r <= badv;
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`EENTRY_ADDR : csr_rdata_r <= eentry;
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`TLBIDX_ADDR : csr_rdata_r <= tlbidx;
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`TLBEHI_ADDR : csr_rdata_r <= tlbehi;
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`TLBELO0_ADDR : csr_rdata_r <= tlbelo0;
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`TLBELO1_ADDR : csr_rdata_r <= tlbelo1;
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`ASID_ADDR : csr_rdata_r <= asid;
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`PGDL_ADDR : csr_rdata_r <= pgdl;
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`PGDH_ADDR : csr_rdata_r <= pgdh;
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`PGD_ADDR : csr_rdata_r <= pgd;
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`CPUID_ADDR : csr_rdata_r <= cpuid;
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`SAVE0_ADDR : csr_rdata_r <= save0;
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`SAVE1_ADDR : csr_rdata_r <= save1;
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`SAVE2_ADDR : csr_rdata_r <= save2;
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`SAVE3_ADDR : csr_rdata_r <= save3;
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`TID_ADDR : csr_rdata_r <= tid;
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`TCFG_ADDR : csr_rdata_r <= tcfg;
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`TVAL_ADDR : csr_rdata_r <= tval;
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`TICLR_ADDR : csr_rdata_r <= ticlr;
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`LLBCTL_ADDR : csr_rdata_r <= llbctl;
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`TLBRENTRY_ADDR : csr_rdata_r <= tlbrentry;
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`CTAG_ADDR : csr_rdata_r <= ctag;
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`DMW0_ADDR : csr_rdata_r <= dmw0;
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`DMW1_ADDR : csr_rdata_r <= dmw1;
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default : csr_rdata_r <= 32'b0;
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endcase
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end
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else if(|csr_op[3:1]) begin
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csr_rdata_r <= ({33{csr_op[1]}} & timer_64[31: 0]) |
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({33{csr_op[2]}} & timer_64[63:32]) |
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({33{csr_op[3]}} & tid);
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end
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else begin
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//csr_rdata_r <= 32'b0;
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end
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end
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assign {inst_csrrd,
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inst_csrwr,
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inst_csrxchg,
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inst_rdcntid_w,
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inst_rdcntvh_w,
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inst_rdcntvl_w,
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inst_sc_w
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} = csr_op;
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assign csr_wdata_temp = csr_wdata_sel ? (src1 & csr_wdata) | (~src1 & csr_rdata_r) : csr_wdata;
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always @(posedge clk) begin
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if(reset) begin
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crmd <= 32'd8;
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prmd <= 0;
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euen <= 0;
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ecfg <= 0;
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estat <= 0;
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era <= 0;
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badv <= 0;
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eentry <= 0;
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tlbidx <= 0;
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tlbehi <= 0;
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tlbelo0 <= 0;
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tlbelo1 <= 0;
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asid <= 0;
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pgdl <= 0;
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pgdh <= 0;
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pgd <= 0;
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cpuid <= 0;
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save0 <= 0;
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save1 <= 0;
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save2 <= 0;
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save3 <= 0;
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tid <= 0;
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tcfg <= 32'hfffffffe;
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tval <= 0;
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ticlr <= 0;
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llbctl <= 0;
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tlbrentry <= 0;
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ctag <= 0;
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dmw0 <= 0;
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dmw1 <= 0;
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timer_en <= 1'b0;
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end
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else if(except_en & ~stallreq_axi) begin
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if((|csr_vec[7:0] & !inst_ertn) | excp_adef) begin
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crmd[ `PLV] <= 2'b0;
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crmd[ `IE] <= 1'b0;
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prmd[`PPLV] <= crmd[`PLV];
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prmd[ `PIE] <= crmd[`IE ];
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estat[ `ECODE] <= ecode;
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estat[`ESUBCODE] <= esubcode;
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era <= pc;
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end
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else if(inst_ertn) begin
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crmd[ `PLV] <= prmd[`PPLV];
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crmd[ `IE] <= prmd[`PIE ];
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end
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if(va_error) begin
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badv <= bad_va;
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end
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end
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else if (csr_we) begin
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case (csr_addr)
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`CRMD_ADDR : begin
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crmd[ `PLV] <= csr_wdata_temp[ `PLV];
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crmd[ `IE] <= csr_wdata_temp[ `IE];
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crmd[ `DA] <= csr_wdata_temp[ `DA];
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crmd[ `PG] <= csr_wdata_temp[ `PG];
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crmd[`DATF] <= csr_wdata_temp[`DATF];
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crmd[`DATM] <= csr_wdata_temp[`DATM];
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end
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`PRMD_ADDR : begin
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prmd[`PPLV] <= csr_wdata_temp[`PPLV];
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prmd[ `PIE] <= csr_wdata_temp[ `PIE];
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end
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`EUEN_ADDR : euen <= csr_wdata_temp;
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`ECFG_ADDR : begin
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ecfg <= csr_wdata_temp; // ????????????????
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end
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`ESTAT_ADDR : estat[1:0] <= csr_wdata_temp[1:0];
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`ERA_ADDR : era <= csr_wdata_temp;
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`BADV_ADDR : badv <= csr_wdata_temp; // MORE
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`EENTRY_ADDR : eentry[31:6] <= csr_wdata_temp[31:6];
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`TLBIDX_ADDR : tlbidx <= csr_wdata_temp; // PASS
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`TLBEHI_ADDR : tlbehi <= csr_wdata_temp; // PASS
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`TLBELO0_ADDR : tlbelo0 <= csr_wdata_temp; // PASS
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`TLBELO1_ADDR : tlbelo1 <= csr_wdata_temp; // PASS
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`ASID_ADDR : asid[`TLB_ASID] <= csr_wdata_temp[`TLB_ASID]; // MORE
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`PGDL_ADDR : pgdl <= csr_wdata_temp;
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`PGDH_ADDR : pgdh <= csr_wdata_temp;
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`PGD_ADDR : pgd <= csr_wdata_temp;
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//`CPUID_ADDR : cpuid <= csr_wdata_temp;
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`SAVE0_ADDR : save0 <= csr_wdata_temp;
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`SAVE1_ADDR : save1 <= csr_wdata_temp;
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`SAVE2_ADDR : save2 <= csr_wdata_temp;
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`SAVE3_ADDR : save3 <= csr_wdata_temp;
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`TID_ADDR : tid <= csr_wdata_temp;
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`TCFG_ADDR : begin
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tcfg[ `EN] <= csr_wdata_temp[ `EN];
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tcfg[`PERIODIC] <= csr_wdata_temp[`PERIODIC];
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tcfg[ `INITVAL] <= csr_wdata_temp[ `INITVAL];
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tval <= {csr_wdata_temp[ `INITVAL], 2'b0};
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timer_en <= csr_wdata_temp[`EN];
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end
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//`TVAL_ADDR : tval <= {csr_wdata_temp[ `INITVAL], 2'b0};
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`TICLR_ADDR : begin
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if(csr_wdata_temp[`CLR]) begin
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estat[11] <= 1'b0;
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end
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end
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`LLBCTL_ADDR : llbctl <= csr_wdata_temp; // PASS
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`TLBRENTRY_ADDR : tlbrentry <= csr_wdata_temp; // PASS
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`CTAG_ADDR : ctag <= csr_wdata_temp;
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`DMW0_ADDR : begin
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dmw0[`PLV0] <= csr_wdata_temp[`PLV0];
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dmw0[`PLV3] <= csr_wdata_temp[`PLV3];
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dmw0[`DMW_MAT] <= csr_wdata_temp[`DMW_MAT];
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dmw0[`PSEG] <= csr_wdata_temp[`PSEG];
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dmw0[`VSEG] <= csr_wdata_temp[`VSEG];
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end
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`DMW1_ADDR : begin
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dmw1[`PLV0] <= csr_wdata_temp[`PLV0];
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dmw1[`PLV3] <= csr_wdata_temp[`PLV3];
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dmw1[`DMW_MAT] <= csr_wdata_temp[`DMW_MAT];
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dmw1[`PSEG] <= csr_wdata_temp[`PSEG];
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dmw1[`VSEG] <= csr_wdata_temp[`VSEG];
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end
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endcase
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end
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else begin
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// estat
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if(timer_en && (tval == 32'b0)) begin
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estat[11] <= 1'b1;
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timer_en <= tcfg[`PERIODIC];
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end
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//estat[9:0] <= intrpt; // ???
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// tval
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if(timer_en) begin
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if (tval != 32'b0) begin
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tval <= tval - 32'b1;
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end
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else if (tval == 32'b0) begin
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tval <= tcfg[`PERIODIC] ? {tcfg[`INITVAL], 2'b0} : 32'hffffffff;
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end
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end
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end
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end
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assign except_en = |csr_vec[7:0];
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assign new_pc = (|csr_vec[7:0] & !inst_ertn) | excp_adef ? eentry :
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inst_ertn ? era :
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32'b0; // TODO!
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//timer_64
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always @(posedge clk) begin
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if (reset) begin
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timer_64 <= 64'b0;
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end
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else begin
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timer_64 <= timer_64 + 1'b1;
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end
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end
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endmodule |