289 lines
9.6 KiB
C++
289 lines
9.6 KiB
C++
#include <common.h>
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#include <devaddr.h>
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#include <la32r.hh>
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namespace {
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using u64 = uint64_t;
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using i64 = int64_t;
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using u32 = uint32_t;
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using i32 = int32_t;
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SystemBus *sysbus;
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enum regenum {
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R0, R1, R2, R3, R4, R5, R6, R7, R8, R9,
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R10, R11, R12, R13, R14, R15, R16, R17, R18, R19,
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R20, R21, R22, R23, R24, R25, R26, R27, R28, R29,
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R30, R31, PC
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};
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enum PLV {
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PLV0,
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// PLV1,
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// PLV2,
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PLV3,
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} PrivilegeLevel ;
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class Registers {
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private:
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u32 regs_[32] = {0};
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u32 pc_ = 0;
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public:
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Registers() = default;
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u32 get(u32 idx) {
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panicifnot((0 <= idx && 32 >= idx) || idx == PC);
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if (idx == PC) {
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return pc_;
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}
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if (0 <= idx && 32 >= idx) {
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return regs_[idx];
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}
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panic("Unexpected register access");
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}
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void set(u32 idx, u32 data) {
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panicifnot((0 <= idx && 32 >= idx) || idx == PC);
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if (idx == PC) {
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pc_ = data;
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}
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if (0 <= idx && 32 >= idx) {
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regs_[idx] = data;
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}
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panic("Unexpected register access");
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}
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u32 &operator[](u32 idx) {
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if (idx == PC) {
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return pc_;
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}
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if (0 <= idx && 32 >= idx) {
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return regs_[idx];
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}
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panic("Unexpected register access");
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}
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} Regs ;
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constexpr u32 gb(u32 hi, u32 lo, u32 data) {
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panicifnot(hi >= lo);
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data = data >> lo;
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u32 width = hi - lo + 1;
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u32 mask = (u32)(~0) >> (32 - width);
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return data & mask;
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}
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constexpr u32 sext(u32 data, u32 width) {
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u32 upper = 32 - width;
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u32 result = (i32)(data << upper) >> upper;
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return result;
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}
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bool check(const char *instfmt, u32 inst) {
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size_t len = strlen(instfmt);
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panicifnot(len >= 32);
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u32 hit = 0;
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// alert ! i should gt 0 not geq 0
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for (size_t i = len; i > 0; --i) {
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auto idx = i - 1;
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if (std::tolower(instfmt[idx]) == 'x') {
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inst >>= 1;
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hit += 1;
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continue;
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} else if (instfmt[idx] == '0' && (inst & 0x1) == 0x0) {
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inst >>= 1;
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hit += 1;
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continue;
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} else if (instfmt[idx] == '1' && (inst & 0x1) == 0x1) {
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inst >>= 1;
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hit += 1;
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continue;
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} else if (strchr("'., ", instfmt[idx])) {
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continue;
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}
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return false;
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}
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return hit == 32;
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}
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u32 SLL(u32 data, u32 sa) {
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if (sa == 0)
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return data;
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return data << sa;
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}
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u32 SRL(u32 data, u32 sa) {
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if (sa == 0)
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return data;
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return data >> sa;
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}
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u32 SRA(u32 data, u32 sa) {
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if (sa == 0)
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return data;
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return (i32)data >> sa;
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}
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#define BEGIN_CHECK() if (false) {}
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#define INST(str, instname, extracond, ...) \
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else if (check((str), (inst)) && (extracond)) { \
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curinst = #instname; \
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__VA_ARGS__; \
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}
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void decode_and_exec(u32 inst) {
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// These decode is fixed
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u32 rd = gb( 4, 0, inst);
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u32 rj = gb( 9, 5, inst);
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u32 cj = gb( 7, 5, inst);
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u32 rk = gb(14, 10, inst);
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u32 ui5 = rk;
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u32 ui12 = gb(21, 10, inst);
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u32 si12 = sext(ui12, 12);
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u32 si14 = sext(gb(23, 10, inst), 14);
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u32 si20 = sext(gb(24, 5, inst), 20);
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u32 csr = gb(23, 10, inst);
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u32 offs_15_00 = gb(25, 10, inst);
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u32 offs_20_16 = gb( 4, 0, inst);
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u32 offs_25_16 = gb( 9, 0, inst);
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u32 code = rd << 0 | rj << 5 | rk << 10;
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u32 level = code;
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u32 hint = code;
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u32 code5 = rd;
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u32 hint5 = code5;
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u32 op = code5;
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const char *curinst = nullptr;
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BEGIN_CHECK()
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INST("00000000000000000'1100'0'xxxxx'00000", RDCNTID.W, gb(4, 0, inst) == 0)
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INST("00000000000000000'1100'0'00000'xxxxx", RDCNTVL.W, gb(9, 5, inst) == 0)
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INST("00000000000000000'1100'1'00000'xxxxx", RDCNTVH.W, gb(9, 5, inst) == 0)
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INST("00000000000'100000'xxxxx'xxxxx'xxxxx", ADD.W, true, Regs[rd] = Regs[rj] + Regs[rk])
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INST("00000000000'100010'xxxxx'xxxxx'xxxxx", SUB.W, true, Regs[rd] = Regs[rj] - Regs[rk])
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INST("00000000000'100100'xxxxx'xxxxx'xxxxx", SLT, true, Regs[rd] = (i32)Regs[rj] < (i32)Regs[rk])
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INST("00000000000'100101'xxxxx'xxxxx'xxxxx", SLTU, true, Regs[rd] = Regs[rj] < Regs[rk])
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INST("00000000000'101000'xxxxx'xxxxx'xxxxx", NOR, true, Regs[rd] = ~(Regs[rj] | Regs[rk]))
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INST("00000000000'101001'xxxxx'xxxxx'xxxxx", AND, true, Regs[rd] = Regs[rj] & Regs[rk])
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INST("00000000000'101010'xxxxx'xxxxx'xxxxx", OR, true, Regs[rd] = Regs[rj] | Regs[rk])
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INST("00000000000'101011'xxxxx'xxxxx'xxxxx", XOR, true, Regs[rd] = Regs[rj] ^ Regs[rk])
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INST("00000000000'101110'xxxxx'xxxxx'xxxxx", SLL.W, true, Regs[rd] = SLL(Regs[rj], gb(4, 0, Regs[rk])))
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INST("00000000000'101111'xxxxx'xxxxx'xxxxx", SRL.W, true, Regs[rd] = SRL(Regs[rj], gb(4, 0, Regs[rk])))
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INST("00000000000'110000'xxxxx'xxxxx'xxxxx", SRA.W, true, Regs[rd] = SRA(Regs[rj], gb(4, 0, Regs[rk])))
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INST("00000000000'111000'xxxxx'xxxxx'xxxxx", MUL.W, true, Regs[rd] = Regs[rj] * Regs[rk])
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INST("00000000000'111001'xxxxx'xxxxx'xxxxx", MULH.W, true, Regs[rd] = (u32)(((i64)(i32)Regs[rj] * (i64)(i32)Regs[rk]) >> 32))
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INST("00000000000'111010'xxxxx'xxxxx'xxxxx", MULH.WU, true, Regs[rd] = (u32)(((u64)Regs[rj] * (u64)Regs[rk]) >> 32))
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INST("0000000000'1000000'xxxxx'xxxxx'xxxxx", DIV.W, true, Regs[rd] = (i32)Regs[rj] / (i32)Regs[rk])
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INST("0000000000'1000001'xxxxx'xxxxx'xxxxx", MOD.W, true, Regs[rd] = (i32)Regs[rj] % (i32)Regs[rk])
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INST("0000000000'1000010'xxxxx'xxxxx'xxxxx", DIV.WU, true, Regs[rd] = Regs[rj] / Regs[rk])
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INST("0000000000'1000011'xxxxx'xxxxx'xxxxx", MOD.WU, true, Regs[rd] = Regs[rj] % Regs[rk])
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INST("0000000000'1010100'xxxxx xxxxx xxxxx", BREAK, true, )
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INST("0000000000'1010110'xxxxx xxxxx xxxxx", SYSCALL, true, )
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INST("000000000'10000'000'xxxxx'xxxxx'xxxxx", SLLI.W, true, Regs[rd] = SLL(Regs[rj], ui5))
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INST("000000000'10000'001'xxxxx'xxxxx'xxxxx", SRLI.W, true, Regs[rd] = SRL(Regs[rj], ui5))
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INST("000000000'10000'010'xxxxx'xxxxx'xxxxx", SRAI.W, true, Regs[rd] = SRA(Regs[rj], ui5))
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INST("000000'1000'xxxxxxx xxxxx'xxxxx'xxxxx", SLTI, true, Regs[rd] = (i32)Regs[rj] < (i32)si12)
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INST("000000'1001'xxxxxxx xxxxx'xxxxx'xxxxx", SLTUI, true, Regs[rd] = Regs[rj] < si12)
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INST("000000'1010'xxxxxxx xxxxx'xxxxx'xxxxx", ADDI.W, true, Regs[rd] = Regs[rj] + si12)
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INST("000000'1101'xxxxxxx xxxxx'xxxxx'xxxxx", ANDI, true, Regs[rd] = Regs[rj] & ui12)
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INST("000000'1110'xxxxxxx xxxxx'xxxxx'xxxxx", ORI, true, Regs[rd] = Regs[rj] | ui12)
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INST("000000'1111'xxxxxxx xxxxx'xxxxx'xxxxx", XORI, true, Regs[rd] = Regs[rj] ^ ui12)
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INST("00000'100'xxxxxxxxxxxxxx'00000'xxxxx", CSRRD, gb(9, 5, inst) == 0, )
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INST("00000'100'xxxxxxxxxxxxxx'00001'xxxxx", CSRWR, gb(9, 5, inst) == 1, )
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INST("00000'100'xxxxxxxxxxxxxx'xxxxx'xxxxx", CSRXCHG, gb(9, 5, inst) > 1, )
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INST("00000'11000'xxxxxxxxxxxx'xxxxx'xxxxx", CACOP, true, )
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INST("00000'1100'1001000001'010'00000'00000", TLBSRCH, true, )
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INST("00000'1100'1001000001'011'00000'00000", TLBRD, true, )
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INST("00000'1100'1001000001'100'00000'00000", TLBWR, true, )
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INST("00000'1100'1001000001'101'00000'00000", TLBFILL, true, )
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INST("00000'1100'1001000001'110'00000'00000", ERTN, true, )
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INST("00000'1100'1001'0001'xxxxx xxxxx xxxxx", IDLE, true, )
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INST("00000'1100'1001'0011'xxxxx'xxxxx'xxxxx", INVTLB, true, )
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INST("000'1010'xxxxxxxxxxxxxxxxxxxx'xxxxx", LU12I.W, true, )
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INST("000'1110'xxxxxxxxxxxxxxxxxxxx'xxxxx", PCADDU12I, true, )
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INST("00'100000'xxxxxxxxxxxxxx'xxxxx'xxxxx", LL.W, true, )
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INST("00'100001'xxxxxxxxxxxxxx'xxxxx'xxxxx", SC.W, true, )
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INST("00'10100000'xxxxxxxxxxxx'xxxxx'xxxxx", LD.B, true, )
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INST("00'10100001'xxxxxxxxxxxx'xxxxx'xxxxx", LD.H, true, )
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INST("00'10100010'xxxxxxxxxxxx'xxxxx'xxxxx", LD.W, true, )
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INST("00'10100100'xxxxxxxxxxxx'xxxxx'xxxxx", ST.B, true, )
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INST("00'10100101'xxxxxxxxxxxx'xxxxx'xxxxx", ST.H, true, )
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INST("00'10100110'xxxxxxxxxxxx'xxxxx'xxxxx", ST.W, true, )
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INST("00'10101000'xxxxxxxxxxxx'xxxxx'xxxxx", LD.BU, true, )
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INST("00'10101001'xxxxxxxxxxxx'xxxxx'xxxxx", LD.HU, true, )
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INST("00'10101011'xxxxxxxxxxxx'xxxxx'xxxxx", PRELD, true, )
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INST("00'111000011100100'xxxxx xxxxx xxxxx", DBAR, true, )
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INST("00'111000011100101'xxxxx xxxxx xxxxx", IBAR, true, )
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INST("0'10010'xxxxxxxxxxxxxxxx'00xxx'xxxxx", BCEQZ, gb(9, 8, inst) == 0, )
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INST("0'10010'xxxxxxxxxxxxxxxx'01xxx'xxxxx", BCNEZ, gb(9, 8, inst) == 1, )
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INST("0'10011'xxxxxxxxxxxxxxxx'xxxxx'xxxxx", JIRL, true, )
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INST("0'10100'xxxxxxxxxxxxxxxx'xxxxx xxxxx", B, true, )
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INST("0'10101'xxxxxxxxxxxxxxxx'xxxxx xxxxx", BL, true, )
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INST("0'10110'xxxxxxxxxxxxxxxx'xxxxx'xxxxx", BEQ, true, )
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INST("0'10111'xxxxxxxxxxxxxxxx'xxxxx'xxxxx", BNE, true, )
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INST("0'11000'xxxxxxxxxxxxxxxx'xxxxx'xxxxx", BLT, true, )
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INST("0'11001'xxxxxxxxxxxxxxxx'xxxxx'xxxxx", BGE, true, )
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INST("0'11010'xxxxxxxxxxxxxxxx'xxxxx'xxxxx", BLTU, true, )
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INST("0'11011'xxxxxxxxxxxxxxxx'xxxxx'xxxxx", BGEU, true, )
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printf("%08x: %s\n", inst, curinst);
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}
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u32 fetch() {
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u32 inst;
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sysbus->read32(inst, Regs[PC]);
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return inst;
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}
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}
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LA32R::LA32R(SystemBus *bus) {
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sysbus = bus;
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Regs[PC] = IMG_ADDR;
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}
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void LA32R::Step(unsigned in) {
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u32 inst = fetch();
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decode_and_exec(inst);
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Regs[PC] += 4;
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} |