UnbalancedCat/neulacpu
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bf2dd4655b53f5ac95d4bd75d8f93db9995bb856
neulacpu/lacpu/rtl/mycpu
History
UnbalancedCat bf2dd4655b [Backup] ready for switching to 7-stage pipline
2023-07-25 21:06:44 +08:00
..
alu.v
[Modified] Switch soc_top&board to axi&xc7a200t
2023-07-20 21:40:21 +08:00
axi_ctrl.v
[Modified] Switch soc_top&board to axi&xc7a200t
2023-07-20 21:40:21 +08:00
bru.v
[Modified] Switch soc_top&board to axi&xc7a200t
2023-07-20 21:40:21 +08:00
cache_data.v
[Modified] Switch soc_top&board to axi&xc7a200t
2023-07-20 21:40:21 +08:00
cache_tag.v
[Modified] Switch soc_top&board to axi&xc7a200t
2023-07-20 21:40:21 +08:00
csr.hv
[Modified] Switch soc_top&board to axi&xc7a200t
2023-07-20 21:40:21 +08:00
csr.v
[Add] add ext_int
2023-07-23 01:59:53 +08:00
dcache.v
[Modified] Switch soc_top&board to axi&xc7a200t
2023-07-20 21:40:21 +08:00
div.v
[Modified] Switch soc_top&board to axi&xc7a200t
2023-07-20 21:40:21 +08:00
exe_stage.v
[Backup] ready for switching to 7-stage pipline
2023-07-25 21:06:44 +08:00
icache.v
[Modified] Switch soc_top&board to axi&xc7a200t
2023-07-20 21:40:21 +08:00
id_stage.v
[Modified] Fix (铸币←me) bug & up to 60MHz
2023-07-23 01:10:46 +08:00
if_stage.v
[Backup] ready for switching to 7-stage pipline
2023-07-25 21:06:44 +08:00
inst_decoder.v
[Modified] Switch soc_top&board to axi&xc7a200t
2023-07-20 21:40:21 +08:00
lsu.v
[Modified] Switch soc_top&board to axi&xc7a200t
2023-07-20 21:40:21 +08:00
mem_stage.v
[Add] add ext_int
2023-07-23 01:59:53 +08:00
mmu.v
[Modified] Switch soc_top&board to axi&xc7a200t
2023-07-20 21:40:21 +08:00
mul_div_lock.v
[Modified] Switch soc_top&board to axi&xc7a200t
2023-07-20 21:40:21 +08:00
mul_div_top.v
[Modified] Switch soc_top&board to axi&xc7a200t
2023-07-20 21:40:21 +08:00
mul.v
[Modified] Switch soc_top&board to axi&xc7a200t
2023-07-20 21:40:21 +08:00
mycpu_core.v
[Backup] ready for switching to 7-stage pipline
2023-07-25 21:06:44 +08:00
mycpu_top.v
[Add] add ext_int
2023-07-23 01:59:53 +08:00
pip_ctrl.v
[Backup] ready for switching to 7-stage pipline
2023-07-25 21:06:44 +08:00
regfile.v
[Modified] Switch soc_top&board to axi&xc7a200t
2023-07-20 21:40:21 +08:00
tlb.v
[Modified] Switch soc_top&board to axi&xc7a200t
2023-07-20 21:40:21 +08:00
tools.v
[Modified] Switch soc_top&board to axi&xc7a200t
2023-07-20 21:40:21 +08:00
uncache.v
[Modified] Switch soc_top&board to axi&xc7a200t
2023-07-20 21:40:21 +08:00
wb_stage.v
[Modified] Switch soc_top&board to axi&xc7a200t
2023-07-20 21:40:21 +08:00