68 lines
1.8 KiB
Verilog
68 lines
1.8 KiB
Verilog
module regfile(
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input clk,
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input reset,
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// READ PORT 1
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input [ 4:0] raddr1,
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output [31:0] rdata1,
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// READ PORT 2
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input [ 4:0] raddr2,
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output [31:0] rdata2,
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// WRITE PORT
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input we, //write enable, HIGH valid
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input [ 4:0] waddr,
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input [31:0] wdata
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);
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reg [31:0] rf[31:0];
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//WRITE
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always @(posedge clk) begin
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if (reset) begin
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rf[ 0] <= 32'b0;
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rf[ 1] <= 32'b0;
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rf[ 2] <= 32'b0;
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rf[ 3] <= 32'b0;
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rf[ 4] <= 32'b0;
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rf[ 5] <= 32'b0;
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rf[ 6] <= 32'b0;
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rf[ 7] <= 32'b0;
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rf[ 8] <= 32'b0;
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rf[ 9] <= 32'b0;
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rf[10] <= 32'b0;
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rf[11] <= 32'b0;
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rf[12] <= 32'b0;
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rf[13] <= 32'b0;
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rf[14] <= 32'b0;
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rf[15] <= 32'b0;
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rf[16] <= 32'b0;
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rf[17] <= 32'b0;
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rf[18] <= 32'b0;
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rf[19] <= 32'b0;
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rf[20] <= 32'b0;
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rf[21] <= 32'b0;
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rf[22] <= 32'b0;
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rf[23] <= 32'b0;
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rf[24] <= 32'b0;
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rf[25] <= 32'b0;
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rf[26] <= 32'b0;
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rf[27] <= 32'b0;
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rf[28] <= 32'b0;
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rf[29] <= 32'b0;
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rf[30] <= 32'b0;
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rf[31] <= 32'b0;
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end
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else if (we) begin
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rf[waddr]<= wdata;
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end
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end
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//READ OUT 1
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assign rdata1 = (raddr1==5'b0 ) ? 32'b0 :
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(raddr1==waddr) & we ? wdata :
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rf[raddr1];
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//READ OUT 2
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assign rdata2 = (raddr2==5'b0 ) ? 32'b0 :
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(raddr2==waddr) & we ? wdata :
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rf[raddr2];
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endmodule |