428 lines
17 KiB
Verilog
428 lines
17 KiB
Verilog
`default_nettype wire
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module axi_ctrl_v5
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#(
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parameter TAG_WD = 21,
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parameter INDEX_WD = 64,
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parameter CACHELINE_WD = 512,
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parameter STAGE_WD = 12
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)
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(
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input clk,
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input reset,
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// icache interface
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input icache_re, // miss
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input [31 :0] icache_raddr, // miss_addr
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output reg [CACHELINE_WD -1:0] icache_cacheline_new,
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input icache_we, // we_back
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input [31 :0] icache_waddr, // waddr
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input [CACHELINE_WD -1:0] icache_cacheline_old, // wback
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output reg icache_refresh,
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// dcache interface
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input dcache_re, // miss
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input [31 :0] dcache_raddr, // miss_addr
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output reg [CACHELINE_WD -1:0] dcache_cacheline_new,
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input dcache_we, // we_back
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input [31 :0] dcache_waddr, // waddr
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input [CACHELINE_WD -1:0] dcache_cacheline_old, // wback
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output reg dcache_refresh, // fin
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// uncache interface
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input uncache_en,
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input [3 :0] uncache_we,
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input [31 :0] uncache_addr,
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input [31 :0] uncache_wdata,
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output reg [31 :0] uncache_rdata,
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output reg uncache_refresh,
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//总线侧接口
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//读地址通道信号
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output reg [3 :0] arid, //读地址ID，用来标志一组写信号
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output reg [31:0] araddr, //读地址，给出一次写突发传输的读地址
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output reg [3 :0] arlen, //突发长度，给出突发传输的次数
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output reg [2 :0] arsize, //突发大小，给出每次突发传输的字节数
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output reg [1 :0] arburst, //突发类型
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output reg [1 :0] arlock, //总线锁信号，可提供操作的原子性
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output reg [3 :0] arcache, //内存类型，表明一次传输是怎样通过系统的
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output reg [2 :0] arprot, //保护类型，表明一次传输的特权级及安全等级
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output reg arvalid, //有效信号，表明此通道的地址控制信号有效
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input arready, //表明"从"可以接收地址和对应的控制信号
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//读数据通道信号
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input [3 :0] rid, //读ID tag
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input [31:0] rdata, //读数据
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input [1 :0] rresp, //读响应，表明读传输的状态
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input rlast, //表明读突发的最后一次传输
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input rvalid, //表明此通道信号有效
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output reg rready, //表明主机能够接收读数据和响应信息
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//写地址通道信号
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output reg [3 :0] awid, //写地址ID，用来标志一组写信号
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output reg [31:0] awaddr, //写地址，给出一次写突发传输的写地址
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output reg [3 :0] awlen, //突发长度，给出突发传输的次数
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output reg [2 :0] awsize, //突发大小，给出每次突发传输的字节数
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output reg [1 :0] awburst, //突发类型
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output reg [1 :0] awlock, //总线锁信号，可提供操作的原子性
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output reg [3 :0] awcache, //内存类型，表明一次传输是怎样通过系统的
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output reg [2 :0] awprot, //保护类型，表明一次传输的特权级及安全等级
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output reg awvalid, //有效信号，表明此通道的地址控制信号有效
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input awready, //表明"从"可以接收地址和对应的控制信号
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//写数据通道信号
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output reg [3 :0] wid, //一次写传输的ID tag
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output reg [31:0] wdata, //写数据
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output reg [3 :0] wstrb, //写数据有效的字节线，用来表明哪8bits数据是有效的
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output reg wlast, //表明此次传输是最后一个突发传输
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output reg wvalid, //写有效，表明此次写有效
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input wready, //表明从机可以接收写数据
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//写响应通道信号
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input [3 :0] bid, //写响应ID tag
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input [1 :0] bresp, //写响应，表明写传输的状态 00为正常，当然可以不理会
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input bvalid, //写响应有效
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output reg bready //表明主机能够接收写响应
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);
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reg [CACHELINE_WD -1:0] icache_rdata_buffer;
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reg [CACHELINE_WD -1:0] icache_wdata_buffer;
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reg [CACHELINE_WD -1:0] dcache_rdata_buffer;
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reg [CACHELINE_WD -1:0] dcache_wdata_buffer;
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reg [31 :0] icache_raddr_buffer;
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reg [31 :0] icache_waddr_buffer;
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reg [31 :0] dcache_raddr_buffer;
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reg [31 :0] dcache_waddr_buffer;
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reg [3 :0] icache_offset;
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reg [3 :0] dcache_offset;
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reg [3 :0] dcache_offset_w;
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reg icache_re_buffer;
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reg dcache_re_buffer;
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reg icache_we_buffer;
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reg dcache_we_buffer;
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reg uncache_en_buffer;
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reg [3 :0] uncache_we_buffer;
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reg [31 :0] uncache_addr_buffer;
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reg [31 :0] uncache_wdata_buffer;
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reg [31 :0] uncache_rdata_buffer;
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reg [STAGE_WD -1:0] stage;
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reg [STAGE_WD -1:0] stage_w;
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always @(posedge clk) begin
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if(reset) begin
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arid <= 4'b0000;
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araddr <= 32'b0;
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arlen <= 4'b0000;
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arsize <= 3'b010;
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arburst <= 2'b01;
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arlock <= 2'b00;
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arcache <= 4'b0000;
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arprot <= 3'b000;
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arvalid <= 1'b0;
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rready <= 1'b0;
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stage <= {{(STAGE_WD-1){1'b0}}, 1'b1};
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icache_refresh <= 0;
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dcache_refresh <= 0;
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icache_cacheline_new <= 0;
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dcache_cacheline_new <= 0;
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uncache_refresh <= 1'b0;
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uncache_rdata <= 32'b0;
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end
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else begin
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case (1'b1)
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stage[0]: begin
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icache_refresh <= 1'b0;
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dcache_refresh <= 1'b0;
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uncache_refresh <= 1'b0;
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icache_re_buffer <= icache_re;
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icache_raddr_buffer <= icache_raddr;
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icache_we_buffer <= icache_we;
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icache_waddr_buffer <= icache_waddr;
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dcache_re_buffer <= dcache_re;
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dcache_raddr_buffer <= dcache_raddr;
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dcache_we_buffer <= dcache_we;
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dcache_waddr_buffer <= dcache_waddr;
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uncache_en_buffer <= uncache_en;
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uncache_we_buffer <= uncache_we;
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uncache_addr_buffer <= uncache_addr;
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uncache_wdata_buffer <= uncache_wdata;
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if (dcache_we|(uncache_en&((|uncache_we)))) begin
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stage <= stage << 1;
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end
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else if (icache_re|dcache_re|(uncache_en&~(|uncache_we))) begin
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stage <= stage << 2;
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end
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end
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stage[1]: begin
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icache_wdata_buffer <= icache_cacheline_old;
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dcache_wdata_buffer <= dcache_cacheline_old;
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if (icache_re_buffer|dcache_re_buffer|(uncache_en_buffer&~(|uncache_we_buffer))) begin
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stage <= stage << 1;
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end
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else begin
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stage <= {1'b0,1'b1,10'b0};
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end
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end
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stage[2]:begin
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if (icache_re_buffer) begin
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arid <= 4'b0;
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araddr <= icache_raddr_buffer;
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arlen <= 4'hf;
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arsize <= 3'b010;
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arvalid <= 1'b1;
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stage <= stage << 1;
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end
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else begin
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stage <= stage << 3;
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end
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end
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stage[3]:begin
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if (arready) begin
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arvalid <= 1'b0;
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araddr <= 32'b0;
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rready <= 1'b1;
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icache_offset <= 4'd0;
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stage <= stage << 1;
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end
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end
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stage[4]:begin
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if (!rlast&rvalid) begin
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icache_rdata_buffer[icache_offset*32+:32] <= rdata;
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icache_offset <= icache_offset + 1'b1;
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end
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else if(rlast&rvalid) begin
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icache_rdata_buffer[icache_offset*32+:32] <= rdata;
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rready <= 1'b0;
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stage <= stage << 1;
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end
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end
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stage[5]:begin
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if (dcache_re_buffer) begin
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arid <= 4'b1;
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araddr <= dcache_raddr_buffer;
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arlen <= 4'hf;
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arsize <= 3'b010;
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arvalid <= 1'b1;
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stage <= stage << 1;
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end
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else if (uncache_en_buffer&~(|uncache_we_buffer)) begin
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arid <= 4'b1;
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araddr <= uncache_addr_buffer;
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arlen <= 4'b0;
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arsize <= 3'b010;
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arvalid <= 1'b1;
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stage <= stage << 3;
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end
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else begin
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stage <= {1'b0,1'b1,10'b0};
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end
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end
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stage[6]:begin
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if (arready) begin
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arvalid <= 1'b0;
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araddr <= 32'b0;
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rready <= 1'b1;
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dcache_offset <= 4'd0;
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stage <= stage << 1;
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end
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end
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stage[7]:begin
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if (!rlast&rvalid) begin
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dcache_rdata_buffer[dcache_offset*32+:32] <= rdata;
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dcache_offset <= dcache_offset + 1'b1;
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end
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else if (rlast&rvalid) begin
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dcache_rdata_buffer[dcache_offset*32+:32] <= rdata;
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rready <= 1'b0;
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stage <= {1'b0,1'b1,10'b0};
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end
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end
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stage[8]:begin
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if (arready) begin
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arvalid <= 1'b0;
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araddr <= 32'b0;
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rready <= 1'b1;
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stage <= stage << 1;
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end
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end
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stage[9]:begin
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if (rvalid) begin
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uncache_rdata_buffer <= rdata;
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rready <= 1'b0;
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stage <= {1'b0,1'b1,10'b0};
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end
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end
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stage[10]:begin
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if (stage_w[10]|stage_w[0]) begin
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stage <= stage << 1;
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end
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end
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stage[11]:begin
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if (icache_re_buffer) begin
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icache_refresh <= 1'b1;
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icache_cacheline_new <= icache_rdata_buffer;
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end
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if (dcache_re_buffer) begin
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dcache_refresh <= 1'b1;
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dcache_cacheline_new <= dcache_rdata_buffer;
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end
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if (uncache_en_buffer) begin
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uncache_refresh <= 1'b1;
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uncache_rdata <= uncache_rdata_buffer;
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end
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stage <= 0;
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end
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default:begin
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stage <= {{(STAGE_WD-1){1'b0}}, 1'b1};
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icache_refresh <= 1'b0;
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dcache_refresh <= 1'b0;
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uncache_refresh <= 1'b0;
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end
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endcase
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end
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end
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always @ (posedge clk) begin
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if (reset) begin
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awid <= 4'b0001;
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awaddr <= 32'b0;
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awlen <= 4'b0000;
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awsize <= 3'b010;
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awburst <= 2'b01;
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awlock <= 2'b00;
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awcache <= 4'b0000;
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awprot <= 3'b000;
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awvalid <= 1'b0;
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wid <= 4'b0001;
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wdata <= 32'b0;
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wstrb <= 4'b0000;
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wlast <= 1'b0;
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wvalid <= 1'b0;
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bready <= 1'b0;
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stage_w <= {{(STAGE_WD-1){1'b0}}, 1'b1};
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end
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else begin
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case (1'b1)
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stage_w[0]:begin
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if (stage[1]) begin
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if (dcache_we_buffer) begin
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awid <= 4'b1;
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awaddr <= dcache_waddr_buffer;
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awlen <= 4'hf;
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awsize <= 3'b010;
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awvalid <= 1'b1;
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wstrb <= 4'b1111;
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wlast <= 1'b0;
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bready <= 1'b1;
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dcache_offset_w <= 4'b0;
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stage_w <= stage_w << 1;
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end
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else if (|uncache_we_buffer) begin // write
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awid <= 4'b1;
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awaddr <= uncache_addr_buffer;
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awlen <= 4'b0;
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case (uncache_we_buffer)
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4'b0001,4'b0010,4'b0100,4'b1000:begin
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awsize <= 3'b000;
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wstrb <= uncache_we_buffer;
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end
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4'b0011,4'b1100:begin
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awsize <= 3'b001;
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wstrb <= uncache_we_buffer;
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end
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4'b1111:begin
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awsize <= 3'b010;
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wstrb <= uncache_we_buffer;
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end
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default:begin
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awsize <= 3'b010;
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wstrb <= uncache_we_buffer;
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end
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endcase
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awvalid <= 1'b1;
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wlast <= 1'b0;
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bready <= 1'b1;
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stage_w <= stage_w << 4;
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end
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end
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end
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stage_w[1]:begin
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if (awready) begin
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awvalid <= 1'b0;
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awaddr <= 32'b0;
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wdata <= dcache_wdata_buffer[dcache_offset_w*32+:32];
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wvalid <= 1'b1;
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wlast <= dcache_offset_w == 4'b1111 ? 1'b1 : 1'b0;
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dcache_offset_w <= dcache_offset_w + 1'b1;
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if (dcache_offset_w == 4'b1111) begin
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stage_w <= stage_w << 1;
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end
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end
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end
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stage_w[2]:begin
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if (wready) begin
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wdata <= 32'b0;
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wvalid <= 1'b0;
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wlast <= 1'b0;
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stage_w <= stage_w << 1;
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end
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end
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stage_w[3]:begin
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if (bvalid) begin
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bready <= 1'b0;
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stage_w <= {1'b0,1'b1,{10{1'b0}}};
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end
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end
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stage_w[4]:begin
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if (awready) begin
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awvalid <= 1'b0;
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awaddr <= 32'b0;
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wdata <= uncache_wdata_buffer;
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wvalid <= 1'b1;
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wlast <= 1'b1;
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stage_w <= stage_w << 1;
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end
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end
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stage_w[5]:begin
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if (wready) begin
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wdata <= 32'b0;
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wvalid <= 1'b0;
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wlast <= 1'b0;
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stage_w <= stage_w << 1;
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end
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end
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stage_w[6]:begin
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if (bvalid) begin
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bready <= 1'b0;
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stage_w <= {1'b0,1'b1,{10{1'b0}}};
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end
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end
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stage_w[10]:begin
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if (stage[11]) begin
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stage_w <= {{(STAGE_WD-1){1'b0}}, 1'b1};
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end
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end
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default:begin
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stage_w <= {{(STAGE_WD-1){1'b0}}, 1'b1};
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end
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endcase
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end
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end
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endmodule |