156 lines
4.8 KiB
Verilog
156 lines
4.8 KiB
Verilog
module mycpu_top
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#(
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parameter FS_TO_DS_BUS_WD = 65,
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parameter DS_TO_ES_BUS_WD = 301,
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parameter ES_TO_MS_BUS_WD = 271,
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parameter MS_TO_WS_BUS_WD = 102,
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parameter WS_TO_RF_BUS_WD = 38,
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parameter MS_TO_ES_BUS_WD = 38,
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parameter WS_TO_ES_BUS_WD = 38,
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parameter BR_BUS_WD = 33
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)
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(
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input clk,
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input resetn,
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output timer_int,
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// inst sram interface
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output inst_sram_en,
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output [ 3:0] inst_sram_we,
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output [31:0] inst_sram_addr,
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output [31:0] inst_sram_wdata,
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input [31:0] inst_sram_rdata,
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// data sram interface
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output data_sram_en,
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output [ 3:0] data_sram_we,
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output [31:0] data_sram_addr,
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output [31:0] data_sram_wdata,
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input [31:0] data_sram_rdata,
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// trace debug interface
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output [31:0] debug_wb_pc,
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output [ 3:0] debug_wb_rf_we,
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output [ 4:0] debug_wb_rf_wnum,
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output [31:0] debug_wb_rf_wdata
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);
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reg reset;
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always @(posedge clk) reset <= ~resetn;
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wire [FS_TO_DS_BUS_WD -1:0] fs_to_ds_bus;
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wire [DS_TO_ES_BUS_WD -1:0] ds_to_es_bus;
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wire [ES_TO_MS_BUS_WD -1:0] es_to_ms_bus;
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wire [MS_TO_WS_BUS_WD -1:0] ms_to_ws_bus;
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wire [WS_TO_RF_BUS_WD -1:0] ws_to_rf_bus;
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wire [MS_TO_ES_BUS_WD -1:0] ms_to_es_bus;
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wire [WS_TO_ES_BUS_WD -1:0] ws_to_es_bus;
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wire [BR_BUS_WD -1:0] br_bus;
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wire flush;
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wire stallreq_es;
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wire stallreq_ds;
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wire [ 5:0] stall;
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wire except_en;
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wire [31:0] new_pc;
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wire [ 1:0] csr_plv;
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wire csr_has_int;
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if_stage if_stage(
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.clk (clk ),
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.reset (reset ),
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.flush (flush ),
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.stall (stall ),
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.new_pc (new_pc ),
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.timer_int (timer_int ),
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.fs_to_ds_bus (fs_to_ds_bus ),
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.br_bus (br_bus ),
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.inst_sram_en (inst_sram_en ),
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.inst_sram_we (inst_sram_we ),
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.inst_sram_addr (inst_sram_addr ),
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.inst_sram_wdata (inst_sram_wdata )
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);
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id_stage id_stage(
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.clk (clk ),
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.reset (reset ),
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.flush (flush ),
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.stall (stall ),
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.br_taken (br_bus[32] ),
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.stallreq_ds (stallreq_ds ),
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.fs_to_ds_bus (fs_to_ds_bus ),
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.pc_valid (inst_sram_en ),
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.inst_sram_rdata (inst_sram_rdata ),
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.csr_plv (csr_plv ),
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.csr_has_int (csr_has_int ),
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.ws_to_rf_bus (ws_to_rf_bus ),
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.ds_to_es_bus (ds_to_es_bus )
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);
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exe_stage exe_stage(
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.clk (clk ),
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.reset (reset ),
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.flush (flush ),
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.stall (stall ),
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.stallreq_es (stallreq_es ),
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.ds_to_es_bus (ds_to_es_bus ),
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.es_to_ms_bus (es_to_ms_bus ),
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.ms_to_es_bus (ms_to_es_bus ),
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.ws_to_es_bus (ws_to_es_bus ),
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.br_bus (br_bus ),
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.data_sram_en (data_sram_en ),
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.data_sram_we (data_sram_we ),
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.data_sram_addr (data_sram_addr ),
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.data_sram_wdata (data_sram_wdata )
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);
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mem_stage mem_stage(
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.clk (clk ),
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.reset (reset ),
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.flush (flush ),
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.stall (stall ),
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.except_en (except_en ),
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.new_pc (new_pc ),
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.csr_plv (csr_plv ),
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.csr_has_int (csr_has_int ),
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.es_to_ms_bus (es_to_ms_bus ),
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.ms_to_es_bus (ms_to_es_bus ),
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.ms_to_ws_bus (ms_to_ws_bus ),
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.data_sram_rdata (data_sram_rdata )
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);
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wb_stage wb_stage(
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.clk (clk ),
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.reset (reset ),
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.flush (flush ),
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.stall (stall ),
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.ms_to_ws_bus (ms_to_ws_bus ),
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.ws_to_rf_bus (ws_to_rf_bus ),
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.ws_to_es_bus (ws_to_es_bus ),
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.debug_wb_pc (debug_wb_pc ),
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.debug_wb_rf_we (debug_wb_rf_we ),
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.debug_wb_rf_wnum (debug_wb_rf_wnum ),
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.debug_wb_rf_wdata (debug_wb_rf_wdata)
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);
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pip_ctrl pip_ctrl(
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.reset (reset ),
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.except_en (except_en ),
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.stallreq_ds (stallreq_ds ),
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.stallreq_es (stallreq_es ),
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.stallreq_axi (1'b0 ), // TODO!
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.flush (flush ),
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.stall (stall )
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);
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endmodule |