63 lines
2.3 KiB
Verilog
63 lines
2.3 KiB
Verilog
`include "mycpu.v"
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module forward(
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input clk ,
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input reset ,
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input [`DS_TO_FW_BUS_WD -1:0] ds_to_fw_bus,
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input [`ES_TO_FW_BUS_WD -1:0] es_to_fw_bus,
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input [`MS_TO_FW_BUS_WD -1:0] ms_to_fw_bus,
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output [`FW_TO_ES_BUS_WD -1:0] fw_to_es_bus
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);
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reg [`DS_TO_FW_BUS_WD -1:0] ds_to_fw_bus_r;
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reg [`ES_TO_FW_BUS_WD -1:0] es_to_fw_bus_r;
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reg [`MS_TO_FW_BUS_WD -1:0] ms_to_fw_bus_r;
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wire [4:0] ds_rf_raddr1;
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wire [4:0] ds_rf_raddr2;
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wire [4:0] es_rf_raddr2;
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wire [4:0] es_dest;
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wire [4:0] ms_dest;
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wire es_mem_we;
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wire es_reg_we;
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wire ms_reg_we;
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wire src1_is_es_dest;
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wire src1_is_ms_dest;
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wire src2_is_es_dest;
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wire src2_is_ms_dest;
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wire data_is_rf_wdata;
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assign {ds_rf_raddr1, ds_rf_raddr2 } = ds_to_fw_bus_r;
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assign {es_rf_rdata2, es_dest, es_reg_we, es_mem_we} = es_to_fw_bus_r;
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assign {ms_dest , ms_reg_we} = ms_to_fw_bus_r;
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assign fw_to_es_bus = {src1_is_es_dest , //4:4
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src1_is_ms_dest , //3:3
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src2_is_es_dest , //2:2
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src2_is_ms_dest , //1:1
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data_is_rf_wdata //0:0
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};
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always @(posedge clk) begin
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if(reset) begin
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ds_to_fw_bus_r <= 0;
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es_to_fw_bus_r <= 0;
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ms_to_fw_bus_r <= 0;
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end
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else begin
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ds_to_fw_bus_r <= ds_to_fw_bus;
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es_to_fw_bus_r <= es_to_fw_bus;
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ms_to_fw_bus_r <= ms_to_fw_bus;
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end
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end
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assign src1_is_ms_dest = ms_reg_we && (ms_dest != 5'b0) && (es_dest != ds_rf_raddr1) && (ms_dest == ds_rf_raddr1);
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assign src1_is_es_dest = es_reg_we && (es_dest != 5'b0) && (es_dest == ds_rf_raddr1);
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assign src2_is_ms_dest = ms_reg_we && (ms_dest != 5'b0) && (es_dest != ds_rf_raddr2) && (ms_dest == ds_rf_raddr2);
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assign src2_is_es_dest = es_reg_we && (es_dest != 5'b0) && (es_dest == ds_rf_raddr2);
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assign data_is_rf_wdata = ms_reg_we && (ms_dest != 5'b0) && (ms_dest == es_rf_raddr2) && es_mem_we;
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endmodule |