xilinx.com xci unknown 1.0 axi_ram 4096 32 0 0 0 32 100000000 1 1 0 0 0 0 0 1 1 4 0 256 2 1 2 1 0.000 AXI4 READ_WRITE 0 0 1 0 0 32 0 0 0 32 100000000 1 1 0 0 0 0 0 1 1 4 0 256 2 1 2 1 0.000 AXI4 READ_WRITE 0 0 1 0 0 OTHER NONE 8192 32 1 OTHER NONE 8192 32 1 100000000 0 0.000 0 18 18 1 4 0 1 8 1 0 256 NONE 0 0 0 ./ 0 0 0 0 0 0 0 0 Estimated Power for IP : 21.018106 mW artix7 1 1 1 0 0 0 0 0 0 0 0 1 0 0 0 0 axi_ram.mem axi_ram.mif 1 1 1 0 1 262144 262144 1 1 32 32 0 0 CE CE ALL 0 1 1 1 0 0 0 4 4 262144 262144 READ_FIRST READ_FIRST 32 32 artix7 4 Memory_Slave AXI4_Full false Minimum_Area true 8 NONE ../../../../../cdp_ede_local/mycpu_env/func/obj/inst_ram.coe ALL axi_ram false false false false false false false false false Use_ENA_Pin Use_ENB_Pin Single_Bit_Error_Injection true AXI4 true no_mem_loaded Simple_Dual_Port_RAM READ_FIRST READ_FIRST 0 0 BRAM 0 100 100 50 100 100 0 8kx2 false false 1 1 32 32 false false false false 0 false false CE CE ASYNC true true false false false false true 262144 32 32 No_ECC false false false Stand_Alone artix7 xc7a200t fbg676 VERILOG MIXED -1 TRUE TRUE IP_Flow 4 TRUE . . 2019.2 OUT_OF_CONTEXT