diff --git a/lacpu/rtl/cpu/cpu_top.v b/lacpu/rtl/cpu/cpu_top.v
index 931025e..3fd352c 100755
--- a/lacpu/rtl/cpu/cpu_top.v
+++ b/lacpu/rtl/cpu/cpu_top.v
@@ -1,4 +1,4 @@
-`include "mycpu.h"
+`include "mycpu.v"
 
 module mycpu_top(
     input         clk,
diff --git a/lacpu/rtl/cpu/exe_stage.v b/lacpu/rtl/cpu/exe_stage.v
index 9e36989..6c6509f 100755
--- a/lacpu/rtl/cpu/exe_stage.v
+++ b/lacpu/rtl/cpu/exe_stage.v
@@ -1,4 +1,4 @@
-`include "mycpu.h"
+`include "mycpu.v"
 
 module exe_stage(
     input                          clk           ,
diff --git a/lacpu/rtl/cpu/id_stage.v b/lacpu/rtl/cpu/id_stage.v
index a11cc2a..3e0570a 100755
--- a/lacpu/rtl/cpu/id_stage.v
+++ b/lacpu/rtl/cpu/id_stage.v
@@ -1,4 +1,4 @@
-`include "mycpu.h"
+`include "mycpu.v"
 
 // 译码阶段
 module id_stage(
diff --git a/lacpu/rtl/cpu/if_stage.v b/lacpu/rtl/cpu/if_stage.v
index 39410f9..a985ee3 100755
--- a/lacpu/rtl/cpu/if_stage.v
+++ b/lacpu/rtl/cpu/if_stage.v
@@ -1,4 +1,4 @@
-`include "mycpu.h"
+`include "mycpu.v"
 
 // 取指阶段
 module if_stage(
diff --git a/lacpu/rtl/cpu/mem_stage.v b/lacpu/rtl/cpu/mem_stage.v
index 0df79d2..b7682a4 100755
--- a/lacpu/rtl/cpu/mem_stage.v
+++ b/lacpu/rtl/cpu/mem_stage.v
@@ -1,4 +1,4 @@
-`include "mycpu.h"
+`include "mycpu.v"
 
 module mem_stage(
     input                          clk           ,
diff --git a/lacpu/rtl/cpu/wb_stage.v b/lacpu/rtl/cpu/wb_stage.v
index 39515fd..f47cac3 100755
--- a/lacpu/rtl/cpu/wb_stage.v
+++ b/lacpu/rtl/cpu/wb_stage.v
@@ -1,4 +1,4 @@
-`include "mycpu.h"
+`include "mycpu.v"
 
 module wb_stage(
     input                           clk           ,
diff --git a/lacpu/run_vivado/la32r/la32r.xpr b/lacpu/run_vivado/la32r/la32r.xpr
index 6adc38f..3a30709 100644
--- a/lacpu/run_vivado/la32r/la32r.xpr
+++ b/lacpu/run_vivado/la32r/la32r.xpr
@@ -61,6 +61,13 @@
           <Attr Name="UsedIn" Val="simulation"/>
         </FileInfo>
       </File>
+      <File Path="$PPRDIR/../../rtl/cpu/mycpu.v">
+        <FileInfo>
+          <Attr Name="UsedIn" Val="synthesis"/>
+          <Attr Name="UsedIn" Val="implementation"/>
+          <Attr Name="UsedIn" Val="simulation"/>
+        </FileInfo>
+      </File>
       <File Path="$PPRDIR/../../rtl/cpu/cpu_top.v">
         <FileInfo>
           <Attr Name="UsedIn" Val="synthesis"/>