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[Modified] change div divu ip position form soc_top to exe_stage

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包焕垲
2023-06-06 11:30:52 +08:00
parent f660bd337b
commit df981a178c
3 changed files with 47 additions and 119 deletions
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38
lacpu/rtl/cpu/cpu_top.v
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@@ -15,24 +15,6 @@ module mycpu_top(
output [31:0] data_sram_addr, output [31:0] data_sram_addr,
output [31:0] data_sram_wdata, output [31:0] data_sram_wdata,
input [31:0] data_sram_rdata, input [31:0] data_sram_rdata,
//div
output [31:0] div_divisor_data,
output div_divisor_valid,
input div_divisor_ready,
output [31:0] div_dividend_data,
output div_dividend_valid,
input div_dividend_ready,
input div_dout_valid,
input [63:0] div_dout_data,
//divu
output [31:0] divu_divisor_data,
output divu_divisor_valid,
input divu_divisor_ready,
output [31:0] divu_dividend_data,
output divu_dividend_valid,
input divu_dividend_ready,
input divu_dout_valid,
input [63:0] divu_dout_data,
// trace debug interface // trace debug interface
output [31:0] debug_wb_pc, output [31:0] debug_wb_pc,
output [ 3:0] debug_wb_rf_wen, output [ 3:0] debug_wb_rf_wen,
@@ -134,25 +116,7 @@ module mycpu_top(
.data_sram_en (data_sram_en ), .data_sram_en (data_sram_en ),
.data_sram_wen (data_sram_wen ), .data_sram_wen (data_sram_wen ),
.data_sram_addr (data_sram_addr ), .data_sram_addr (data_sram_addr ),
.data_sram_wdata(data_sram_wdata), .data_sram_wdata(data_sram_wdata)
//div
.div_divisor_data (div_divisor_data ),
.div_divisor_valid (div_divisor_valid ),
.div_divisor_ready (div_divisor_ready ),
.div_dividend_data (div_dividend_data ),
.div_dividend_valid (div_dividend_valid ),
.div_dividend_ready (div_dividend_ready ),
.div_dout_valid (div_dout_valid ),
.div_dout_data (div_dout_data ),
//divu
.divu_divisor_data (divu_divisor_data ),
.divu_divisor_valid (divu_divisor_valid ),
.divu_divisor_ready (divu_divisor_ready ),
.divu_dividend_data (divu_dividend_data ),
.divu_dividend_valid(divu_dividend_valid),
.divu_dividend_ready(divu_dividend_ready),
.divu_dout_valid (divu_dout_valid ),
.divu_dout_data (divu_dout_data )
); );
// MEM stage // MEM stage
mem_stage mem_stage( mem_stage mem_stage(

65
lacpu/rtl/cpu/exe_stage.v
View File

@@ -28,25 +28,7 @@ module exe_stage(
//to lu //to lu
output [`ES_TO_LU_BUS_WD -1:0] es_to_lu_bus , output [`ES_TO_LU_BUS_WD -1:0] es_to_lu_bus ,
//from lu //from lu
input lu_to_es_bus , input lu_to_es_bus
//div
output [31:0] div_divisor_data ,
output div_divisor_valid ,
input div_divisor_ready ,
output [31:0] div_dividend_data ,
output div_dividend_valid ,
input div_dividend_ready ,
input div_dout_valid ,
input [63:0] div_dout_data ,
//divu
output [31:0] divu_divisor_data ,
output divu_divisor_valid ,
input divu_divisor_ready ,
output [31:0] divu_dividend_data ,
output divu_dividend_valid ,
input divu_dividend_ready ,
input divu_dout_valid ,
input [63:0] divu_dout_data
); );
reg es_valid ; reg es_valid ;
@@ -136,6 +118,25 @@ module exe_stage(
wire [31:0] div_mod_result; wire [31:0] div_mod_result;
//div
wire [31:0] div_divisor_data;
wire div_divisor_valid;
wire div_divisor_ready;
wire [31:0] div_dividend_data;
wire div_dividend_valid;
wire div_dividend_ready;
wire div_dout_valid;
wire [63:0] div_dout_data;
//divu
wire [31:0] divu_divisor_data;
wire divu_divisor_valid;
wire divu_divisor_ready;
wire [31:0] divu_dividend_data;
wire divu_dividend_valid;
wire divu_dividend_ready;
wire divu_dout_valid;
wire [63:0] divu_dout_data;
assign es_result = is_div_mod ? div_mod_result : es_alu_result; assign es_result = is_div_mod ? div_mod_result : es_alu_result;
assign es_to_ms_bus = {br_target , //120:89 assign es_to_ms_bus = {br_target , //120:89
@@ -274,6 +275,32 @@ module exe_stage(
end end
end end
//div
div div(
.aclk (clk ),
.s_axis_divisor_tdata (div_divisor_data ),
.s_axis_divisor_tvalid (div_divisor_valid ),
.s_axis_divisor_tready (div_divisor_ready ),
.s_axis_dividend_tdata (div_dividend_data ),
.s_axis_dividend_tvalid (div_dividend_valid ),
.s_axis_dividend_tready (div_dividend_ready ),
.m_axis_dout_tvalid (div_dout_valid ),
.m_axis_dout_tdata (div_dout_data )
);
//divu
divu divu(
.aclk (clk ),
.s_axis_divisor_tdata (divu_divisor_data ),
.s_axis_divisor_tvalid (divu_divisor_valid ),
.s_axis_divisor_tready (divu_divisor_ready ),
.s_axis_dividend_tdata (divu_dividend_data ),
.s_axis_dividend_tvalid (divu_dividend_valid),
.s_axis_dividend_tready (divu_dividend_ready),
.m_axis_dout_tvalid (divu_dout_valid ),
.m_axis_dout_tdata (divu_dout_data )
);
assign div_divisor_valid = div_divisor_valid_r; assign div_divisor_valid = div_divisor_valid_r;
assign div_dividend_valid = div_dividend_valid_r; assign div_dividend_valid = div_dividend_valid_r;
assign divu_divisor_valid = divu_divisor_valid_r; assign divu_divisor_valid = divu_divisor_valid_r;

63
lacpu/rtl/soc_lite_top.v
View File

@@ -33,24 +33,6 @@ module soc_lite_top
wire [31:0] cpu_data_addr; wire [31:0] cpu_data_addr;
wire [31:0] cpu_data_wdata; wire [31:0] cpu_data_wdata;
wire [31:0] cpu_data_rdata; wire [31:0] cpu_data_rdata;
//div
wire [31:0] div_divisor_data;
wire div_divisor_valid;
wire div_divisor_ready;
wire [31:0] div_dividend_data;
wire div_dividend_valid;
wire div_dividend_ready;
wire div_dout_valid;
wire [63:0] div_dout_data;
//divu
wire [31:0] divu_divisor_data;
wire divu_divisor_valid;
wire divu_divisor_ready;
wire [31:0] divu_dividend_data;
wire divu_dividend_valid;
wire divu_dividend_ready;
wire divu_dout_valid;
wire [63:0] divu_dout_data;
//cpu //cpu
mycpu_top cpu( mycpu_top cpu(
@@ -69,25 +51,6 @@ module soc_lite_top
.data_sram_wdata (cpu_data_wdata), .data_sram_wdata (cpu_data_wdata),
.data_sram_rdata (cpu_data_rdata), .data_sram_rdata (cpu_data_rdata),
//div
.div_divisor_data (div_divisor_data ),
.div_divisor_valid (div_divisor_valid ),
.div_divisor_ready (div_divisor_ready ),
.div_dividend_data (div_dividend_data ),
.div_dividend_valid (div_dividend_valid ),
.div_dividend_ready (div_dividend_ready ),
.div_dout_valid (div_dout_valid ),
.div_dout_data (div_dout_data ),
//divu
.divu_divisor_data (divu_divisor_data ),
.divu_divisor_valid (divu_divisor_valid ),
.divu_divisor_ready (divu_divisor_ready ),
.divu_dividend_data (divu_dividend_data ),
.divu_dividend_valid(divu_dividend_valid),
.divu_dividend_ready(divu_dividend_ready),
.divu_dout_valid (divu_dout_valid ),
.divu_dout_data (divu_dout_data ),
//debug //debug
.debug_wb_pc (debug_wb_pc ), .debug_wb_pc (debug_wb_pc ),
.debug_wb_rf_wen (debug_wb_rf_wen ), .debug_wb_rf_wen (debug_wb_rf_wen ),
@@ -121,32 +84,6 @@ module soc_lite_top
.dina (cpu_data_wdata ), //31:0 .dina (cpu_data_wdata ), //31:0
.douta (cpu_data_rdata ) //31:0 .douta (cpu_data_rdata ) //31:0
); );
//div
div div(
.aclk (cpu_clk ),
.s_axis_divisor_tdata (div_divisor_data ),
.s_axis_divisor_tvalid (div_divisor_valid ),
.s_axis_divisor_tready (div_divisor_ready ),
.s_axis_dividend_tdata (div_dividend_data ),
.s_axis_dividend_tvalid (div_dividend_valid ),
.s_axis_dividend_tready (div_dividend_ready ),
.m_axis_dout_tvalid (div_dout_valid ),
.m_axis_dout_tdata (div_dout_data )
);
//divu
divu divu(
.aclk (cpu_clk ),
.s_axis_divisor_tdata (divu_divisor_data ),
.s_axis_divisor_tvalid (divu_divisor_valid ),
.s_axis_divisor_tready (divu_divisor_ready ),
.s_axis_dividend_tdata (divu_dividend_data ),
.s_axis_dividend_tvalid (divu_dividend_valid),
.s_axis_dividend_tready (divu_dividend_ready),
.m_axis_dout_tvalid (divu_dout_valid ),
.m_axis_dout_tdata (divu_dout_data )
);
`endif `endif
endmodule endmodule