diff --git a/lacpu/rtl/mycpu/exe_stage.v b/lacpu/rtl/mycpu/exe_stage.v index 3ee631e..1b477a8 100644 --- a/lacpu/rtl/mycpu/exe_stage.v +++ b/lacpu/rtl/mycpu/exe_stage.v @@ -189,7 +189,7 @@ module exe_stage wire csr_cancel; reg csr_cancel_reg; - assign csr_cancel = /*flush ? 1'b0 :*/ |csr_vec[31:0] | excp_adef;// TODO! + assign csr_cancel = /*flush ? 1'b0 :*/ |csr_vec[31:0] | excp_adef;// TODO? always @ (posedge clk) begin if (reset) begin diff --git a/lacpu/rtl/mycpu/id_stage.v b/lacpu/rtl/mycpu/id_stage.v index 1e63207..59f1f30 100644 --- a/lacpu/rtl/mycpu/id_stage.v +++ b/lacpu/rtl/mycpu/id_stage.v @@ -29,8 +29,8 @@ module id_stage reg [31:0] inst_r; reg stall_flag; - reg [ 6:0] ex_load_buffer; - reg ex_csr_buffer; + reg [ 6:0] es_load_buffer; + reg es_csr_buffer; wire br_flush; wire [31:0] ds_pc; @@ -72,10 +72,10 @@ module id_stage wire [31:0] rj_value; wire [31:0] rkd_value; - wire [ 4:0] ex_rf_waddr; - wire ex_is_load; - wire ex_is_csr; - wire ex_rf_we; + wire [ 4:0] es_dest; + wire es_is_load; + wire es_is_csr; + wire es_reg_we; wire stallreq_load; wire stallreq_csr; @@ -153,11 +153,11 @@ module id_stage always @ (posedge clk) begin if (reset) begin - inst_r <= 32'b0; + inst_r <= 64'b0; stall_flag <= 1'b0; end else if (flush) begin - inst_r <= 32'b0; + inst_r <= 64'b0; stall_flag <= 1'b0; end //if not stall, get inst from inst_sram @@ -227,31 +227,31 @@ module id_stage always @ (posedge clk) begin if (reset) begin - ex_load_buffer <= 7'b0; - ex_csr_buffer <= 1'b0; + es_load_buffer <= 7'b0; + es_csr_buffer <= 1'b0; end else if (flush) begin - ex_load_buffer <= 7'b0; - ex_csr_buffer <= 1'b0; + es_load_buffer <= 7'b0; + es_csr_buffer <= 1'b0; end else if (stall[2]&(!stall[3])) begin - ex_load_buffer <= 7'b0; - ex_csr_buffer <= 1'b0; + es_load_buffer <= 7'b0; + es_csr_buffer <= 1'b0; end else if (!stall[2]) begin - ex_load_buffer <= {|load_op, rf_we, rf_waddr}; - ex_csr_buffer <= |csr_op; + es_load_buffer <= {|load_op, reg_we, dest}; + es_csr_buffer <= |csr_op; end end - assign {ex_is_load, - ex_rf_we, - ex_rf_waddr - } = ex_load_buffer; - assign ex_is_csr = ex_csr_buffer; + assign {es_is_load, + es_reg_we, + es_dest + } = es_load_buffer; + assign es_is_csr = es_csr_buffer; //ex段为load指令，且发生数据相关时，id段需要被暂停 - assign stallreq_load = ex_is_load & ex_rf_we & ((ex_rf_waddr==rj_value & rj_value!=0)|(ex_rf_waddr==rkd_value & rkd_value!=0)); - assign stallreq_csr = ex_is_csr & ex_rf_we & ((ex_rf_waddr==rj_value & rj_value!=0)|(ex_rf_waddr==rkd_value & rkd_value!=0)); + assign stallreq_load = es_is_load & es_reg_we & ((es_dest==rj & rj!=0)|(es_dest==rkd & rkd!=0)); + assign stallreq_csr = es_is_csr & es_reg_we & ((es_dest==rj & rj!=0)|(es_dest==rkd & rkd!=0)); assign stallreq_ds = stallreq_load | stallreq_csr; endmodule \ No newline at end of file diff --git a/lacpu/rtl/mycpu/mem_stage.v b/lacpu/rtl/mycpu/mem_stage.v index ac8675c..10ca65a 100644 --- a/lacpu/rtl/mycpu/mem_stage.v +++ b/lacpu/rtl/mycpu/mem_stage.v @@ -79,7 +79,7 @@ module mem_stage assign ms_to_es_bus = {reg_we, dest, - ms_final_result + es_result }; assign ms_to_ws_bus = {reg_we ,//101:101 diff --git a/lacpu/rtl/xilinx_ip/clk_pll/clk_pll.xci b/lacpu/rtl/xilinx_ip/clk_pll/clk_pll.xci index be1ed15..0b825e4 100644 --- a/lacpu/rtl/xilinx_ip/clk_pll/clk_pll.xci +++ b/lacpu/rtl/xilinx_ip/clk_pll/clk_pll.xci @@ -98,17 +98,17 @@ 100.0 0000 0000 - 45.00000 + 60.00000 0000 0000 - 90.00000 + 100.00000 BUFG 50.0 false - 45.00000 + 60.00000 0.000 50.000 - 45.000 + 60.000 0.000 1 0000 @@ -117,10 +117,10 @@ BUFG 50.0 false - 90.00000 + 100.00000 0.000 50.000 - 90.000 + 100.000 0.000 1 1 @@ -203,12 +203,12 @@ din 0000 1 - 0.5 - 0.45 - 0.45 - 0.45 - 0.45 - 0.45 + 0.6 + 0.6 + 0.6 + 0.6 + 0.6 + 0.6 dout drdy dwe @@ -251,11 +251,11 @@ FALSE 10.000 10.000 - 20.000 + 15.000 0.500 0.000 FALSE - 10 + 9 0.500 0.000 FALSE @@ -292,8 +292,8 @@ 2 Output Output Phase Duty Cycle Pk-to-Pk Phase Clock Freq (MHz) (degrees) (%) Jitter (ps) Error (ps) - _cpu_clk__45.00000______0.000______50.0______163.238____105.461 - timer_clk__90.00000______0.000______50.0______140.709____105.461 + _cpu_clk__60.00000______0.000______50.0______153.276____105.461 + timer_clk__100.00000______0.000______50.0______137.681____105.461 no_CLK_OUT3_output no_CLK_OUT4_output no_CLK_OUT5_output @@ -414,20 +414,20 @@ 100.0 0.010 BUFG - 163.238 + 153.276 false 105.461 50.000 - 45.000 + 60.000 0.000 1 true BUFG - 140.709 + 137.681 false 105.461 50.000 - 90.000 + 100.000 0.000 1 true @@ -530,11 +530,11 @@ false 10.000 10.000 - 20 + 15 0.500 0.000 false - 10 + 9 0.500 0.000 false diff --git a/lacpu/run_vivado/la32r/la32r.xpr b/lacpu/run_vivado/la32r/la32r.xpr index d0e6d16..33d2b94 100644 --- a/lacpu/run_vivado/la32r/la32r.xpr +++ b/lacpu/run_vivado/la32r/la32r.xpr @@ -36,13 +36,13 @@