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[Modified] meet time limit

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包焕垲
2023-05-12 22:14:46 +08:00
parent 3228082f83
commit cf7d106af0
5 changed files with 62 additions and 48 deletions
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4
lacpu/rtl/cpu/cpu_top.v
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@@ -86,8 +86,6 @@ module mycpu_top(
//to ms
.es_to_ms_valid (es_to_ms_valid ),
.es_to_ms_bus (es_to_ms_bus ),
//to fs
.br_bus (br_bus ),
// data sram interface
.data_sram_en (data_sram_en ),
.data_sram_wen (data_sram_wen ),
@@ -107,6 +105,8 @@ module mycpu_top(
//to ws
.ms_to_ws_valid (ms_to_ws_valid ),
.ms_to_ws_bus (ms_to_ws_bus ),
//to fs
.br_bus (br_bus ),
//from data-sram
.data_sram_rdata(data_sram_rdata)
);

32
lacpu/rtl/cpu/exe_stage.v
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@@ -12,8 +12,6 @@ module exe_stage(
//to ms
output es_to_ms_valid,
output [`ES_TO_MS_BUS_WD -1:0] es_to_ms_bus ,
//to fs
output [`BR_BUS_WD -1:0] br_bus ,
// data sram interface
output data_sram_en ,
output [ 3:0] data_sram_wen ,
@@ -59,7 +57,6 @@ module exe_stage(
es_pc //31 :0
} = ds_to_es_bus_r;
wire br_taken;
wire [31:0] br_target;
wire [31:0] es_alu_src1 ;
@@ -70,14 +67,18 @@ module exe_stage(
wire es_Overflow ;
wire es_Zero ;
assign br_bus = {br_taken,br_target};
assign es_to_ms_bus = {es_load_op , //75:71
es_mem_to_reg , //70:70
es_reg_we , //69:69
es_dest , //68:64
es_alu_result , //63:32
es_pc //31:0
assign es_to_ms_bus = {br_target , //120:89
es_branch_op , //88 :80
es_Carry , //79 :79
es_Sign , //78 :78
es_Overflow , //77 :77
es_Zero , //76 :76
es_load_op , //75 :71
es_mem_to_reg , //70 :70
es_reg_we , //69 :69
es_dest , //68 :64
es_alu_result , //63 :32
es_pc //31 :0
};
assign es_ready_go = 1'b1;
@@ -130,15 +131,6 @@ module exe_stage(
es_store_op[2] ? es_rf_rdata2 :
32'b0;
assign br_taken = ( es_branch_op[0] && es_Zero
|| es_branch_op[1] && !es_Zero
|| es_branch_op[2] && (es_Sign != es_Overflow)
|| es_branch_op[3] && (es_Zero | (es_Sign == es_Overflow))
|| es_branch_op[4] && es_Carry
|| es_branch_op[5] && (es_Zero | ~es_Carry )
|| es_branch_op[6]
|| es_branch_op[7]
|| es_branch_op[8]);
assign br_target = (^es_branch_op[5:0]) ? (es_pc + es_imm) :
( es_branch_op[7:6]) ? (es_pc + es_imm) :
( es_branch_op[8] ) ? (es_rf_rdata1 + es_imm) :

56
lacpu/rtl/cpu/mem_stage.v
View File

@@ -12,6 +12,8 @@ module mem_stage(
//to ws
output ms_to_ws_valid,
output [`MS_TO_WS_BUS_WD -1:0] ms_to_ws_bus ,
//to fs
output [`BR_BUS_WD -1:0] br_bus ,
//from data-sram
input [31 :0] data_sram_rdata
);
@@ -20,6 +22,8 @@ module mem_stage(
wire ms_ready_go;
reg [`ES_TO_MS_BUS_WD -1:0] es_to_ms_bus_r;
wire [31:0] br_target;
wire [ 8:0] ms_branch_op;
wire [ 4:0] ms_load_op;
wire [ 2:0] ms_store_op;
wire ms_mem_to_reg;
@@ -27,22 +31,37 @@ module mem_stage(
wire [ 4:0] ms_dest;
wire [31:0] ms_alu_result;
wire [31:0] ms_pc;
assign {ms_load_op , //75:71
ms_mem_to_reg , //70:70
ms_reg_we , //69:69
ms_dest , //68:64
ms_alu_result , //63:32
ms_pc //31:0
wire ms_Carry ;
wire ms_Sign ;
wire ms_Overflow ;
wire ms_Zero ;
assign {br_target , //120:89
ms_branch_op , //88 :80
ms_Carry , //79 :79
ms_Sign , //78 :78
ms_Overflow , //77 :77
ms_Zero , //76 :76
ms_load_op , //75 :71
ms_mem_to_reg , //70 :70
ms_reg_we , //69 :69
ms_dest , //68 :64
ms_alu_result , //63 :32
ms_pc //31 :0
} = es_to_ms_bus_r;
wire br_taken;
wire [31:0] mem_result;
wire [31:0] ms_final_result;
assign br_bus = {br_taken, br_target};
assign ms_to_ws_bus = {ms_reg_we , //69:69
ms_dest , //68:64
ms_final_result, //63:32
ms_pc //31:0
};
ms_dest , //68:64
ms_final_result, //63:32
ms_pc //31:0
};
assign ms_ready_go = 1'b1;
assign ms_allowin = !ms_valid || ms_ready_go && ws_allowin;
@@ -66,10 +85,21 @@ module mem_stage(
{ data_sram_rdata[ 7:0], 24'b0}) :
(ms_load_op[1] || ms_load_op[4]) ? ((ms_alu_result[1:0] == 2'b00) ? {{16{ms_load_op[4] ? data_sram_rdata[15] : 1'b0 }}, data_sram_rdata[15:0] } :
{ data_sram_rdata[15:0], 16'b0}) :
ms_load_op[2] ? ( data_sram_rdata ) :
32'b0;
ms_load_op[2] ? ( data_sram_rdata ) :
32'b0;
assign ms_final_result = ms_mem_to_reg ? mem_result
: ms_alu_result;
: ms_alu_result;
assign br_taken = ( ms_branch_op[0] && ms_Zero
|| ms_branch_op[1] && !ms_Zero
|| ms_branch_op[2] && (ms_Sign != ms_Overflow)
|| ms_branch_op[3] && (ms_Zero | (ms_Sign == ms_Overflow))
|| ms_branch_op[4] && ms_Carry
|| ms_branch_op[5] && (ms_Zero | ~ms_Carry )
|| ms_branch_op[6]
|| ms_branch_op[7]
|| ms_branch_op[8]);
endmodule

2
lacpu/rtl/cpu/mycpu.h
View File

@@ -4,7 +4,7 @@
`define BR_BUS_WD 33
`define FS_TO_DS_BUS_WD 64
`define DS_TO_ES_BUS_WD 167
`define ES_TO_MS_BUS_WD 76
`define ES_TO_MS_BUS_WD 121
`define MS_TO_WS_BUS_WD 70
`define WS_TO_RF_BUS_WD 38
`endif

16
lacpu/run_vivado/la32r/la32r.xpr
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@@ -225,9 +225,7 @@
</Run>
<Run Id="inst_ram_synth_1" Type="Ft3:Synth" SrcSet="inst_ram" Part="xc7a100tcsg324-1" ConstrsSet="inst_ram" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" Dir="$PRUNDIR/inst_ram_synth_1" IncludeInArchive="true">
<Strategy Version="1" Minor="2">
<StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2019">
<Desc>Vivado Synthesis Defaults</Desc>
</StratHandle>
<StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2019"/>
<Step Id="synth_design"/>
</Strategy>
<GeneratedRun Dir="$PRUNDIR" File="gen_run.xml"/>
@@ -237,9 +235,7 @@
</Run>
<Run Id="data_ram_synth_1" Type="Ft3:Synth" SrcSet="data_ram" Part="xc7a100tcsg324-1" ConstrsSet="data_ram" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" Dir="$PRUNDIR/data_ram_synth_1" IncludeInArchive="true">
<Strategy Version="1" Minor="2">
<StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2019">
<Desc>Vivado Synthesis Defaults</Desc>
</StratHandle>
<StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2019"/>
<Step Id="synth_design"/>
</Strategy>
<GeneratedRun Dir="$PRUNDIR" File="gen_run.xml"/>
@@ -267,9 +263,7 @@
</Run>
<Run Id="inst_ram_impl_1" Type="Ft2:EntireDesign" Part="xc7a100tcsg324-1" ConstrsSet="inst_ram" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" SynthRun="inst_ram_synth_1" IncludeInArchive="false" GenFullBitstream="true">
<Strategy Version="1" Minor="2">
<StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2019">
<Desc>Default settings for Implementation.</Desc>
</StratHandle>
<StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2019"/>
<Step Id="init_design"/>
<Step Id="opt_design"/>
<Step Id="power_opt_design"/>
@@ -286,9 +280,7 @@
</Run>
<Run Id="data_ram_impl_1" Type="Ft2:EntireDesign" Part="xc7a100tcsg324-1" ConstrsSet="data_ram" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" SynthRun="data_ram_synth_1" IncludeInArchive="false" GenFullBitstream="true">
<Strategy Version="1" Minor="2">
<StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2019">
<Desc>Default settings for Implementation.</Desc>
</StratHandle>
<StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2019"/>
<Step Id="init_design"/>
<Step Id="opt_design"/>
<Step Id="power_opt_design"/>