From bc692afda0e47e9b935e7835acfa0555f3ef679f Mon Sep 17 00:00:00 2001 From: UnbalancedCat Date: Fri, 12 May 2023 22:58:45 +0800 Subject: [PATCH] [Modified] little changes for dpi --- lacpu/rtl/cpu/{mycpu.h => mycpu.v} | 20 ++++++------- lacpu/rtl/soc_lite_top.v | 46 +++++++++++++++++------------- 2 files changed, 36 insertions(+), 30 deletions(-) rename lacpu/rtl/cpu/{mycpu.h => mycpu.v} (95%) mode change 100755 => 100644 diff --git a/lacpu/rtl/cpu/mycpu.h b/lacpu/rtl/cpu/mycpu.v old mode 100755 new mode 100644 similarity index 95% rename from lacpu/rtl/cpu/mycpu.h rename to lacpu/rtl/cpu/mycpu.v index cd01ff6..9239be2 --- a/lacpu/rtl/cpu/mycpu.h +++ b/lacpu/rtl/cpu/mycpu.v @@ -1,10 +1,10 @@ -`ifndef MYCPU_H - `define MYCPU_H - - `define BR_BUS_WD 33 - `define FS_TO_DS_BUS_WD 64 - `define DS_TO_ES_BUS_WD 167 - `define ES_TO_MS_BUS_WD 121 - `define MS_TO_WS_BUS_WD 70 - `define WS_TO_RF_BUS_WD 38 -`endif +`ifndef MYCPU_H + `define MYCPU_H + + `define BR_BUS_WD 33 + `define FS_TO_DS_BUS_WD 64 + `define DS_TO_ES_BUS_WD 167 + `define ES_TO_MS_BUS_WD 121 + `define MS_TO_WS_BUS_WD 70 + `define WS_TO_RF_BUS_WD 38 +`endif diff --git a/lacpu/rtl/soc_lite_top.v b/lacpu/rtl/soc_lite_top.v index 86216a2..17b63f9 100755 --- a/lacpu/rtl/soc_lite_top.v +++ b/lacpu/rtl/soc_lite_top.v @@ -58,27 +58,33 @@ module soc_lite_top .debug_wb_rf_wdata(debug_wb_rf_wdata) ); - //inst ram - inst_ram inst_ram - ( - .clka (cpu_clk ), - .ena (cpu_inst_en ), - .wea (cpu_inst_wen ), //3:0 - .addra (cpu_inst_addr[17:2]), //15:0 - .dina (cpu_inst_wdata ), //31:0 - .douta (cpu_inst_rdata ) //31:0 - ); - //data ram - data_ram data_ram - ( - .clka (cpu_clk ), - .ena (cpu_data_en ), - .wea (cpu_data_wen ), //3:0 - .addra (cpu_data_addr[17:2]), //15:0 - .dina (cpu_data_wdata ), //31:0 - .douta (cpu_data_rdata ) //31:0 - ); + `ifdef DPIC + + + `else + //inst ram + inst_ram inst_ram + ( + .clka (cpu_clk ), + .ena (cpu_inst_en ), + .wea (cpu_inst_wen ), //3:0 + .addra (cpu_inst_addr[17:2]), //15:0 + .dina (cpu_inst_wdata ), //31:0 + .douta (cpu_inst_rdata ) //31:0 + ); + + //data ram + data_ram data_ram + ( + .clka (cpu_clk ), + .ena (cpu_data_en ), + .wea (cpu_data_wen ), //3:0 + .addra (cpu_data_addr[17:2]), //15:0 + .dina (cpu_data_wdata ), //31:0 + .douta (cpu_data_rdata ) //31:0 + ); + `endif endmodule