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[Modified] Switch soc_top&board to axi&xc7a200t

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包焕垲
2023-07-20 21:40:21 +08:00
parent 104518d875
commit a755aae99e
43 changed files with 5798 additions and 105625 deletions
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23
.gitignore vendored
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@@ -3,15 +3,18 @@
build/ build/
ext/ ext/
# VIVADO VERILOG # VIVADO PROJECT
/lacpu/run_vivado/la32r/* /lacpu/run_vivado/la32r/*
/lacpu/rtl/xilinx_ip/inst_ram/*
/lacpu/rtl/xilinx_ip/data_ram/*
vivado.jou
vivado.log
!/lacpu/run_vivado/la32r/la32r.xpr !/lacpu/run_vivado/la32r/la32r.xpr
!/lacpu/rtl/xilinx_ip/inst_ram/inst_ram.xci
!/lacpu/run_vivado/la32r/sim # VIVADO IP
!/lacpu/rtl/xilinx_ip/inst_ram/inst_ram.coe /lacpu/rtl/xilinx_ip/axi_crossbar_1x2/*
!/lacpu/rtl/xilinx_ip/data_ram/data_ram.xci /lacpu/rtl/xilinx_ip/axi_ram/*
!/lacpu/rtl/xilinx_ip/data_ram/data_ram.coe /lacpu/rtl/xilinx_ip/clk_pll/*
/lacpu/rtl/xilinx_ip/data_bram_bank/*
!/lacpu/rtl/xilinx_ip/axi_crossbar_1x2/axi_crossbar_1x2.xci
!/lacpu/rtl/xilinx_ip/axi_ram/axi_ram.xci
!/lacpu/rtl/xilinx_ip/clk_pll/clk_pll.xci
!/lacpu/rtl/xilinx_ip/data_bram_bank/data_bram_bank.xci

2
lacpu/README.md
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@@ -4,6 +4,8 @@
![指令格式](./doc/pic/指令格式.png) ![指令格式](./doc/pic/指令格式.png)
未更新
最新 op 划分不在遵循下列方式，请参考 **[chiplab/mycpu](https://gitee.com/loongson-edu/chiplab/tree/chiplab_diff/IP/myCPU)** 中的划分方式。 最新 op 划分不在遵循下列方式，请参考 **[chiplab/mycpu](https://gitee.com/loongson-edu/chiplab/tree/chiplab_diff/IP/myCPU)** 中的划分方式。
#### op6 #### op6

838
lacpu/rtl/CONFREG/confreg.v Normal file
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@@ -0,0 +1,838 @@
/*------------------------------------------------------------------------------
--------------------------------------------------------------------------------
Copyright (c) 2016, Loongson Technology Corporation Limited.
All rights reserved.
Redistribution and use in source and binary forms, with or without modification,
are permitted provided that the following conditions are met:
1. Redistributions of source code must retain the above copyright notice, this
list of conditions and the following disclaimer.
2. Redistributions in binary form must reproduce the above copyright notice,
this list of conditions and the following disclaimer in the documentation and/or
other materials provided with the distribution.
3. Neither the name of Loongson Technology Corporation Limited nor the names of
its contributors may be used to endorse or promote products derived from this
software without specific prior written permission.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
DISCLAIMED. IN NO EVENT SHALL LOONGSON TECHNOLOGY CORPORATION LIMITED BE LIABLE
TO ANY PARTY FOR DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE
GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
--------------------------------------------------------------------------------
------------------------------------------------------------------------------*/
//*************************************************************************
// > File Name : confreg.v
// > Description : Control module of
// 16 red leds, 2 green/red leds,
// 7-segment display,
// switchs,
// key board,
// bottom STEP,
// timer.
//
// > Author : LOONGSON
// > Date : 2017-08-04
//*************************************************************************
`define RANDOM_SEED {7'b1010101,16'h00FF}
`define CR0_ADDR 16'h8000 //32'hbfaf_8000
`define CR1_ADDR 16'h8010 //32'hbfaf_8010
`define CR2_ADDR 16'h8020 //32'hbfaf_8020
`define CR3_ADDR 16'h8030 //32'hbfaf_8030
`define CR4_ADDR 16'h8040 //32'hbfaf_8040
`define CR5_ADDR 16'h8050 //32'hbfaf_8050
`define CR6_ADDR 16'h8060 //32'hbfaf_8060
`define CR7_ADDR 16'h8070 //32'hbfaf_8070
`define LED_ADDR 16'hf020 //32'hbfaf_f020
`define LED_RG0_ADDR 16'hf030 //32'hbfaf_f030
`define LED_RG1_ADDR 16'hf040 //32'hbfaf_f040
`define NUM_ADDR 16'hf050 //32'hbfaf_f050
`define SWITCH_ADDR 16'hf060 //32'hbfaf_f060
`define BTN_KEY_ADDR 16'hf070 //32'hbfaf_f070
`define BTN_STEP_ADDR 16'hf080 //32'hbfaf_f080
`define SW_INTER_ADDR 16'hf090 //32'hbfaf_f090
`define TIMER_ADDR 16'he000 //32'hbfaf_e000
`define IO_SIMU_ADDR 16'hff00 //32'hbfaf_ff00
`define VIRTUAL_UART_ADDR 16'hff10 //32'hbfaf_ff10
`define SIMU_FLAG_ADDR 16'hff20 //32'hbfaf_ff20
`define OPEN_TRACE_ADDR 16'hff30 //32'hbfaf_ff30
`define NUM_MONITOR_ADDR 16'hff40 //32'hbfaf_ff40
module confreg
#(parameter SIMULATION=1'b0)
(
input wire aclk,
input wire timer_clk,
input wire aresetn,
// read and write from cpu
//ar
input wire [3 :0] arid ,
input wire [31:0] araddr ,
input wire [7 :0] arlen ,
input wire [2 :0] arsize ,
input wire [1 :0] arburst,
input wire [1 :0] arlock ,
input wire [3 :0] arcache,
input wire [2 :0] arprot ,
input wire arvalid,
output wire arready,
//r
output wire [3 :0] rid ,
output wire [31:0] rdata ,
output wire [1 :0] rresp ,
output wire rlast ,
output wire rvalid ,
input wire rready ,
//aw
input wire [3 :0] awid ,
input wire [31:0] awaddr ,
input wire [7 :0] awlen ,
input wire [2 :0] awsize ,
input wire [1 :0] awburst,
input wire [1 :0] awlock ,
input wire [3 :0] awcache,
input wire [2 :0] awprot ,
input wire awvalid,
output wire awready,
//w
input wire [3 :0] wid ,
input wire [31:0] wdata ,
input wire [3 :0] wstrb ,
input wire wlast ,
input wire wvalid ,
output wire wready ,
//b
output wire [3 :0] bid ,
output wire [1 :0] bresp ,
output wire bvalid ,
input wire bready ,
//for lab6
output wire [4 :0] ram_random_mask ,
// read and write to device on board
output wire [15:0] led,
output wire [1 :0] led_rg0,
output wire [1 :0] led_rg1,
output reg [7 :0] num_csn,
output reg [6 :0] num_a_g,
output reg [31:0] num_data,
input wire [7 :0] switch,
output wire [3 :0] btn_key_col,
input wire [3 :0] btn_key_row,
input wire [1 :0] btn_step
);
reg [31:0] cr0;
reg [31:0] cr1;
reg [31:0] cr2;
reg [31:0] cr3;
reg [31:0] cr4;
reg [31:0] cr5;
reg [31:0] cr6;
reg [31:0] cr7;
reg [31:0] led_data;
reg [31:0] led_rg0_data;
reg [31:0] led_rg1_data;
wire [31:0] switch_data;
wire [31:0] sw_inter_data; //switch interleave
wire [31:0] btn_key_data;
wire [31:0] btn_step_data;
reg [31:0] timer_r2;
reg [31:0] simu_flag;
reg [31:0] io_simu;
reg [7 :0] virtual_uart_data;
reg open_trace;
reg num_monitor;
//--------------------------{axi interface}begin-------------------------//
reg busy,write,R_or_W;
reg s_wready;
wire ar_enter = arvalid & arready;
wire r_retire = rvalid & rready & rlast;
wire aw_enter = awvalid & awready;
wire w_enter = wvalid & wready & wlast;
wire b_retire = bvalid & bready;
assign arready = ~busy & (!R_or_W| !awvalid);
assign awready = ~busy & ( R_or_W| !arvalid);
reg [3 :0] buf_id;
reg [31:0] buf_addr;
reg [7 :0] buf_len;
reg [2 :0] buf_size;
always @(posedge aclk)
begin
if(~aresetn) busy <= 1'b0;
else if(ar_enter|aw_enter) busy <= 1'b1;
else if(r_retire|b_retire) busy <= 1'b0;
end
always @(posedge aclk)
begin
if(~aresetn)
begin
R_or_W <= 1'b0;
buf_id <= 4'b0;
buf_addr <= 32'b0;
buf_len <= 8'b0;
buf_size <= 3'b0;
end
else
if(ar_enter | aw_enter)
begin
R_or_W <= ar_enter;
buf_id <= ar_enter ? arid : awid ;
buf_addr <= ar_enter ? araddr : awaddr ;
buf_len <= ar_enter ? arlen : awlen ;
buf_size <= ar_enter ? arsize : awsize ;
end
end
reg conf_wready_reg;
assign wready = conf_wready_reg;
always@(posedge aclk)
begin
if (~aresetn ) conf_wready_reg <= 1'b0;
else if(aw_enter ) conf_wready_reg <= 1'b1;
else if(w_enter & wlast) conf_wready_reg <= 1'b0;
end
// read data has one cycle delay
reg [31:0] conf_rdata_reg;
reg conf_rvalid_reg;
reg conf_rlast_reg;
assign rdata = conf_rdata_reg;
assign rvalid = conf_rvalid_reg;
assign rlast = conf_rlast_reg;
always @(posedge aclk)
begin
if(~aresetn)
begin
conf_rdata_reg <= 32'd0;
conf_rvalid_reg <= 1'd0;
conf_rlast_reg <= 1'd0;
end
else if(busy & R_or_W & !r_retire)
begin
conf_rvalid_reg <= 1'd1;
conf_rlast_reg <= 1'd1;
case (buf_addr[15:0])
`CR0_ADDR : conf_rdata_reg <= cr0 ;
`CR1_ADDR : conf_rdata_reg <= cr1 ;
`CR2_ADDR : conf_rdata_reg <= cr2 ;
`CR3_ADDR : conf_rdata_reg <= cr3 ;
`CR4_ADDR : conf_rdata_reg <= cr4 ;
`CR5_ADDR : conf_rdata_reg <= cr5 ;
`CR6_ADDR : conf_rdata_reg <= cr6 ;
`CR7_ADDR : conf_rdata_reg <= cr7 ;
`LED_ADDR : conf_rdata_reg <= led_data ;
`LED_RG0_ADDR : conf_rdata_reg <= led_rg0_data ;
`LED_RG1_ADDR : conf_rdata_reg <= led_rg1_data ;
`NUM_ADDR : conf_rdata_reg <= num_data ;
`SWITCH_ADDR : conf_rdata_reg <= switch_data ;
`BTN_KEY_ADDR : conf_rdata_reg <= btn_key_data ;
`BTN_STEP_ADDR : conf_rdata_reg <= btn_step_data;
`SW_INTER_ADDR : conf_rdata_reg <= sw_inter_data;
`TIMER_ADDR : conf_rdata_reg <= timer_r2 ;
`SIMU_FLAG_ADDR: conf_rdata_reg <= simu_flag ;
`IO_SIMU_ADDR : conf_rdata_reg <= io_simu ;
`VIRTUAL_UART_ADDR : conf_rdata_reg <= {24'd0,virtual_uart_data} ;
`OPEN_TRACE_ADDR : conf_rdata_reg <= {31'd0,open_trace} ;
`NUM_MONITOR_ADDR: conf_rdata_reg <= {31'd0,num_monitor} ;
default : conf_rdata_reg <= 32'd0;
endcase
end
else if(r_retire)
begin
conf_rvalid_reg <= 1'b0;
end
end
//conf write, only support a word write
wire conf_we;
wire [31:0] conf_addr;
wire [31:0] conf_wdata;
assign conf_we = w_enter;
assign conf_addr = buf_addr;
assign conf_wdata= wdata;
reg conf_bvalid_reg;
assign bvalid = conf_bvalid_reg;
always @(posedge aclk)
begin
if (~aresetn) conf_bvalid_reg <= 1'b0;
else if(w_enter ) conf_bvalid_reg <= 1'b1;
else if(b_retire) conf_bvalid_reg <= 1'b0;
end
assign rid = buf_id;
assign bid = buf_id;
assign bresp = 2'b0;
assign rresp = 2'b0;
//---------------------------{axi interface}end--------------------------//
//-------------------------{confreg register}begin-----------------------//
wire write_cr0 = conf_we & (conf_addr[15:0]==`CR0_ADDR);
wire write_cr1 = conf_we & (conf_addr[15:0]==`CR1_ADDR);
wire write_cr2 = conf_we & (conf_addr[15:0]==`CR2_ADDR);
wire write_cr3 = conf_we & (conf_addr[15:0]==`CR3_ADDR);
wire write_cr4 = conf_we & (conf_addr[15:0]==`CR4_ADDR);
wire write_cr5 = conf_we & (conf_addr[15:0]==`CR5_ADDR);
wire write_cr6 = conf_we & (conf_addr[15:0]==`CR6_ADDR);
wire write_cr7 = conf_we & (conf_addr[15:0]==`CR7_ADDR);
always @(posedge aclk)
begin
cr0 <= !aresetn ? 32'd0 :
write_cr0 ? conf_wdata : cr0;
cr1 <= !aresetn ? 32'd0 :
write_cr1 ? conf_wdata : cr1;
cr2 <= !aresetn ? 32'd0 :
write_cr2 ? conf_wdata : cr2;
cr3 <= !aresetn ? 32'd0 :
write_cr3 ? conf_wdata : cr3;
cr4 <= !aresetn ? 32'd0 :
write_cr4 ? conf_wdata : cr4;
cr5 <= !aresetn ? 32'd0 :
write_cr5 ? conf_wdata : cr5;
cr6 <= !aresetn ? 32'd0 :
write_cr6 ? conf_wdata : cr6;
cr7 <= !aresetn ? 32'd0 :
write_cr7 ? conf_wdata : cr7;
end
//--------------------------{confreg register}end------------------------//
//-------------------------------{timer}begin----------------------------//
reg write_timer_begin,write_timer_begin_r1, write_timer_begin_r2,write_timer_begin_r3;
reg write_timer_end_r1, write_timer_end_r2;
reg [31:0] conf_wdata_r, conf_wdata_r1,conf_wdata_r2;
reg [31:0] timer_r1;
reg [31:0] timer;
wire write_timer = conf_we & (conf_addr[15:0]==`TIMER_ADDR);
always @(posedge aclk)
begin
if (!aresetn)
begin
write_timer_begin <= 1'b0;
end
else if (write_timer)
begin
write_timer_begin <= 1'b1;
conf_wdata_r <= conf_wdata;
end
else if (write_timer_end_r2)
begin
write_timer_begin <= 1'b0;
end
write_timer_end_r1 <= write_timer_begin_r2;
write_timer_end_r2 <= write_timer_end_r1;
end
always @(posedge timer_clk)
begin
write_timer_begin_r1 <= write_timer_begin;
write_timer_begin_r2 <= write_timer_begin_r1;
write_timer_begin_r3 <= write_timer_begin_r2;
conf_wdata_r1 <= conf_wdata_r;
conf_wdata_r2 <= conf_wdata_r1;
if(!aresetn)
begin
timer <= 32'd0;
end
else if (write_timer_begin_r2 && !write_timer_begin_r3)
begin
timer <= conf_wdata_r2[31:0];
end
else
begin
timer <= timer + 1'b1;
end
end
always @(posedge aclk)
begin
timer_r1 <= timer;
timer_r2 <= timer_r1;
end
//--------------------------------{timer}end-----------------------------//
//--------------------------{simulation flag}begin-----------------------//
always @(posedge aclk)
begin
if(!aresetn)
begin
simu_flag <= {32{SIMULATION}};
end
end
//---------------------------{simulation flag}end------------------------//
//---------------------------{io simulation}begin------------------------//
wire write_io_simu = conf_we & (conf_addr[15:0]==`IO_SIMU_ADDR);
always @(posedge aclk)
begin
if(!aresetn)
begin
io_simu <= 32'd0;
end
else if(write_io_simu)
begin
io_simu <= {conf_wdata[15:0],conf_wdata[31:16]};
end
end
//----------------------------{io simulation}end-------------------------//
//-----------------------------{open trace}begin-------------------------//
wire write_open_trace = conf_we & (conf_addr[15:0]==`OPEN_TRACE_ADDR);
always @(posedge aclk)
begin
if(!aresetn)
begin
open_trace <= 1'b1;
end
else if(write_open_trace)
begin
open_trace <= |conf_wdata;
end
end
//-----------------------------{open trace}end---------------------------//
//----------------------------{num monitor}begin-------------------------//
wire write_num_monitor = conf_we & (conf_addr[15:0]==`NUM_MONITOR_ADDR);
always @(posedge aclk)
begin
if(!aresetn)
begin
num_monitor <= 1'b1;
end
else if(write_num_monitor)
begin
num_monitor <= conf_wdata[0];
end
end
//----------------------------{num monitor}end---------------------------//
//---------------------------{virtual uart}begin-------------------------//
wire [7:0] write_uart_data;
wire write_uart_valid = conf_we & (conf_addr[15:0]==`VIRTUAL_UART_ADDR);
assign write_uart_data = conf_wdata[7:0];
always @(posedge aclk)
begin
if(!aresetn)
begin
virtual_uart_data <= 8'd0;
end
else if(write_uart_valid)
begin
virtual_uart_data <= write_uart_data;
end
end
//----------------------------{virtual uart}end--------------------------//
//--------------------------{axirandom mask}begin------------------------//
wire [15:0] switch_led;
wire [15:0] led_r_n;
assign led_r_n = ~switch_led;
reg [22:0] pseudo_random_23;
reg no_mask; //if led_r_n[7:0] is all 1, no mask
reg short_delay; //memory short delay
always @ (posedge aclk)
begin
if (!aresetn)
pseudo_random_23 <= simu_flag[0] ? `RANDOM_SEED : {7'b1010101,led_r_n};
else
pseudo_random_23 <= {pseudo_random_23[21:0],pseudo_random_23[22] ^ pseudo_random_23[17]};
if(!aresetn)
no_mask <= pseudo_random_23[15:0]==16'h00FF;
if(!aresetn)
short_delay <= pseudo_random_23[7:0]==8'hFF;
end
assign ram_random_mask[0] = (pseudo_random_23[10]&pseudo_random_23[20]) & (short_delay|(pseudo_random_23[11]^pseudo_random_23[5]))
| no_mask;
assign ram_random_mask[1] = (pseudo_random_23[ 9]&pseudo_random_23[17]) & (short_delay|(pseudo_random_23[12]^pseudo_random_23[4]))
| no_mask;
assign ram_random_mask[2] = (pseudo_random_23[ 8]^pseudo_random_23[22]) & (short_delay|(pseudo_random_23[13]^pseudo_random_23[3]))
| no_mask;
assign ram_random_mask[3] = (pseudo_random_23[ 7]&pseudo_random_23[19]) & (short_delay|(pseudo_random_23[14]^pseudo_random_23[2]))
| no_mask;
assign ram_random_mask[4] = (pseudo_random_23[ 6]^pseudo_random_23[16]) & (short_delay|(pseudo_random_23[15]^pseudo_random_23[1]))
| no_mask;
//---------------------------{axirandom mask}end-------------------------//
//--------------------------------{led}begin-----------------------------//
//led display
//led_data[31:0]
wire write_led = conf_we & (conf_addr[15:0]==`LED_ADDR);
assign led = led_data[15:0];
assign switch_led = {{2{switch[7]}},{2{switch[6]}},{2{switch[5]}},{2{switch[4]}},
{2{switch[3]}},{2{switch[2]}},{2{switch[1]}},{2{switch[0]}}};
always @(posedge aclk)
begin
if(!aresetn)
begin
led_data <= {16'h0,switch_led};
end
else if(write_led)
begin
led_data <= conf_wdata[31:0];
end
end
//---------------------------------{led}end------------------------------//
//-------------------------------{switch}begin---------------------------//
//switch data
//switch_data[7:0]
assign switch_data = {24'd0,switch};
assign sw_inter_data = {16'd0,
switch[7],1'b0,switch[6],1'b0,
switch[5],1'b0,switch[4],1'b0,
switch[3],1'b0,switch[2],1'b0,
switch[1],1'b0,switch[0],1'b0};
//--------------------------------{switch}end----------------------------//
//------------------------------{btn key}begin---------------------------//
//btn key data
reg [15:0] btn_key_r;
assign btn_key_data = {16'd0,btn_key_r};
//state machine
reg [2:0] state;
wire [2:0] next_state;
//eliminate jitter
reg key_flag;
reg [19:0] key_count;
reg [ 3:0] state_count;
wire key_start = (state==3'b000) && !(&btn_key_row);
wire key_end = (state==3'b111) && (&btn_key_row);
wire key_sample= key_count[19];
always @(posedge aclk)
begin
if(!aresetn)
begin
key_flag <= 1'd0;
end
else if (key_sample && state_count[3])
begin
key_flag <= 1'b0;
end
else if( key_start || key_end )
begin
key_flag <= 1'b1;
end
if(!aresetn || !key_flag)
begin
key_count <= 20'd0;
end
else
begin
key_count <= key_count + 1'b1;
end
end
always @(posedge aclk)
begin
if(!aresetn || state_count[3])
begin
state_count <= 4'd0;
end
else
begin
state_count <= state_count + 1'b1;
end
end
always @(posedge aclk)
begin
if(!aresetn)
begin
state <= 3'b000;
end
else if (state_count[3])
begin
state <= next_state;
end
end
assign next_state = (state == 3'b000) ? ( (key_sample && !(&btn_key_row)) ? 3'b001 : 3'b000 ) :
(state == 3'b001) ? ( !(&btn_key_row) ? 3'b111 : 3'b010 ) :
(state == 3'b010) ? ( !(&btn_key_row) ? 3'b111 : 3'b011 ) :
(state == 3'b011) ? ( !(&btn_key_row) ? 3'b111 : 3'b100 ) :
(state == 3'b100) ? ( !(&btn_key_row) ? 3'b111 : 3'b000 ) :
(state == 3'b111) ? ( (key_sample && (&btn_key_row)) ? 3'b000 : 3'b111 ) :
3'b000;
assign btn_key_col = (state == 3'b000) ? 4'b0000:
(state == 3'b001) ? 4'b1110:
(state == 3'b010) ? 4'b1101:
(state == 3'b011) ? 4'b1011:
(state == 3'b100) ? 4'b0111:
4'b0000;
wire [15:0] btn_key_tmp;
always @(posedge aclk) begin
if(!aresetn) begin
btn_key_r <= 16'd0;
end
else if(next_state==3'b000)
begin
btn_key_r <=16'd0;
end
else if(next_state == 3'b111 && state != 3'b111 && state_count[3]) begin
btn_key_r <= btn_key_tmp;
end
end
assign btn_key_tmp = (state == 3'b001)&(btn_key_row == 4'b1110) ? 16'h0001:
(state == 3'b001)&(btn_key_row == 4'b1101) ? 16'h0010:
(state == 3'b001)&(btn_key_row == 4'b1011) ? 16'h0100:
(state == 3'b001)&(btn_key_row == 4'b0111) ? 16'h1000:
(state == 3'b010)&(btn_key_row == 4'b1110) ? 16'h0002:
(state == 3'b010)&(btn_key_row == 4'b1101) ? 16'h0020:
(state == 3'b010)&(btn_key_row == 4'b1011) ? 16'h0200:
(state == 3'b010)&(btn_key_row == 4'b0111) ? 16'h2000:
(state == 3'b011)&(btn_key_row == 4'b1110) ? 16'h0004:
(state == 3'b011)&(btn_key_row == 4'b1101) ? 16'h0040:
(state == 3'b011)&(btn_key_row == 4'b1011) ? 16'h0400:
(state == 3'b011)&(btn_key_row == 4'b0111) ? 16'h4000:
(state == 3'b100)&(btn_key_row == 4'b1110) ? 16'h0008:
(state == 3'b100)&(btn_key_row == 4'b1101) ? 16'h0080:
(state == 3'b100)&(btn_key_row == 4'b1011) ? 16'h0800:
(state == 3'b100)&(btn_key_row == 4'b0111) ? 16'h8000:16'h0000;
//-------------------------------{btn key}end----------------------------//
//-----------------------------{btn step}begin---------------------------//
//btn step data
reg btn_step0_r; //0:press
reg btn_step1_r; //0:press
assign btn_step_data = {30'd0,~btn_step0_r,~btn_step1_r}; //1:press
//-----step0
//eliminate jitter
reg step0_flag;
reg [19:0] step0_count;
wire step0_start = btn_step0_r && !btn_step[0];
wire step0_end = !btn_step0_r && btn_step[0];
wire step0_sample= step0_count[19];
always @(posedge aclk)
begin
if(!aresetn)
begin
step0_flag <= 1'd0;
end
else if (step0_sample)
begin
step0_flag <= 1'b0;
end
else if( step0_start || step0_end )
begin
step0_flag <= 1'b1;
end
if(!aresetn || !step0_flag)
begin
step0_count <= 20'd0;
end
else
begin
step0_count <= step0_count + 1'b1;
end
if(!aresetn)
begin
btn_step0_r <= 1'b1;
end
else if(step0_sample)
begin
btn_step0_r <= btn_step[0];
end
end
//-----step1
//eliminate jitter
reg step1_flag;
reg [19:0] step1_count;
wire step1_start = btn_step1_r && !btn_step[1];
wire step1_end = !btn_step1_r && btn_step[1];
wire step1_sample= step1_count[19];
always @(posedge aclk)
begin
if(!aresetn)
begin
step1_flag <= 1'd0;
end
else if (step1_sample)
begin
step1_flag <= 1'b0;
end
else if( step1_start || step1_end )
begin
step1_flag <= 1'b1;
end
if(!aresetn || !step1_flag)
begin
step1_count <= 20'd0;
end
else
begin
step1_count <= step1_count + 1'b1;
end
if(!aresetn)
begin
btn_step1_r <= 1'b1;
end
else if(step1_sample)
begin
btn_step1_r <= btn_step[1];
end
end
//------------------------------{btn step}end----------------------------//
//-------------------------------{led rg}begin---------------------------//
//led_rg0_data[31:0] led_rg0_data[31:0]
//bfd0_f010 bfd0_f014
wire write_led_rg0 = conf_we & (conf_addr[15:0]==`LED_RG0_ADDR);
wire write_led_rg1 = conf_we & (conf_addr[15:0]==`LED_RG1_ADDR);
assign led_rg0 = led_rg0_data[1:0];
assign led_rg1 = led_rg1_data[1:0];
always @(posedge aclk)
begin
if(!aresetn)
begin
led_rg0_data <= 32'h0;
end
else if(write_led_rg0)
begin
led_rg0_data <= conf_wdata[31:0];
end
if(!aresetn)
begin
led_rg1_data <= 32'h0;
end
else if(write_led_rg1)
begin
led_rg1_data <= conf_wdata[31:0];
end
end
//--------------------------------{led rg}end----------------------------//
//---------------------------{digital number}begin-----------------------//
//digital number display
//num_data[31:0]
wire write_num = conf_we & (conf_addr[15:0]==`NUM_ADDR);
always @(posedge aclk)
begin
if(!aresetn)
begin
num_data <= 32'h0;
end
else if(write_num)
begin
num_data <= conf_wdata[31:0];
end
end
reg [19:0] count;
always @(posedge aclk)
begin
if(!aresetn)
begin
count <= 20'd0;
end
else
begin
count <= count + 1'b1;
end
end
//scan data
reg [3:0] scan_data;
always @ ( posedge aclk )
begin
if ( !aresetn )
begin
scan_data <= 32'd0;
num_csn <= 8'b1111_1111;
end
else
begin
case(count[19:17])
3'b000 : scan_data <= num_data[31:28];
3'b001 : scan_data <= num_data[27:24];
3'b010 : scan_data <= num_data[23:20];
3'b011 : scan_data <= num_data[19:16];
3'b100 : scan_data <= num_data[15:12];
3'b101 : scan_data <= num_data[11: 8];
3'b110 : scan_data <= num_data[7 : 4];
3'b111 : scan_data <= num_data[3 : 0];
endcase
case(count[19:17])
3'b000 : num_csn <= 8'b0111_1111;
3'b001 : num_csn <= 8'b1011_1111;
3'b010 : num_csn <= 8'b1101_1111;
3'b011 : num_csn <= 8'b1110_1111;
3'b100 : num_csn <= 8'b1111_0111;
3'b101 : num_csn <= 8'b1111_1011;
3'b110 : num_csn <= 8'b1111_1101;
3'b111 : num_csn <= 8'b1111_1110;
endcase
end
end
always @(posedge aclk)
begin
if ( !aresetn )
begin
num_a_g <= 7'b0000000;
end
else
begin
case ( scan_data )
4'd0 : num_a_g <= 7'b1111110; //0
4'd1 : num_a_g <= 7'b0110000; //1
4'd2 : num_a_g <= 7'b1101101; //2
4'd3 : num_a_g <= 7'b1111001; //3
4'd4 : num_a_g <= 7'b0110011; //4
4'd5 : num_a_g <= 7'b1011011; //5
4'd6 : num_a_g <= 7'b1011111; //6
4'd7 : num_a_g <= 7'b1110000; //7
4'd8 : num_a_g <= 7'b1111111; //8
4'd9 : num_a_g <= 7'b1111011; //9
4'd10: num_a_g <= 7'b1110111; //a
4'd11: num_a_g <= 7'b0011111; //b
4'd12: num_a_g <= 7'b1001110; //c
4'd13: num_a_g <= 7'b0111101; //d
4'd14: num_a_g <= 7'b1001111; //e
4'd15: num_a_g <= 7'b1000111; //f
endcase
end
end
//----------------------------{digital number}end------------------------//
endmodule

166
lacpu/rtl/axi_wrap/axi_wrap.v Normal file
View File

@@ -0,0 +1,166 @@
/*------------------------------------------------------------------------------
--------------------------------------------------------------------------------
Copyright (c) 2016, Loongson Technology Corporation Limited.
All rights reserved.
Redistribution and use in source and binary forms, with or without modification,
are permitted provided that the following conditions are met:
1. Redistributions of source code must retain the above copyright notice, this
list of conditions and the following disclaimer.
2. Redistributions in binary form must reproduce the above copyright notice,
this list of conditions and the following disclaimer in the documentation and/or
other materials provided with the distribution.
3. Neither the name of Loongson Technology Corporation Limited nor the names of
its contributors may be used to endorse or promote products derived from this
software without specific prior written permission.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
DISCLAIMED. IN NO EVENT SHALL LOONGSON TECHNOLOGY CORPORATION LIMITED BE LIABLE
TO ANY PARTY FOR DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE
GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
--------------------------------------------------------------------------------
------------------------------------------------------------------------------*/
module axi_wrap(
input wire m_aclk,
input wire m_aresetn,
//ar
input wire [3 :0] m_arid ,
input wire [31:0] m_araddr ,
input wire [7 :0] m_arlen ,
input wire [2 :0] m_arsize ,
input wire [1 :0] m_arburst,
input wire [1 :0] m_arlock ,
input wire [3 :0] m_arcache,
input wire [2 :0] m_arprot ,
input wire m_arvalid,
output wire m_arready,
//r
output wire [3 :0] m_rid ,
output wire [31:0] m_rdata ,
output wire [1 :0] m_rresp ,
output wire m_rlast ,
output wire m_rvalid ,
input wire m_rready ,
//aw
input wire [3 :0] m_awid ,
input wire [31:0] m_awaddr ,
input wire [7 :0] m_awlen ,
input wire [2 :0] m_awsize ,
input wire [1 :0] m_awburst,
input wire [1 :0] m_awlock ,
input wire [3 :0] m_awcache,
input wire [2 :0] m_awprot ,
input wire m_awvalid,
output wire m_awready,
//w
input wire [3 :0] m_wid ,
input wire [31:0] m_wdata ,
input wire [3 :0] m_wstrb ,
input wire m_wlast ,
input wire m_wvalid ,
output wire m_wready ,
//b
output wire [3 :0] m_bid ,
output wire [1 :0] m_bresp ,
output wire m_bvalid ,
input wire m_bready ,
output wire s_aclk,
output wire s_aresetn,
//ar
output wire [3 :0] s_arid ,
output wire [31:0] s_araddr ,
output wire [7 :0] s_arlen ,
output wire [2 :0] s_arsize ,
output wire [1 :0] s_arburst,
output wire [1 :0] s_arlock ,
output wire [3 :0] s_arcache,
output wire [2 :0] s_arprot ,
output wire s_arvalid,
input wire s_arready,
//r
input wire [3 :0] s_rid ,
input wire [31:0] s_rdata ,
input wire [1 :0] s_rresp ,
input wire s_rlast ,
input wire s_rvalid ,
output wire s_rready ,
//aw
output wire [3 :0] s_awid ,
output wire [31:0] s_awaddr ,
output wire [7 :0] s_awlen ,
output wire [2 :0] s_awsize ,
output wire [1 :0] s_awburst,
output wire [1 :0] s_awlock ,
output wire [3 :0] s_awcache,
output wire [2 :0] s_awprot ,
output wire s_awvalid,
input wire s_awready,
//w
output wire [3 :0] s_wid ,
output wire [31:0] s_wdata ,
output wire [3 :0] s_wstrb ,
output wire s_wlast ,
output wire s_wvalid ,
input wire s_wready ,
//b
input wire [3 :0] s_bid ,
input wire [1 :0] s_bresp ,
input wire s_bvalid ,
output wire s_bready
);
assign s_aclk = m_aclk ;
assign s_aresetn = m_aresetn;
//ar
assign s_arid = m_arid ;
assign s_araddr = m_araddr ;
assign s_arlen = m_arlen ;
assign s_arsize = m_arsize ;
assign s_arburst = m_arburst;
assign s_arlock = m_arlock ;
assign s_arcache = m_arcache;
assign s_arprot = m_arprot ;
assign s_arvalid = m_arvalid;
assign m_arready = s_arready;
//r
assign m_rid = m_rvalid ? s_rid : 4'd0 ;
assign m_rdata = m_rvalid ? s_rdata : 32'd0 ;
assign m_rresp = m_rvalid ? s_rresp : 2'd0 ;
assign m_rlast = m_rvalid ? s_rlast : 1'd0 ;
assign m_rvalid = s_rvalid;
assign s_rready = m_rready;
//aw
assign s_awid = m_awid ;
assign s_awaddr = m_awaddr ;
assign s_awlen = m_awlen ;
assign s_awsize = m_awsize ;
assign s_awburst = m_awburst;
assign s_awlock = m_awlock ;
assign s_awcache = m_awcache;
assign s_awprot = m_awprot ;
assign s_awvalid = m_awvalid;
assign m_awready = s_awready;
//w
assign s_wid = m_wid ;
assign s_wdata = m_wdata ;
assign s_wstrb = m_wstrb ;
assign s_wlast = m_wlast ;
assign s_wvalid = m_wvalid ;
assign m_wready = s_wready ;
//b
assign m_bid = m_bvalid ? s_bid : 4'd0 ;
assign m_bresp = m_bvalid ? s_bresp : 2'd0 ;
assign m_bvalid = s_bvalid ;
assign s_bready = m_bready ;
endmodule

196
lacpu/rtl/cpu/alu.v → lacpu/rtl/mycpu/alu.v Executable file → Normal file
View File

@@ -1,99 +1,99 @@
module alu( module alu(
input [11:0] alu_op , input [11:0] alu_op ,
input [31:0] alu_src1 , input [31:0] alu_src1 ,
input [31:0] alu_src2 , input [31:0] alu_src2 ,
output [31:0] alu_result output [31:0] alu_result
); );
wire op_add; wire op_add;
wire op_sub; wire op_sub;
wire op_lui; wire op_lui;
wire op_slt; wire op_slt;
wire op_sltu; wire op_sltu;
wire op_and; wire op_and;
wire op_or; wire op_or;
wire op_nor; wire op_nor;
wire op_xor; wire op_xor;
wire op_sll; wire op_sll;
wire op_srl; wire op_srl;
wire op_sra; wire op_sra;
assign op_add = alu_op[ 0]; assign op_add = alu_op[ 0];
assign op_sub = alu_op[ 1]; assign op_sub = alu_op[ 1];
assign op_slt = alu_op[ 2]; assign op_slt = alu_op[ 2];
assign op_sltu = alu_op[ 3]; assign op_sltu = alu_op[ 3];
assign op_and = alu_op[ 4]; assign op_and = alu_op[ 4];
assign op_nor = alu_op[ 5]; assign op_nor = alu_op[ 5];
assign op_or = alu_op[ 6]; assign op_or = alu_op[ 6];
assign op_xor = alu_op[ 7]; assign op_xor = alu_op[ 7];
assign op_sll = alu_op[ 8]; assign op_sll = alu_op[ 8];
assign op_srl = alu_op[ 9]; assign op_srl = alu_op[ 9];
assign op_sra = alu_op[10]; assign op_sra = alu_op[10];
assign op_lui = alu_op[11]; assign op_lui = alu_op[11];
wire [31:0] add_sub_result; wire [31:0] add_sub_result;
wire [31:0] slt_result; wire [31:0] slt_result;
wire [31:0] sltu_result; wire [31:0] sltu_result;
wire [31:0] and_result; wire [31:0] and_result;
wire [31:0] nor_result; wire [31:0] nor_result;
wire [31:0] or_result; wire [31:0] or_result;
wire [31:0] xor_result; wire [31:0] xor_result;
wire [31:0] lui_result; wire [31:0] lui_result;
wire [31:0] sll_result; wire [31:0] sll_result;
wire [63:0] sr64_result; wire [63:0] sr64_result;
wire [31:0] sr_result; wire [31:0] sr_result;
// 32-bit adder // 32-bit adder
wire [31:0] adder_a; wire [31:0] adder_a;
wire [31:0] adder_b; wire [31:0] adder_b;
wire adder_cin; wire adder_cin;
wire [31:0] adder_result; wire [31:0] adder_result;
wire adder_cout; wire adder_cout;
assign adder_a = alu_src1; assign adder_a = alu_src1;
assign adder_b = (op_sub | op_slt | op_sltu) ? ~alu_src2 : alu_src2; assign adder_b = (op_sub | op_slt | op_sltu) ? ~alu_src2 : alu_src2;
assign adder_cin = (op_sub | op_slt | op_sltu) ? 1'b1 : 1'b0; assign adder_cin = (op_sub | op_slt | op_sltu) ? 1'b1 : 1'b0;
assign {adder_cout, adder_result} = adder_a + adder_b + adder_cin; assign {adder_cout, adder_result} = adder_a + adder_b + adder_cin;
// ADD, SUB result // ADD, SUB result
assign add_sub_result = adder_result; assign add_sub_result = adder_result;
// SLT result // SLT result
assign slt_result[31:1] = 31'b0; assign slt_result[31:1] = 31'b0;
assign slt_result[0] = (alu_src1[31] & ~alu_src2[31]) assign slt_result[0] = (alu_src1[31] & ~alu_src2[31])
| ((alu_src1[31] ~^ alu_src2[31]) & adder_result[31]); | ((alu_src1[31] ~^ alu_src2[31]) & adder_result[31]);
// SLTU result // SLTU result
assign sltu_result[31:1] = 31'b0; assign sltu_result[31:1] = 31'b0;
assign sltu_result[0] = ~adder_cout; assign sltu_result[0] = ~adder_cout;
// bitwise operation // bitwise operation
assign and_result = alu_src1 & alu_src2; assign and_result = alu_src1 & alu_src2;
assign or_result = alu_src1 | alu_src2; assign or_result = alu_src1 | alu_src2;
assign nor_result = ~or_result; assign nor_result = ~or_result;
assign xor_result = alu_src1 ^ alu_src2; assign xor_result = alu_src1 ^ alu_src2;
assign lui_result = alu_src2; assign lui_result = alu_src2;
// SLL result // SLL result
assign sll_result = alu_src1 << alu_src2[4:0]; assign sll_result = alu_src1 << alu_src2[4:0];
// SRL, SRA result // SRL, SRA result
assign sr64_result = {{32{op_sra & alu_src1[31]}}, alu_src1[31:0]} >> alu_src2[4:0]; assign sr64_result = {{32{op_sra & alu_src1[31]}}, alu_src1[31:0]} >> alu_src2[4:0];
assign sr_result = sr64_result[31:0]; assign sr_result = sr64_result[31:0];
// final result mux // final result mux
assign alu_result = ({32{op_add|op_sub}} & add_sub_result) assign alu_result = ({32{op_add|op_sub}} & add_sub_result)
| ({32{op_slt }} & slt_result) | ({32{op_slt }} & slt_result)
| ({32{op_sltu }} & sltu_result) | ({32{op_sltu }} & sltu_result)
| ({32{op_and }} & and_result) | ({32{op_and }} & and_result)
| ({32{op_nor }} & nor_result) | ({32{op_nor }} & nor_result)
| ({32{op_or }} & or_result) | ({32{op_or }} & or_result)
| ({32{op_xor }} & xor_result) | ({32{op_xor }} & xor_result)
| ({32{op_lui }} & lui_result) | ({32{op_lui }} & lui_result)
| ({32{op_sll }} & sll_result) | ({32{op_sll }} & sll_result)
| ({32{op_srl|op_sra}} & sr_result); | ({32{op_srl|op_sra}} & sr_result);
endmodule endmodule

0
lacpu/rtl/cpu/axi_ctrl.v → lacpu/rtl/mycpu/axi_ctrl.v
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0
lacpu/rtl/cpu/bru.v → lacpu/rtl/mycpu/bru.v
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0
lacpu/rtl/cpu/cache_data.v → lacpu/rtl/mycpu/cache_data.v
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0
lacpu/rtl/cpu/cache_tag.v → lacpu/rtl/mycpu/cache_tag.v
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0
lacpu/rtl/cpu/csr.hv → lacpu/rtl/mycpu/csr.hv
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37
lacpu/rtl/cpu/csr.v → lacpu/rtl/mycpu/csr.v
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@@ -6,6 +6,7 @@ module csr(
input [31:0] pc, input [31:0] pc,
input [31:0] src1, input [31:0] src1,
input stallreq_axi,
input [31:0] error_va, input [31:0] error_va,
@@ -59,8 +60,8 @@ module csr(
reg timer_en; reg timer_en;
reg [63:0] timer_64; reg [63:0] timer_64;
reg has_int_r; // reg has_int_r;
reg [ 1:0] plv_r; // reg [ 1:0] plv_r;
wire inst_sc_w; wire inst_sc_w;
wire inst_csrrd; wire inst_csrrd;
@@ -88,26 +89,26 @@ module csr(
wire va_error; wire va_error;
wire [31:0] bad_va; wire [31:0] bad_va;
always @(posedge clk) begin // always @(posedge clk) begin
if(reset) begin // if(reset) begin
has_int_r <= 0; // has_int_r <= 0;
plv_r <= 0; // plv_r <= 0;
end // end
else begin // else begin
has_int_r <= ((ecfg[`LIE] & estat[`IS]) != 13'b0) & crmd[`IE]; // has_int_r <= ((ecfg[`LIE] & estat[`IS]) != 13'b0) & crmd[`IE];
plv_r <= except_en & !inst_ertn ? 2'b0 : // plv_r <= except_en & !inst_ertn ? 2'b0 :
inst_ertn ? prmd[`PPLV] : // inst_ertn ? prmd[`PPLV] :
csr_we && (csr_addr == `CRMD_ADDR) ? csr_wdata[`PLV] : // csr_we && (csr_addr == `CRMD_ADDR) ? csr_wdata[`PLV] :
crmd[`PLV]; // crmd[`PLV];
end // end
end // end
// out TODO! // out TODO!
assign has_int_out = ((ecfg[`LIE] & estat[`IS]) != 13'b0) & crmd[`IE]; //has_int_r; assign has_int_out = ((ecfg[`LIE] & estat[`IS]) != 13'b0) & crmd[`IE];
assign plv_out = except_en & !inst_ertn ? 2'b0 : assign plv_out = except_en & !inst_ertn ? 2'b0 :
inst_ertn ? prmd[`PPLV] : inst_ertn ? prmd[`PPLV] :
csr_we && (csr_addr == `CRMD_ADDR) ? csr_wdata[`PLV] : csr_we && (csr_addr == `CRMD_ADDR) ? csr_wdata[`PLV] :
crmd[`PLV]; //plv_r; crmd[`PLV];
assign {excp_ale, assign {excp_ale,
excp_adef, excp_adef,
@@ -222,7 +223,7 @@ module csr(
timer_en <= 1'b0; timer_en <= 1'b0;
end end
else if(except_en) begin else if(except_en & ~stallreq_axi) begin
if((|csr_vec[7:0] & !inst_ertn) | excp_adef) begin if((|csr_vec[7:0] & !inst_ertn) | excp_adef) begin
crmd[ `PLV] <= 2'b0; crmd[ `PLV] <= 2'b0;
crmd[ `IE] <= 1'b0; crmd[ `IE] <= 1'b0;

0
lacpu/rtl/cpu/dcache.v → lacpu/rtl/mycpu/dcache.v
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0
lacpu/rtl/cpu/div.v → lacpu/rtl/mycpu/div.v
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0
lacpu/rtl/cpu/exe_stage.v → lacpu/rtl/mycpu/exe_stage.v Executable file → Normal file
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0
lacpu/rtl/cpu/icache.v → lacpu/rtl/mycpu/icache.v
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512
lacpu/rtl/cpu/id_stage.v → lacpu/rtl/mycpu/id_stage.v Executable file → Normal file
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@@ -1,257 +1,257 @@
module id_stage module id_stage
#( #(
parameter FS_TO_DS_BUS_WD = 65, parameter FS_TO_DS_BUS_WD = 65,
parameter DS_TO_ES_BUS_WD = 301, parameter DS_TO_ES_BUS_WD = 301,
parameter WS_TO_RF_BUS_WD = 38 parameter WS_TO_RF_BUS_WD = 38
) )
( (
input clk, input clk,
input reset, input reset,
input flush, input flush,
input [ 5:0] stall, input [ 5:0] stall,
input br_taken, input br_taken,
output stallreq_ds, output stallreq_ds,
input pc_valid, input pc_valid,
input [31:0] inst_sram_rdata, input [31:0] inst_sram_rdata,
input [ 1:0] csr_plv, input [ 1:0] csr_plv,
input csr_has_int, input csr_has_int,
input [FS_TO_DS_BUS_WD -1:0] fs_to_ds_bus, input [FS_TO_DS_BUS_WD -1:0] fs_to_ds_bus,
input [WS_TO_RF_BUS_WD -1:0] ws_to_rf_bus, input [WS_TO_RF_BUS_WD -1:0] ws_to_rf_bus,
output [DS_TO_ES_BUS_WD -1:0] ds_to_es_bus output [DS_TO_ES_BUS_WD -1:0] ds_to_es_bus
); );
reg [FS_TO_DS_BUS_WD -1:0] fs_to_ds_bus_r; reg [FS_TO_DS_BUS_WD -1:0] fs_to_ds_bus_r;
reg pc_valid_r; reg pc_valid_r;
reg [31:0] inst_r; reg [31:0] inst_r;
reg stall_flag; reg stall_flag;
reg [ 6:0] ex_load_buffer; reg [ 6:0] ex_load_buffer;
reg ex_csr_buffer; reg ex_csr_buffer;
wire br_flush; wire br_flush;
wire [31:0] ds_pc; wire [31:0] ds_pc;
wire src1_is_pc; wire src1_is_pc;
wire src2_is_imm; wire src2_is_imm;
wire src2_is_4; wire src2_is_4;
wire src_reg_is_rd; wire src_reg_is_rd;
wire [ 4:0] rj; wire [ 4:0] rj;
wire [ 4:0] rk; wire [ 4:0] rk;
wire [ 4:0] rd; wire [ 4:0] rd;
wire [ 4:0] rkd; wire [ 4:0] rkd;
wire [31:0] imm; wire [31:0] imm;
wire [ 4:0] dest; wire [ 4:0] dest;
wire [11:0] alu_op; wire [11:0] alu_op;
wire [ 3:0] mul_div_op; wire [ 3:0] mul_div_op;
wire mul_div_sign; wire mul_div_sign;
wire [ 8:0] branch_op; wire [ 8:0] branch_op;
wire [ 5:0] load_op; wire [ 5:0] load_op;
wire [ 2:0] store_op; wire [ 2:0] store_op;
wire reg_we; wire reg_we;
wire csr_we; wire csr_we;
wire [ 6:0] csr_op; wire [ 6:0] csr_op;
wire [13:0] csr_addr; wire [13:0] csr_addr;
wire csr_wdata_sel; wire csr_wdata_sel;
wire [31:0] inst; wire [31:0] inst;
wire [31:0] next_inst; wire [31:0] next_inst;
wire [ 4:0] rf_raddr1; wire [ 4:0] rf_raddr1;
wire [31:0] rf_rdata1; wire [31:0] rf_rdata1;
wire [ 4:0] rf_raddr2; wire [ 4:0] rf_raddr2;
wire [31:0] rf_rdata2; wire [31:0] rf_rdata2;
wire rf_we; wire rf_we;
wire [ 4:0] rf_waddr; wire [ 4:0] rf_waddr;
wire [31:0] rf_wdata; wire [31:0] rf_wdata;
wire [31:0] rj_value; wire [31:0] rj_value;
wire [31:0] rkd_value; wire [31:0] rkd_value;
wire [ 4:0] ex_rf_waddr; wire [ 4:0] ex_rf_waddr;
wire ex_is_load; wire ex_is_load;
wire ex_is_csr; wire ex_is_csr;
wire ex_rf_we; wire ex_rf_we;
wire stallreq_load; wire stallreq_load;
wire stallreq_csr; wire stallreq_csr;
wire excp_adef; wire excp_adef;
wire [31:0] csr_vec_h; wire [31:0] csr_vec_h;
wire [31:0] csr_vec_l; wire [31:0] csr_vec_l;
wire [63:0] csr_vec; wire [63:0] csr_vec;
assign {csr_vec_h, assign {csr_vec_h,
excp_adef, excp_adef,
ds_pc ds_pc
} = fs_to_ds_bus_r; } = fs_to_ds_bus_r;
assign csr_vec = {csr_vec_h, csr_vec_l}; assign csr_vec = {csr_vec_h, csr_vec_l};
assign br_flush = br_taken; assign br_flush = br_taken;
assign {rf_we , //37:37 assign {rf_we , //37:37
rf_waddr, //36:32 rf_waddr, //36:32
rf_wdata //31:0 rf_wdata //31:0
} = ws_to_rf_bus; } = ws_to_rf_bus;
assign ds_to_es_bus = {csr_vec & {64{pc_valid_r}} ,//300:237 assign ds_to_es_bus = {csr_vec & {64{pc_valid_r}} ,//300:237
csr_op ,//236:230 csr_op ,//236:230
csr_wdata_sel ,//229:229 csr_wdata_sel ,//229:229
csr_addr ,//228:215 csr_addr ,//228:215
csr_we ,//214:214 csr_we ,//214:214
alu_op ,//213:202 alu_op ,//213:202
mul_div_op & {4{pc_valid_r}} ,//198:189 mul_div_op & {4{pc_valid_r}} ,//198:189
mul_div_sign & pc_valid_r ,//197:197 mul_div_sign & pc_valid_r ,//197:197
branch_op & {9{pc_valid_r}} ,//196:188 branch_op & {9{pc_valid_r}} ,//196:188
store_op & {3{pc_valid_r}} ,//187:185 store_op & {3{pc_valid_r}} ,//187:185
load_op & {6{pc_valid_r}} ,//184:179 load_op & {6{pc_valid_r}} ,//184:179
reg_we & pc_valid_r ,//178:178 reg_we & pc_valid_r ,//178:178
src1_is_pc ,//177:177 src1_is_pc ,//177:177
src2_is_imm ,//176:176 src2_is_imm ,//176:176
src2_is_4 ,//175:175 src2_is_4 ,//175:175
rj ,//174:170 rj ,//174:170
rkd ,//169:165 rkd ,//169:165
rj_value ,//164:133 rj_value ,//164:133
rkd_value ,//132:101 rkd_value ,//132:101
dest ,//100:96 dest ,//100:96
imm ,//95 :64 imm ,//95 :64
ds_pc ,//63 :32 ds_pc ,//63 :32
inst & {32{pc_valid_r}} //31 :0 inst & {32{pc_valid_r}} //31 :0
}; };
always @ (posedge clk)begin always @ (posedge clk)begin
if (reset) begin if (reset) begin
pc_valid_r <= 1'b0; pc_valid_r <= 1'b0;
fs_to_ds_bus_r <= 0; fs_to_ds_bus_r <= 0;
end end
else if (flush) begin else if (flush) begin
pc_valid_r <= 1'b0; pc_valid_r <= 1'b0;
fs_to_ds_bus_r <= 0; fs_to_ds_bus_r <= 0;
end end
//nop, ID stall and EX not stall //nop, ID stall and EX not stall
else if (stall[1] & (!stall[2]))begin else if (stall[1] & (!stall[2]))begin
pc_valid_r <= 1'b0; pc_valid_r <= 1'b0;
fs_to_ds_bus_r <= 0; fs_to_ds_bus_r <= 0;
end end
//nop, ID not stall but branch //nop, ID not stall but branch
else if (!stall[1] & br_flush) begin else if (!stall[1] & br_flush) begin
pc_valid_r <= 1'b0; pc_valid_r <= 1'b0;
fs_to_ds_bus_r <= 0; fs_to_ds_bus_r <= 0;
end end
// ID not stall so go on // ID not stall so go on
else if (!stall[1]) begin else if (!stall[1]) begin
pc_valid_r <= pc_valid; pc_valid_r <= pc_valid;
fs_to_ds_bus_r <= fs_to_ds_bus; fs_to_ds_bus_r <= fs_to_ds_bus;
end end
end end
always @ (posedge clk) begin always @ (posedge clk) begin
if (reset) begin if (reset) begin
inst_r <= 64'b0; inst_r <= 64'b0;
stall_flag <= 1'b0; stall_flag <= 1'b0;
end end
else if (flush) begin else if (flush) begin
inst_r <= 64'b0; inst_r <= 64'b0;
stall_flag <= 1'b0; stall_flag <= 1'b0;
end end
//if not stall, get inst from inst_sram //if not stall, get inst from inst_sram
else if (!stall[1]) begin else if (!stall[1]) begin
inst_r <= inst_sram_rdata; inst_r <= inst_sram_rdata;
stall_flag <= 1'b0; stall_flag <= 1'b0;
end end
else if (stall_flag) begin else if (stall_flag) begin
end end
//if stall and id stall, get inst from inst_ram ? //if stall and id stall, get inst from inst_ram ?
else if (stall[1]&stall[2]) begin else if (stall[1]&stall[2]) begin
inst_r <= inst_sram_rdata; inst_r <= inst_sram_rdata;
stall_flag <= 1'b1; stall_flag <= 1'b1;
end end
end end
assign next_inst = stall_flag ? inst_r : inst_sram_rdata; assign next_inst = stall_flag ? inst_r : inst_sram_rdata;
assign inst = ~pc_valid_r ? 32'b0 : next_inst; assign inst = ~pc_valid_r ? 32'b0 : next_inst;
inst_decoder u_inst_decoder( inst_decoder u_inst_decoder(
.inst (inst ), .inst (inst ),
.src1_is_pc (src1_is_pc ), .src1_is_pc (src1_is_pc ),
.src2_is_imm (src2_is_imm ), .src2_is_imm (src2_is_imm ),
.src2_is_4 (src2_is_4 ), .src2_is_4 (src2_is_4 ),
.src_reg_is_rd (src_reg_is_rd ), .src_reg_is_rd (src_reg_is_rd ),
.rj (rj ), .rj (rj ),
.rk (rk ), .rk (rk ),
.rd (rd ), .rd (rd ),
.imm (imm ), .imm (imm ),
.dest (dest ), .dest (dest ),
.alu_op (alu_op ), .alu_op (alu_op ),
.mul_div_op (mul_div_op ), .mul_div_op (mul_div_op ),
.mul_div_sign (mul_div_sign ), .mul_div_sign (mul_div_sign ),
.branch_op (branch_op ), .branch_op (branch_op ),
.load_op (load_op ), .load_op (load_op ),
.store_op (store_op ), .store_op (store_op ),
.excp_adef (excp_adef ), .excp_adef (excp_adef ),
.csr_plv (csr_plv ), .csr_plv (csr_plv ),
.csr_has_int (csr_has_int ), .csr_has_int (csr_has_int ),
.csr_we (csr_we ), .csr_we (csr_we ),
.csr_op (csr_op ), .csr_op (csr_op ),
.csr_addr (csr_addr ), .csr_addr (csr_addr ),
.csr_wdata_sel (csr_wdata_sel ), .csr_wdata_sel (csr_wdata_sel ),
.csr_vec_l (csr_vec_l ), .csr_vec_l (csr_vec_l ),
.reg_we (reg_we ) .reg_we (reg_we )
); );
assign rf_raddr1 = rj; assign rf_raddr1 = rj;
assign rf_raddr2 = src_reg_is_rd ? rd : rk; assign rf_raddr2 = src_reg_is_rd ? rd : rk;
assign rkd = src_reg_is_rd ? rd : rk; assign rkd = src_reg_is_rd ? rd : rk;
regfile u_regfile( regfile u_regfile(
.clk (clk ), .clk (clk ),
.reset (reset ), .reset (reset ),
.raddr1 (rf_raddr1), .raddr1 (rf_raddr1),
.rdata1 (rf_rdata1), .rdata1 (rf_rdata1),
.raddr2 (rf_raddr2), .raddr2 (rf_raddr2),
.rdata2 (rf_rdata2), .rdata2 (rf_rdata2),
.we (rf_we ), .we (rf_we ),
.waddr (rf_waddr ), .waddr (rf_waddr ),
.wdata (rf_wdata ) .wdata (rf_wdata )
); );
assign rj_value = rf_rdata1; assign rj_value = rf_rdata1;
assign rkd_value = rf_rdata2; assign rkd_value = rf_rdata2;
always @ (posedge clk) begin always @ (posedge clk) begin
if (reset) begin if (reset) begin
ex_load_buffer <= 7'b0; ex_load_buffer <= 7'b0;
ex_csr_buffer <= 1'b0; ex_csr_buffer <= 1'b0;
end end
else if (flush) begin else if (flush) begin
ex_load_buffer <= 7'b0; ex_load_buffer <= 7'b0;
ex_csr_buffer <= 1'b0; ex_csr_buffer <= 1'b0;
end end
else if (stall[2]&(!stall[3])) begin else if (stall[2]&(!stall[3])) begin
ex_load_buffer <= 7'b0; ex_load_buffer <= 7'b0;
ex_csr_buffer <= 1'b0; ex_csr_buffer <= 1'b0;
end end
else if (!stall[2]) begin else if (!stall[2]) begin
ex_load_buffer <= {|load_op, rf_we, rf_waddr}; ex_load_buffer <= {|load_op, rf_we, rf_waddr};
ex_csr_buffer <= |csr_op; ex_csr_buffer <= |csr_op;
end end
end end
assign {ex_is_load, assign {ex_is_load,
ex_rf_we, ex_rf_we,
ex_rf_waddr ex_rf_waddr
} = ex_load_buffer; } = ex_load_buffer;
assign ex_is_csr = ex_csr_buffer; assign ex_is_csr = ex_csr_buffer;
//ex段为load指令，且发生数据相关时，id段需要被暂停 //ex段为load指令，且发生数据相关时，id段需要被暂停
assign stallreq_load = ex_is_load & ex_rf_we & ((ex_rf_waddr==rj_value & rj_value!=0)|(ex_rf_waddr==rkd_value & rkd_value!=0)); assign stallreq_load = ex_is_load & ex_rf_we & ((ex_rf_waddr==rj_value & rj_value!=0)|(ex_rf_waddr==rkd_value & rkd_value!=0));
assign stallreq_csr = ex_is_csr & ex_rf_we & ((ex_rf_waddr==rj_value & rj_value!=0)|(ex_rf_waddr==rkd_value & rkd_value!=0)); assign stallreq_csr = ex_is_csr & ex_rf_we & ((ex_rf_waddr==rj_value & rj_value!=0)|(ex_rf_waddr==rkd_value & rkd_value!=0));
assign stallreq_ds = stallreq_load | stallreq_csr; assign stallreq_ds = stallreq_load | stallreq_csr;
endmodule endmodule

150
lacpu/rtl/cpu/if_stage.v → lacpu/rtl/mycpu/if_stage.v Executable file → Normal file
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@@ -1,76 +1,76 @@
module if_stage module if_stage
#( #(
parameter BR_BUS_WD = 33, parameter BR_BUS_WD = 33,
parameter FS_TO_DS_BUS_WD = 65 parameter FS_TO_DS_BUS_WD = 65
) )
( (
input clk , input clk ,
input reset, input reset,
input flush, input flush,
input [ 5:0] stall, input [ 5:0] stall,
input [31:0] new_pc, input [31:0] new_pc,
input timer_int, input timer_int,
output inst_sram_en , output inst_sram_en ,
output [ 3:0] inst_sram_we , output [ 3:0] inst_sram_we ,
output [31:0] inst_sram_addr , output [31:0] inst_sram_addr ,
output [31:0] inst_sram_wdata, output [31:0] inst_sram_wdata,
input [BR_BUS_WD -1:0] br_bus, input [BR_BUS_WD -1:0] br_bus,
output [FS_TO_DS_BUS_WD -1:0] fs_to_ds_bus output [FS_TO_DS_BUS_WD -1:0] fs_to_ds_bus
); );
reg pc_valid; reg pc_valid;
reg [31:0] fs_pc; reg [31:0] fs_pc;
reg excp_adef; reg excp_adef;
reg [31:0] csr_vec_h; reg [31:0] csr_vec_h;
wire [31:0] seq_pc; wire [31:0] seq_pc;
wire [31:0] next_pc; wire [31:0] next_pc;
wire br_taken; wire br_taken;
wire [31:0] br_target; wire [31:0] br_target;
assign fs_to_ds_bus = {csr_vec_h, //64:33 assign fs_to_ds_bus = {csr_vec_h, //64:33
excp_adef, //32:32 excp_adef, //32:32
fs_pc //31:0 fs_pc //31:0
}; };
assign {br_taken, assign {br_taken,
br_target br_target
} = br_bus; } = br_bus;
always @ (posedge clk) begin always @ (posedge clk) begin
if (reset) begin if (reset) begin
pc_valid <= 1'b0; pc_valid <= 1'b0;
fs_pc <= 32'h1bff_fffc; fs_pc <= 32'h1bff_fffc;
excp_adef <= 1'b0; excp_adef <= 1'b0;
csr_vec_h <= 32'b0; csr_vec_h <= 32'b0;
end end
else if (flush) begin else if (flush) begin
pc_valid <= 1'b1; pc_valid <= 1'b1;
fs_pc <= new_pc; fs_pc <= new_pc;
excp_adef <= |new_pc[1:0]; excp_adef <= |new_pc[1:0];
csr_vec_h <= 32'b0; csr_vec_h <= 32'b0;
end end
else if (!stall[0]) begin else if (!stall[0]) begin
pc_valid <= 1'b1; pc_valid <= 1'b1;
fs_pc <= next_pc; fs_pc <= next_pc;
excp_adef <= |next_pc[1:0]; excp_adef <= |next_pc[1:0];
csr_vec_h <= 0; // timer_int; TODO! csr_vec_h <= 0; // timer_int; TODO!
end end
end end
assign seq_pc = fs_pc + 3'h4; assign seq_pc = fs_pc + 3'h4;
assign next_pc = br_taken ? br_target : seq_pc; assign next_pc = br_taken ? br_target : seq_pc;
assign inst_sram_en = flush | (br_taken ? 1'b0 : pc_valid); assign inst_sram_en = flush | (br_taken ? 1'b0 : pc_valid);
assign inst_sram_we = 4'h0; assign inst_sram_we = 4'h0;
assign inst_sram_addr = fs_pc; assign inst_sram_addr = fs_pc;
assign inst_sram_wdata = 32'b0; assign inst_sram_wdata = 32'b0;
endmodule endmodule

0
lacpu/rtl/cpu/inst_decoder.v → lacpu/rtl/mycpu/inst_decoder.v
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0
lacpu/rtl/cpu/lsu.v → lacpu/rtl/mycpu/lsu.v
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387
lacpu/rtl/cpu/mem_stage.v → lacpu/rtl/mycpu/mem_stage.v Executable file → Normal file
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@@ -1,193 +1,196 @@
module mem_stage module mem_stage
#( #(
parameter ES_TO_MS_BUS_WD = 271, parameter ES_TO_MS_BUS_WD = 271,
parameter MS_TO_ES_BUS_WD = 38, parameter MS_TO_ES_BUS_WD = 38,
parameter MS_TO_WS_BUS_WD = 102 parameter MS_TO_WS_BUS_WD = 102
) )
( (
input clk, input clk,
input reset, input reset,
input flush, input flush,
input [ 5:0] stall, input [ 5:0] stall,
output except_en, output except_en,
output [31:0] new_pc, output [31:0] new_pc,
output [ 1:0] csr_plv, output [ 1:0] csr_plv,
output csr_has_int, output csr_has_int,
input [ES_TO_MS_BUS_WD -1:0] es_to_ms_bus, input stallreq_axi,
output [MS_TO_ES_BUS_WD -1:0] ms_to_es_bus,
output [MS_TO_WS_BUS_WD -1:0] ms_to_ws_bus, input [ES_TO_MS_BUS_WD -1:0] es_to_ms_bus,
output [MS_TO_ES_BUS_WD -1:0] ms_to_es_bus,
input [31:0] data_sram_rdata output [MS_TO_WS_BUS_WD -1:0] ms_to_ws_bus,
);
input [31:0] data_sram_rdata
reg [ES_TO_MS_BUS_WD -1:0] es_to_ms_bus_r; );
reg [31:0] data_sram_rdata_r;
reg [31:0] csr_rdata_r; reg [ES_TO_MS_BUS_WD -1:0] es_to_ms_bus_r;
reg stall_flag; reg [31:0] data_sram_rdata_r;
reg [31:0] csr_rdata_r;
wire [63:0] csr_vec; reg stall_flag;
wire [63:0] csr_bus;
wire [ 5:0] load_op; wire [63:0] csr_vec;
wire [ 2:0] store_op; wire [63:0] csr_bus;
wire reg_we; wire [ 5:0] load_op;
wire [ 4:0] dest; wire [ 2:0] store_op;
wire [31:0] es_result; wire reg_we;
wire [31:0] ms_pc; wire [ 4:0] dest;
wire [31:0] inst; wire [31:0] es_result;
wire [31:0] ms_pc;
wire [31:0] data_temp; wire [31:0] inst;
wire [31:0] csr_result;
wire [31:0] csr_rdata; wire [31:0] data_temp;
wire [31:0] csr_result;
wire inst_ll_w; wire [31:0] csr_rdata;
wire inst_ld_b;
wire inst_ld_bu; wire inst_ll_w;
wire inst_ld_h; wire inst_ld_b;
wire inst_ld_hu; wire inst_ld_bu;
wire inst_ld_w; wire inst_ld_h;
wire inst_ld_hu;
wire [ 3:0] byte_sel; wire inst_ld_w;
wire [31:0] ms_result;
wire [ 3:0] byte_sel;
wire csr_we; wire [31:0] ms_result;
wire csr_wdata_sel;
wire [ 6:0] csr_op; wire csr_we;
wire [13:0] csr_addr; wire csr_wdata_sel;
wire [31:0] csr_wdata; wire [ 6:0] csr_op;
wire [13:0] csr_addr;
wire [31:0] csr_wdata;
wire [31:0] src1;
wire [31:0] ms_final_result; wire [31:0] src1;
assign {csr_vec ,//270:207 wire [31:0] ms_final_result;
csr_bus ,//206:143
load_op ,//142:137 assign {csr_vec ,//270:207
store_op ,//136:134 csr_bus ,//206:143
reg_we ,//133:133 load_op ,//142:137
dest ,//132:128 store_op ,//136:134
es_result,//127:96 reg_we ,//133:133
src1 ,//95 :64 dest ,//132:128
ms_pc ,//63 :32 es_result,//127:96
inst //31 :0 src1 ,//95 :64
} = es_to_ms_bus_r; ms_pc ,//63 :32
inst //31 :0
assign ms_to_es_bus = {reg_we, } = es_to_ms_bus_r;
dest,
ms_final_result assign ms_to_es_bus = {reg_we,
}; dest,
ms_final_result
assign ms_to_ws_bus = {reg_we ,//101:101 };
dest ,//100:96
ms_final_result ,//95 :64 assign ms_to_ws_bus = {reg_we ,//101:101
ms_pc ,//63 :32 dest ,//100:96
inst //31 :0 ms_final_result ,//95 :64
}; ms_pc ,//63 :32
inst //31 :0
always @ (posedge clk) begin };
if (reset) begin
es_to_ms_bus_r <= 0; always @ (posedge clk) begin
end if (reset) begin
else if (flush) begin es_to_ms_bus_r <= 0;
es_to_ms_bus_r <= 0; end
end else if (flush) begin
else if (stall[3]&(!stall[4])) begin es_to_ms_bus_r <= 0;
es_to_ms_bus_r <= 0; end
end else if (stall[3]&(!stall[4])) begin
else if (!stall[3]) begin es_to_ms_bus_r <= 0;
es_to_ms_bus_r <= es_to_ms_bus; end
end else if (!stall[3]) begin
end es_to_ms_bus_r <= es_to_ms_bus;
end
always @ (posedge clk) begin end
if (reset) begin
data_sram_rdata_r <= 0; always @ (posedge clk) begin
csr_rdata_r <= 0; if (reset) begin
stall_flag <= 1'b0; data_sram_rdata_r <= 0;
end csr_rdata_r <= 0;
else if (flush) begin stall_flag <= 1'b0;
data_sram_rdata_r <= 0; end
csr_rdata_r <= 0; else if (flush) begin
stall_flag <= 1'b0; data_sram_rdata_r <= 0;
end csr_rdata_r <= 0;
else if (!stall[3]) begin stall_flag <= 1'b0;
data_sram_rdata_r <= data_sram_rdata; end
csr_rdata_r <= csr_rdata; else if (!stall[3]) begin
stall_flag <= 1'b0; data_sram_rdata_r <= data_sram_rdata;
end csr_rdata_r <= csr_rdata;
else if (stall_flag) begin stall_flag <= 1'b0;
end
end else if (stall_flag) begin
else if (stall[3]&stall[4])begin
data_sram_rdata_r <= data_sram_rdata; end
csr_rdata_r <= csr_rdata; else if (stall[3]&stall[4])begin
stall_flag <= 1'b1; data_sram_rdata_r <= data_sram_rdata;
end csr_rdata_r <= csr_rdata;
end stall_flag <= 1'b1;
end
assign data_temp = stall_flag ? data_sram_rdata_r : data_sram_rdata; end
assign csr_result = stall_flag ? csr_rdata_r : csr_rdata;
assign data_temp = stall_flag ? data_sram_rdata_r : data_sram_rdata;
assign {inst_ld_b, assign csr_result = stall_flag ? csr_rdata_r : csr_rdata;
inst_ld_h,
inst_ld_w, assign {inst_ld_b,
inst_ld_bu, inst_ld_h,
inst_ld_hu, inst_ld_w,
inst_ll_w inst_ld_bu,
} = load_op; inst_ld_hu,
inst_ll_w
decoder_2_4 u_decoder_2_4( } = load_op;
.in (es_result[1:0]),
.out(byte_sel ) decoder_2_4 u_decoder_2_4(
); .in (es_result[1:0]),
.out(byte_sel )
assign ms_result = (inst_ld_b & byte_sel[0]) ? {{24{data_temp[ 7]}}, data_temp[ 7: 0]} : );
(inst_ld_b & byte_sel[1]) ? {{24{data_temp[15]}}, data_temp[15: 8]} :
(inst_ld_b & byte_sel[2]) ? {{24{data_temp[23]}}, data_temp[23:16]} : assign ms_result = (inst_ld_b & byte_sel[0]) ? {{24{data_temp[ 7]}}, data_temp[ 7: 0]} :
(inst_ld_b & byte_sel[3]) ? {{24{data_temp[31]}}, data_temp[31:24]} : (inst_ld_b & byte_sel[1]) ? {{24{data_temp[15]}}, data_temp[15: 8]} :
(inst_ld_bu & byte_sel[0]) ? { 24'b0, data_temp[ 7: 0]} : (inst_ld_b & byte_sel[2]) ? {{24{data_temp[23]}}, data_temp[23:16]} :
(inst_ld_bu & byte_sel[1]) ? { 24'b0, data_temp[15: 8]} : (inst_ld_b & byte_sel[3]) ? {{24{data_temp[31]}}, data_temp[31:24]} :
(inst_ld_bu & byte_sel[2]) ? { 24'b0, data_temp[23:16]} : (inst_ld_bu & byte_sel[0]) ? { 24'b0, data_temp[ 7: 0]} :
(inst_ld_bu & byte_sel[3]) ? { 24'b0, data_temp[31:24]} : (inst_ld_bu & byte_sel[1]) ? { 24'b0, data_temp[15: 8]} :
(inst_ld_h & byte_sel[0]) ? {{16{data_temp[15]}}, data_temp[15: 0]} : (inst_ld_bu & byte_sel[2]) ? { 24'b0, data_temp[23:16]} :
(inst_ld_h & byte_sel[2]) ? {{16{data_temp[31]}}, data_temp[31:16]} : (inst_ld_bu & byte_sel[3]) ? { 24'b0, data_temp[31:24]} :
(inst_ld_hu & byte_sel[0]) ? { 16'b0, data_temp[15: 0]} : (inst_ld_h & byte_sel[0]) ? {{16{data_temp[15]}}, data_temp[15: 0]} :
(inst_ld_hu & byte_sel[2]) ? { 16'b0, data_temp[31:16]} : (inst_ld_h & byte_sel[2]) ? {{16{data_temp[31]}}, data_temp[31:16]} :
(inst_ld_w & byte_sel[0]) ? data_temp : (inst_ld_hu & byte_sel[0]) ? { 16'b0, data_temp[15: 0]} :
32'b0; // inst_ll ? (inst_ld_hu & byte_sel[2]) ? { 16'b0, data_temp[31:16]} :
(inst_ld_w & byte_sel[0]) ? data_temp :
assign {csr_we, 32'b0; // inst_ll ?
csr_wdata_sel,
csr_op, assign {csr_we,
csr_addr, csr_wdata_sel,
csr_wdata csr_op,
} = csr_bus; csr_addr,
csr_wdata
csr u_csr( } = csr_bus;
.clk (clk ),
.reset (reset ), csr u_csr(
.stall (stall[3]&stall[4] ), .clk (clk ),
.pc (ms_pc ), .reset (reset ),
.src1 (src1 ), .stall (stall[3]&stall[4] ),
.error_va (es_result ), .pc (ms_pc ),
.plv_out (csr_plv ), .src1 (src1 ),
.has_int_out (csr_has_int ), .error_va (es_result ),
.csr_we (csr_we ), .plv_out (csr_plv ),
.csr_vec (csr_vec ), .has_int_out (csr_has_int ),
.csr_op (csr_op ), .csr_we (csr_we ),
.csr_addr (csr_addr ), .csr_vec (csr_vec ),
.csr_wdata_sel (csr_wdata_sel ), .csr_op (csr_op ),
.csr_wdata (csr_wdata ), .csr_addr (csr_addr ),
.csr_rdata (csr_rdata ), .csr_wdata_sel (csr_wdata_sel ),
.except_en (except_en ), .csr_wdata (csr_wdata ),
.new_pc (new_pc ) .csr_rdata (csr_rdata ),
); .except_en (except_en ),
.new_pc (new_pc ),
assign ms_final_result = (|load_op) ? ms_result : .stallreq_axi (stallreq_axi )
(|csr_op ) ? csr_result : );
es_result;
assign ms_final_result = (|load_op) ? ms_result :
(|csr_op ) ? csr_result :
es_result;
endmodule endmodule

0
lacpu/rtl/cpu/mmu.v → lacpu/rtl/mycpu/mmu.v
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0
lacpu/rtl/cpu/mul.v → lacpu/rtl/mycpu/mul.v
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0
lacpu/rtl/cpu/mul_div_lock.v → lacpu/rtl/mycpu/mul_div_lock.v
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0
lacpu/rtl/cpu/mul_div_top.v → lacpu/rtl/mycpu/mul_div_top.v
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3
lacpu/rtl/cpu/mycpu_core.v → lacpu/rtl/mycpu/mycpu_core.v
View File

@@ -129,6 +129,7 @@ module mycpu_core
.new_pc (new_pc ), .new_pc (new_pc ),
.csr_plv (csr_plv ), .csr_plv (csr_plv ),
.csr_has_int (csr_has_int ), .csr_has_int (csr_has_int ),
.stallreq_axi (stallreq_cache ),
.es_to_ms_bus (es_to_ms_bus ), .es_to_ms_bus (es_to_ms_bus ),
.ms_to_es_bus (ms_to_es_bus ), .ms_to_es_bus (ms_to_es_bus ),
@@ -158,7 +159,7 @@ module mycpu_core
.except_en (except_en ), .except_en (except_en ),
.stallreq_ds (stallreq_ds ), .stallreq_ds (stallreq_ds ),
.stallreq_es (stallreq_es ), .stallreq_es (stallreq_es ),
.stallreq_axi (1'b0 ), // TODO! .stallreq_axi (stallreq_cache ), // TODO!
.stallreq_cache (stallreq_cache ), .stallreq_cache (stallreq_cache ),
.flush (flush ), .flush (flush ),
.stall (stall ) .stall (stall )

0
lacpu/rtl/cpu/mycpu_top.v → lacpu/rtl/mycpu/mycpu_top.v
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8
lacpu/rtl/cpu/pip_ctrl.v → lacpu/rtl/mycpu/pip_ctrl.v
View File

@@ -37,10 +37,10 @@ module pip_ctrl(
flush = 0; flush = 0;
stall = `StallBus'b011111; stall = `StallBus'b011111;
end end
else if(stallreq_cache) begin // else if(stallreq_cache) begin
flush = 0; // flush = 0;
stall = `StallBus'b111111; // stall = `StallBus'b111111;
end // end
else begin else begin
flush = 0; flush = 0;
stall = `StallBus'b000000; stall = `StallBus'b000000;

134
lacpu/rtl/cpu/regfile.v → lacpu/rtl/mycpu/regfile.v Executable file → Normal file
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@@ -1,68 +1,68 @@
module regfile( module regfile(
input clk, input clk,
input reset, input reset,
// READ PORT 1 // READ PORT 1
input [ 4:0] raddr1, input [ 4:0] raddr1,
output [31:0] rdata1, output [31:0] rdata1,
// READ PORT 2 // READ PORT 2
input [ 4:0] raddr2, input [ 4:0] raddr2,
output [31:0] rdata2, output [31:0] rdata2,
// WRITE PORT // WRITE PORT
input we, //write enable, HIGH valid input we, //write enable, HIGH valid
input [ 4:0] waddr, input [ 4:0] waddr,
input [31:0] wdata input [31:0] wdata
); );
reg [31:0] rf[31:0]; reg [31:0] rf[31:0];
//WRITE //WRITE
always @(posedge clk) begin always @(posedge clk) begin
if (reset) begin if (reset) begin
rf[ 0] <= 32'b0; rf[ 0] <= 32'b0;
rf[ 1] <= 32'b0; rf[ 1] <= 32'b0;
rf[ 2] <= 32'b0; rf[ 2] <= 32'b0;
rf[ 3] <= 32'b0; rf[ 3] <= 32'b0;
rf[ 4] <= 32'b0; rf[ 4] <= 32'b0;
rf[ 5] <= 32'b0; rf[ 5] <= 32'b0;
rf[ 6] <= 32'b0; rf[ 6] <= 32'b0;
rf[ 7] <= 32'b0; rf[ 7] <= 32'b0;
rf[ 8] <= 32'b0; rf[ 8] <= 32'b0;
rf[ 9] <= 32'b0; rf[ 9] <= 32'b0;
rf[10] <= 32'b0; rf[10] <= 32'b0;
rf[11] <= 32'b0; rf[11] <= 32'b0;
rf[12] <= 32'b0; rf[12] <= 32'b0;
rf[13] <= 32'b0; rf[13] <= 32'b0;
rf[14] <= 32'b0; rf[14] <= 32'b0;
rf[15] <= 32'b0; rf[15] <= 32'b0;
rf[16] <= 32'b0; rf[16] <= 32'b0;
rf[17] <= 32'b0; rf[17] <= 32'b0;
rf[18] <= 32'b0; rf[18] <= 32'b0;
rf[19] <= 32'b0; rf[19] <= 32'b0;
rf[20] <= 32'b0; rf[20] <= 32'b0;
rf[21] <= 32'b0; rf[21] <= 32'b0;
rf[22] <= 32'b0; rf[22] <= 32'b0;
rf[23] <= 32'b0; rf[23] <= 32'b0;
rf[24] <= 32'b0; rf[24] <= 32'b0;
rf[25] <= 32'b0; rf[25] <= 32'b0;
rf[26] <= 32'b0; rf[26] <= 32'b0;
rf[27] <= 32'b0; rf[27] <= 32'b0;
rf[28] <= 32'b0; rf[28] <= 32'b0;
rf[29] <= 32'b0; rf[29] <= 32'b0;
rf[30] <= 32'b0; rf[30] <= 32'b0;
rf[31] <= 32'b0; rf[31] <= 32'b0;
end end
else if (we) begin else if (we) begin
rf[waddr]<= wdata; rf[waddr]<= wdata;
end end
end end
//READ OUT 1 //READ OUT 1
assign rdata1 = (raddr1==5'b0 ) ? 32'b0 : assign rdata1 = (raddr1==5'b0 ) ? 32'b0 :
(raddr1==waddr) & we ? wdata : (raddr1==waddr) & we ? wdata :
rf[raddr1]; rf[raddr1];
//READ OUT 2 //READ OUT 2
assign rdata2 = (raddr2==5'b0 ) ? 32'b0 : assign rdata2 = (raddr2==5'b0 ) ? 32'b0 :
(raddr2==waddr) & we ? wdata : (raddr2==waddr) & we ? wdata :
rf[raddr2]; rf[raddr2];
endmodule endmodule

0
lacpu/rtl/cpu/tlb.v → lacpu/rtl/mycpu/tlb.v
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108
lacpu/rtl/cpu/tools.v → lacpu/rtl/mycpu/tools.v Executable file → Normal file
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@@ -1,54 +1,54 @@
`default_nettype wire `default_nettype wire
module decoder_2_4( module decoder_2_4(
input [ 1:0] in, input [ 1:0] in,
output [ 3:0] out output [ 3:0] out
); );
genvar i; genvar i;
generate for (i=0; i<4; i=i+1) begin : gen_for_dec_2_4 generate for (i=0; i<4; i=i+1) begin : gen_for_dec_2_4
assign out[i] = (in == i); assign out[i] = (in == i);
end endgenerate end endgenerate
endmodule endmodule
module decoder_4_16( module decoder_4_16(
input [ 3:0] in, input [ 3:0] in,
output [15:0] out output [15:0] out
); );
genvar i; genvar i;
generate for (i=0; i<16; i=i+1) begin : gen_for_dec_4_16 generate for (i=0; i<16; i=i+1) begin : gen_for_dec_4_16
assign out[i] = (in == i); assign out[i] = (in == i);
end endgenerate end endgenerate
endmodule endmodule
module decoder_5_32( module decoder_5_32(
input [ 4:0] in, input [ 4:0] in,
output [31:0] out output [31:0] out
); );
genvar i; genvar i;
generate for (i=0; i<32; i=i+1) begin : gen_for_dec_5_32 generate for (i=0; i<32; i=i+1) begin : gen_for_dec_5_32
assign out[i] = (in == i); assign out[i] = (in == i);
end endgenerate end endgenerate
endmodule endmodule
module decoder_6_64( module decoder_6_64(
input [ 5:0] in, input [ 5:0] in,
output [63:0] out output [63:0] out
); );
genvar i; genvar i;
generate for (i=0; i<64; i=i+1) begin : gen_for_dec_6_64 //bug7 generate for (i=0; i<64; i=i+1) begin : gen_for_dec_6_64 //bug7
assign out[i] = (in == i); assign out[i] = (in == i);
end endgenerate end endgenerate
endmodule endmodule

0
lacpu/rtl/cpu/uncache.v → lacpu/rtl/mycpu/uncache.v
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134
lacpu/rtl/cpu/wb_stage.v → lacpu/rtl/mycpu/wb_stage.v Executable file → Normal file
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@@ -1,68 +1,68 @@
module wb_stage module wb_stage
#( #(
parameter MS_TO_WS_BUS_WD = 102, parameter MS_TO_WS_BUS_WD = 102,
parameter WS_TO_RF_BUS_WD = 38, parameter WS_TO_RF_BUS_WD = 38,
parameter WS_TO_ES_BUS_WD = 38 parameter WS_TO_ES_BUS_WD = 38
) )
( (
input clk, input clk,
input reset, input reset,
input flush, input flush,
input [5:0] stall, input [5:0] stall,
input [MS_TO_WS_BUS_WD -1:0] ms_to_ws_bus, input [MS_TO_WS_BUS_WD -1:0] ms_to_ws_bus,
output [WS_TO_RF_BUS_WD -1:0] ws_to_rf_bus, output [WS_TO_RF_BUS_WD -1:0] ws_to_rf_bus,
output [WS_TO_ES_BUS_WD -1:0] ws_to_es_bus, output [WS_TO_ES_BUS_WD -1:0] ws_to_es_bus,
output [31:0] debug_wb_pc, output [31:0] debug_wb_pc,
output [ 3:0] debug_wb_rf_we, output [ 3:0] debug_wb_rf_we,
output [ 4:0] debug_wb_rf_wnum, output [ 4:0] debug_wb_rf_wnum,
output [31:0] debug_wb_rf_wdata output [31:0] debug_wb_rf_wdata
); );
reg [MS_TO_WS_BUS_WD -1:0] ms_to_ws_bus_r; reg [MS_TO_WS_BUS_WD -1:0] ms_to_ws_bus_r;
wire reg_we; wire reg_we;
wire [ 4:0] dest; wire [ 4:0] dest;
wire [31:0] ms_final_result; wire [31:0] ms_final_result;
wire [31:0] ws_pc; wire [31:0] ws_pc;
wire [31:0] inst; wire [31:0] inst;
assign {reg_we ,//101:101 assign {reg_we ,//101:101
dest ,//100:96 dest ,//100:96
ms_final_result ,//95 :64 ms_final_result ,//95 :64
ws_pc ,//63 :32 ws_pc ,//63 :32
inst //31 :0 inst //31 :0
} = ms_to_ws_bus_r; } = ms_to_ws_bus_r;
assign ws_to_rf_bus = {reg_we, assign ws_to_rf_bus = {reg_we,
dest, dest,
ms_final_result ms_final_result
}; };
assign ws_to_es_bus = {reg_we, assign ws_to_es_bus = {reg_we,
dest, dest,
ms_final_result ms_final_result
}; };
always @ (posedge clk) begin always @ (posedge clk) begin
if (reset) begin if (reset) begin
ms_to_ws_bus_r <= 0; ms_to_ws_bus_r <= 0;
end end
else if (flush) begin else if (flush) begin
ms_to_ws_bus_r <= 0; ms_to_ws_bus_r <= 0;
end end
else if (stall[4]&(!stall[5])) begin else if (stall[4]&(!stall[5])) begin
ms_to_ws_bus_r <= 0; ms_to_ws_bus_r <= 0;
end end
else if (!stall[4]) begin else if (!stall[4]) begin
ms_to_ws_bus_r <= ms_to_ws_bus; ms_to_ws_bus_r <= ms_to_ws_bus;
end end
end end
assign debug_wb_pc = stall[5] ? 0 : ws_pc; assign debug_wb_pc = stall[5] ? 0 : ws_pc;
assign debug_wb_rf_we = stall[5] ? 0 : {4{reg_we}}; assign debug_wb_rf_we = stall[5] ? 0 : {4{reg_we}};
assign debug_wb_rf_wnum = stall[5] ? 0 : dest; assign debug_wb_rf_wnum = stall[5] ? 0 : dest;
assign debug_wb_rf_wdata = stall[5] ? 0 : ms_final_result; assign debug_wb_rf_wdata = stall[5] ? 0 : ms_final_result;
endmodule endmodule

293
lacpu/rtl/ram_wrap/axi_wrap_ram.v Normal file
View File

@@ -0,0 +1,293 @@
/*------------------------------------------------------------------------------
--------------------------------------------------------------------------------
Copyright (c) 2016, Loongson Technology Corporation Limited.
All rights reserved.
Redistribution and use in source and binary forms, with or without modification,
are permitted provided that the following conditions are met:
1. Redistributions of source code must retain the above copyright notice, this
list of conditions and the following disclaimer.
2. Redistributions in binary form must reproduce the above copyright notice,
this list of conditions and the following disclaimer in the documentation and/or
other materials provided with the distribution.
3. Neither the name of Loongson Technology Corporation Limited nor the names of
its contributors may be used to endorse or promote products derived from this
software without specific prior written permission.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
DISCLAIMED. IN NO EVENT SHALL LOONGSON TECHNOLOGY CORPORATION LIMITED BE LIABLE
TO ANY PARTY FOR DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE
GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
--------------------------------------------------------------------------------
------------------------------------------------------------------------------*/
//for func test, no define RUN_PERF_TEST
`define _RUN_PERF_TEST
module axi_wrap_ram(
input wire aclk,
input wire aresetn,
//ar
input wire [3 :0] axi_arid ,
input wire [31:0] axi_araddr ,
input wire [7 :0] axi_arlen ,
input wire [2 :0] axi_arsize ,
input wire [1 :0] axi_arburst,
input wire [1 :0] axi_arlock ,
input wire [3 :0] axi_arcache,
input wire [2 :0] axi_arprot ,
input wire axi_arvalid,
output wire axi_arready,
//r
output wire [3 :0] axi_rid ,
output wire [31:0] axi_rdata ,
output wire [1 :0] axi_rresp ,
output wire axi_rlast ,
output wire axi_rvalid ,
input wire axi_rready ,
//aw
input wire [3 :0] axi_awid ,
input wire [31:0] axi_awaddr ,
input wire [7 :0] axi_awlen ,
input wire [2 :0] axi_awsize ,
input wire [1 :0] axi_awburst,
input wire [1 :0] axi_awlock ,
input wire [3 :0] axi_awcache,
input wire [2 :0] axi_awprot ,
input wire axi_awvalid,
output wire axi_awready,
//w
input wire [3 :0] axi_wid ,
input wire [31:0] axi_wdata ,
input wire [3 :0] axi_wstrb ,
input wire axi_wlast ,
input wire axi_wvalid ,
output wire axi_wready ,
//b
output wire [3 :0] axi_bid ,
output wire [1 :0] axi_bresp ,
output wire axi_bvalid ,
input wire axi_bready ,
//from confreg
input wire [4 :0] ram_random_mask
);
wire axi_arvalid_m_masked;
wire axi_rready_m_masked;
wire axi_awvalid_m_masked;
wire axi_wvalid_m_masked;
wire axi_bready_m_masked;
wire axi_arready_s_unmasked;
wire axi_rvalid_s_unmasked;
wire axi_awready_s_unmasked;
wire axi_wready_s_unmasked;
wire axi_bvalid_s_unmasked;
wire ar_and;
wire r_and;
wire aw_and;
wire w_and;
wire b_and;
reg ar_nomask;
reg aw_nomask;
reg w_nomask;
reg [4:0] pf_r2r;
reg [1:0] pf_b2b;
wire pf_r2r_nomask= pf_r2r==5'd0;
wire pf_b2b_nomask= pf_b2b==2'd0;
//mask
`ifdef RUN_PERF_TEST
assign ar_and = 1'b1;
assign r_and = pf_r2r_nomask;
assign aw_and = 1'b1;
assign w_and = 1'b1;
assign b_and = pf_b2b_nomask;
`else
assign ar_and = ram_random_mask[4] | ar_nomask;
assign r_and = ram_random_mask[3] ;
assign aw_and = ram_random_mask[2] | aw_nomask;
assign w_and = ram_random_mask[1] | w_nomask;
assign b_and = ram_random_mask[0] ;
`endif
always @(posedge aclk)
begin
//for func test, random mask
ar_nomask <= !aresetn ? 1'b0 :
axi_arvalid_m_masked&&axi_arready ? 1'b0 :
axi_arvalid_m_masked ? 1'b1 : ar_nomask;
aw_nomask <= !aresetn ? 1'b0 :
axi_awvalid_m_masked&&axi_awready ? 1'b0 :
axi_awvalid_m_masked ? 1'b1 : aw_nomask;
w_nomask <= !aresetn ? 1'b0 :
axi_wvalid_m_masked&&axi_wready ? 1'b0 :
axi_wvalid_m_masked ? 1'b1 : w_nomask;
//for perf test
pf_r2r <= !aresetn ? 5'd0 :
axi_arvalid_m_masked&&axi_arready ? 5'd25 :
!pf_r2r_nomask ? pf_r2r-1'b1 : pf_r2r;
pf_b2b <= !aresetn ? 2'd0 :
axi_awvalid_m_masked&&axi_awready ? 2'd3 :
!pf_b2b_nomask ? pf_b2b-1'b1 : pf_b2b;
end
//-----{master -> slave}-----
assign axi_arvalid_m_masked = axi_arvalid & ar_and;
assign axi_rready_m_masked = axi_rready & r_and;
assign axi_awvalid_m_masked = axi_awvalid & aw_and;
assign axi_wvalid_m_masked = axi_wvalid & w_and;
assign axi_bready_m_masked = axi_bready & b_and;
//-----{slave -> master}-----
assign axi_arready = axi_arready_s_unmasked & ar_and;
assign axi_rvalid = axi_rvalid_s_unmasked & r_and;
assign axi_awready = axi_awready_s_unmasked & aw_and;
assign axi_wready = axi_wready_s_unmasked & w_and;
assign axi_bvalid = axi_bvalid_s_unmasked & b_and;
//ram axi
//ar
wire [3 :0] ram_arid ;
wire [31:0] ram_araddr ;
wire [7 :0] ram_arlen ;
wire [2 :0] ram_arsize ;
wire [1 :0] ram_arburst;
wire [1 :0] ram_arlock ;
wire [3 :0] ram_arcache;
wire [2 :0] ram_arprot ;
wire ram_arvalid;
wire ram_arready;
//r
wire [3 :0] ram_rid ;
wire [31:0] ram_rdata ;
wire [1 :0] ram_rresp ;
wire ram_rlast ;
wire ram_rvalid ;
wire ram_rready ;
//aw
wire [3 :0] ram_awid ;
wire [31:0] ram_awaddr ;
wire [7 :0] ram_awlen ;
wire [2 :0] ram_awsize ;
wire [1 :0] ram_awburst;
wire [1 :0] ram_awlock ;
wire [3 :0] ram_awcache;
wire [2 :0] ram_awprot ;
wire ram_awvalid;
wire ram_awready;
//w
wire [3 :0] ram_wid ;
wire [31:0] ram_wdata ;
wire [3 :0] ram_wstrb ;
wire ram_wlast ;
wire ram_wvalid ;
wire ram_wready ;
//b
wire [3 :0] ram_bid ;
wire [1 :0] ram_bresp ;
wire ram_bvalid ;
wire ram_bready ;
// inst ram axi
axi_ram ram(
.s_aclk (aclk ),
.s_aresetn (aresetn ),
//ar
.s_axi_arid (ram_arid ),
.s_axi_araddr (ram_araddr ),
.s_axi_arlen (ram_arlen ),
.s_axi_arsize (ram_arsize ),
.s_axi_arburst (ram_arburst ),
.s_axi_arvalid (ram_arvalid ),
.s_axi_arready (ram_arready ),
//r
.s_axi_rid (ram_rid ),
.s_axi_rdata (ram_rdata ),
.s_axi_rresp (ram_rresp ),
.s_axi_rlast (ram_rlast ),
.s_axi_rvalid (ram_rvalid ),
.s_axi_rready (ram_rready ),
//aw
.s_axi_awid (ram_awid ),
.s_axi_awaddr (ram_awaddr ),
.s_axi_awlen (ram_awlen ),
.s_axi_awsize (ram_awsize ),
.s_axi_awburst (ram_awburst ),
.s_axi_awvalid (ram_awvalid ),
.s_axi_awready (ram_awready ),
//w
.s_axi_wdata (ram_wdata ),
.s_axi_wstrb (ram_wstrb ),
.s_axi_wlast (ram_wlast ),
.s_axi_wvalid (ram_wvalid ),
.s_axi_wready (ram_wready ),
//b
.s_axi_bid (ram_bid ),
.s_axi_bresp (ram_bresp ),
.s_axi_bvalid (ram_bvalid ),
.s_axi_bready (ram_bready )
);
//ar
assign ram_arid = axi_arid ;
assign ram_araddr = (axi_araddr[31:28] == 4'h0 ||
axi_araddr[31:28] == 4'h1 ||
axi_araddr[31:28] == 4'h7) ? axi_araddr :
{12'b0, 4'hf, axi_araddr[31:28], axi_araddr[11:0]};
assign ram_arlen = axi_arlen ;
assign ram_arsize = axi_arsize ;
assign ram_arburst = axi_arburst;
assign ram_arlock = axi_arlock ;
assign ram_arcache = axi_arcache;
assign ram_arprot = axi_arprot ;
assign ram_arvalid = axi_arvalid_m_masked;
assign axi_arready_s_unmasked = ram_arready;
//r
assign axi_rid = axi_rvalid ? ram_rid : 4'd0 ;
assign axi_rdata = axi_rvalid ? ram_rdata : 32'd0 ;
assign axi_rresp = axi_rvalid ? ram_rresp : 2'd0 ;
assign axi_rlast = axi_rvalid ? ram_rlast : 1'd0 ;
assign axi_rvalid_s_unmasked = ram_rvalid;
assign ram_rready = axi_rready_m_masked;
//aw
assign ram_awid = axi_awid ;
assign ram_awaddr = (axi_awaddr[31:28] == 4'h0 ||
axi_awaddr[31:28] == 4'h1 ||
axi_awaddr[31:28] == 4'h7) ? axi_awaddr :
{12'b0, 4'hf, axi_awaddr[31:28], axi_awaddr[11:0]};
assign ram_awlen = axi_awlen ;
assign ram_awsize = axi_awsize ;
assign ram_awburst = axi_awburst;
assign ram_awlock = axi_awlock ;
assign ram_awcache = axi_awcache;
assign ram_awprot = axi_awprot ;
assign ram_awvalid = axi_awvalid_m_masked;
assign axi_awready_s_unmasked = ram_awready;
//w
assign ram_wid = axi_wid ;
assign ram_wdata = axi_wdata ;
assign ram_wstrb = axi_wstrb ;
assign ram_wlast = axi_wlast ;
assign ram_wvalid = axi_wvalid_m_masked;
assign axi_wready_s_unmasked = ram_wready ;
//b
assign axi_bid = axi_bvalid ? ram_bid : 4'd0 ;
assign axi_bresp = axi_bvalid ? ram_bresp : 2'd0 ;
assign axi_bvalid_s_unmasked = ram_bvalid ;
assign ram_bready = axi_bready_m_masked;
endmodule

0
lacpu/rtl/xilinx_ip/.Xil/.data_bram_bank.xcix.lock Normal file
View File

2555
lacpu/rtl/xilinx_ip/axi_crossbar_1x2/axi_crossbar_1x2.xci Normal file
View File

File diff suppressed because it is too large Load Diff

142
lacpu/rtl/xilinx_ip/data_ram/data_ram.xci → lacpu/rtl/xilinx_ip/axi_ram/axi_ram.xci
View File

@@ -6,70 +6,70 @@
<spirit:version>1.0</spirit:version> <spirit:version>1.0</spirit:version>
<spirit:componentInstances> <spirit:componentInstances>
<spirit:componentInstance> <spirit:componentInstance>
<spirit:instanceName>data_ram</spirit:instanceName> <spirit:instanceName>axi_ram</spirit:instanceName>
<spirit:componentRef spirit:vendor="xilinx.com" spirit:library="ip" spirit:name="blk_mem_gen" spirit:version="8.4"/> <spirit:componentRef spirit:vendor="xilinx.com" spirit:library="ip" spirit:name="blk_mem_gen" spirit:version="8.4"/>
<spirit:configurableElementValues> <spirit:configurableElementValues>
<spirit:configurableElementValue spirit:referenceId="ADDRBLOCK_RANGE.S_1.Mem0">4096</spirit:configurableElementValue> <spirit:configurableElementValue spirit:referenceId="ADDRBLOCK_RANGE.S_1.Mem0">4096</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXILITE_SLAVE_S_AXI.ADDR_WIDTH">1</spirit:configurableElementValue> <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXILITE_SLAVE_S_AXI.ADDR_WIDTH">32</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXILITE_SLAVE_S_AXI.ARUSER_WIDTH">0</spirit:configurableElementValue> <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXILITE_SLAVE_S_AXI.ARUSER_WIDTH">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXILITE_SLAVE_S_AXI.AWUSER_WIDTH">0</spirit:configurableElementValue> <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXILITE_SLAVE_S_AXI.AWUSER_WIDTH">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXILITE_SLAVE_S_AXI.BUSER_WIDTH">0</spirit:configurableElementValue> <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXILITE_SLAVE_S_AXI.BUSER_WIDTH">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXILITE_SLAVE_S_AXI.CLK_DOMAIN"/> <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXILITE_SLAVE_S_AXI.CLK_DOMAIN"/>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXILITE_SLAVE_S_AXI.DATA_WIDTH">1</spirit:configurableElementValue> <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXILITE_SLAVE_S_AXI.DATA_WIDTH">32</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXILITE_SLAVE_S_AXI.FREQ_HZ">100000000</spirit:configurableElementValue> <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXILITE_SLAVE_S_AXI.FREQ_HZ">100000000</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXILITE_SLAVE_S_AXI.INSERT_VIP">0</spirit:configurableElementValue> <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXILITE_SLAVE_S_AXI.INSERT_VIP">0</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXILITE_SLAVE_S_AXI.PHASE">0.000</spirit:configurableElementValue> <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXILITE_SLAVE_S_AXI.PHASE">0.000</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXILITE_SLAVE_S_AXI.PROTOCOL">AXI4LITE</spirit:configurableElementValue> <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXILITE_SLAVE_S_AXI.PROTOCOL">AXI4</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXILITE_SLAVE_S_AXI.READ_WRITE_MODE">READ_WRITE</spirit:configurableElementValue> <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXILITE_SLAVE_S_AXI.READ_WRITE_MODE">READ_WRITE</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXI_SLAVE_S_AXI.CLK_DOMAIN"/> <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXI_SLAVE_S_AXI.CLK_DOMAIN"/>
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<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXI_SLAVE_S_AXI.PHASE">0.000</spirit:configurableElementValue> <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXI_SLAVE_S_AXI.PHASE">0.000</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXI_SLAVE_S_AXI.PROTOCOL">AXI4LITE</spirit:configurableElementValue> <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXI_SLAVE_S_AXI.PROTOCOL">AXI4</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXI_SLAVE_S_AXI.READ_WRITE_MODE">READ_WRITE</spirit:configurableElementValue> <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXI_SLAVE_S_AXI.READ_WRITE_MODE">READ_WRITE</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXI_SLAVE_S_AXI.RUSER_BITS_PER_BYTE">0</spirit:configurableElementValue> <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXI_SLAVE_S_AXI.RUSER_BITS_PER_BYTE">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXI_SLAVE_S_AXI.RUSER_WIDTH">0</spirit:configurableElementValue> <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXI_SLAVE_S_AXI.RUSER_WIDTH">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXI_SLAVE_S_AXI.SUPPORTS_NARROW_BURST">0</spirit:configurableElementValue> <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXI_SLAVE_S_AXI.SUPPORTS_NARROW_BURST">1</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXI_SLAVE_S_AXI.WUSER_BITS_PER_BYTE">0</spirit:configurableElementValue> <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXI_SLAVE_S_AXI.WUSER_BITS_PER_BYTE">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXI_SLAVE_S_AXI.WUSER_WIDTH">0</spirit:configurableElementValue> <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.AXI_SLAVE_S_AXI.WUSER_WIDTH">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.BRAM_PORTA.MASTER_TYPE">OTHER</spirit:configurableElementValue> <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.BRAM_PORTA.MASTER_TYPE">OTHER</spirit:configurableElementValue>
@@ -89,16 +89,16 @@
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.CLK.ACLK.INSERT_VIP">0</spirit:configurableElementValue> <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.CLK.ACLK.INSERT_VIP">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.CLK.ACLK.PHASE">0.000</spirit:configurableElementValue> <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.CLK.ACLK.PHASE">0.000</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.RST.ARESETN.INSERT_VIP">0</spirit:configurableElementValue> <spirit:configurableElementValue spirit:referenceId="BUSIFPARAM_VALUE.RST.ARESETN.INSERT_VIP">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_ADDRA_WIDTH">16</spirit:configurableElementValue> <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_ADDRA_WIDTH">18</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_ADDRB_WIDTH">16</spirit:configurableElementValue> <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_ADDRB_WIDTH">18</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_ALGORITHM">1</spirit:configurableElementValue> <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_ALGORITHM">1</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_AXI_ID_WIDTH">4</spirit:configurableElementValue> <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_AXI_ID_WIDTH">4</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_AXI_SLAVE_TYPE">0</spirit:configurableElementValue> <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_AXI_SLAVE_TYPE">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_AXI_TYPE">1</spirit:configurableElementValue> <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_AXI_TYPE">1</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_BYTE_SIZE">8</spirit:configurableElementValue> <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_BYTE_SIZE">8</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_COMMON_CLK">0</spirit:configurableElementValue> <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_COMMON_CLK">1</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_COUNT_18K_BRAM">0</spirit:configurableElementValue> <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_COUNT_18K_BRAM">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_COUNT_36K_BRAM">64</spirit:configurableElementValue> <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_COUNT_36K_BRAM">256</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CTRL_ECC_ALGO">NONE</spirit:configurableElementValue> <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CTRL_ECC_ALGO">NONE</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_DEFAULT_DATA">0</spirit:configurableElementValue> <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_DEFAULT_DATA">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_DISABLE_WARN_BHV_COLL">0</spirit:configurableElementValue> <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_DISABLE_WARN_BHV_COLL">0</spirit:configurableElementValue>
@@ -112,11 +112,11 @@
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_EN_SAFETY_CKT">0</spirit:configurableElementValue> <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_EN_SAFETY_CKT">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_EN_SHUTDOWN_PIN">0</spirit:configurableElementValue> <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_EN_SHUTDOWN_PIN">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_EN_SLEEP_PIN">0</spirit:configurableElementValue> <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_EN_SLEEP_PIN">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_EST_POWER_SUMMARY">Estimated Power for IP : 10.194002 mW</spirit:configurableElementValue> <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_EST_POWER_SUMMARY">Estimated Power for IP : 21.018106 mW</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_FAMILY">artix7</spirit:configurableElementValue> <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_FAMILY">artix7</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_AXI_ID">0</spirit:configurableElementValue> <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_AXI_ID">1</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_ENA">1</spirit:configurableElementValue> <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_ENA">1</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_ENB">0</spirit:configurableElementValue> <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_ENB">1</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_INJECTERR">0</spirit:configurableElementValue> <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_INJECTERR">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_MEM_OUTPUT_REGS_A">0</spirit:configurableElementValue> <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_MEM_OUTPUT_REGS_A">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_MEM_OUTPUT_REGS_B">0</spirit:configurableElementValue> <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_MEM_OUTPUT_REGS_B">0</spirit:configurableElementValue>
@@ -125,20 +125,20 @@
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_REGCEA">0</spirit:configurableElementValue> <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_REGCEA">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_REGCEB">0</spirit:configurableElementValue> <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_REGCEB">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_RSTA">0</spirit:configurableElementValue> <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_RSTA">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_RSTB">0</spirit:configurableElementValue> <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_RSTB">1</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_SOFTECC_INPUT_REGS_A">0</spirit:configurableElementValue> <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_SOFTECC_INPUT_REGS_A">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_SOFTECC_OUTPUT_REGS_B">0</spirit:configurableElementValue> <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_SOFTECC_OUTPUT_REGS_B">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_INITA_VAL">0</spirit:configurableElementValue> <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_INITA_VAL">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_INITB_VAL">0</spirit:configurableElementValue> <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_INITB_VAL">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_INIT_FILE">data_ram.mem</spirit:configurableElementValue> <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_INIT_FILE">axi_ram.mem</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_INIT_FILE_NAME">no_coe_file_loaded</spirit:configurableElementValue> <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_INIT_FILE_NAME">no_coe_file_loaded</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_INTERFACE_TYPE">0</spirit:configurableElementValue> <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_INTERFACE_TYPE">1</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_LOAD_INIT_FILE">0</spirit:configurableElementValue> <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_LOAD_INIT_FILE">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MEM_TYPE">0</spirit:configurableElementValue> <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MEM_TYPE">1</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MUX_PIPELINE_STAGES">0</spirit:configurableElementValue> <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MUX_PIPELINE_STAGES">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PRIM_TYPE">1</spirit:configurableElementValue> <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PRIM_TYPE">1</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_READ_DEPTH_A">65536</spirit:configurableElementValue> <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_READ_DEPTH_A">262144</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_READ_DEPTH_B">65536</spirit:configurableElementValue> <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_READ_DEPTH_B">262144</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_READ_LATENCY_A">1</spirit:configurableElementValue> <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_READ_LATENCY_A">1</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_READ_LATENCY_B">1</spirit:configurableElementValue> <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_READ_LATENCY_B">1</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_READ_WIDTH_A">32</spirit:configurableElementValue> <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_READ_WIDTH_A">32</spirit:configurableElementValue>
@@ -157,10 +157,10 @@
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_URAM">0</spirit:configurableElementValue> <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_URAM">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WEA_WIDTH">4</spirit:configurableElementValue> <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WEA_WIDTH">4</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WEB_WIDTH">4</spirit:configurableElementValue> <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WEB_WIDTH">4</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WRITE_DEPTH_A">65536</spirit:configurableElementValue> <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WRITE_DEPTH_A">262144</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WRITE_DEPTH_B">65536</spirit:configurableElementValue> <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WRITE_DEPTH_B">262144</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WRITE_MODE_A">WRITE_FIRST</spirit:configurableElementValue> <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WRITE_MODE_A">READ_FIRST</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WRITE_MODE_B">WRITE_FIRST</spirit:configurableElementValue> <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WRITE_MODE_B">READ_FIRST</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WRITE_WIDTH_A">32</spirit:configurableElementValue> <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WRITE_WIDTH_A">32</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WRITE_WIDTH_B">32</spirit:configurableElementValue> <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WRITE_WIDTH_B">32</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_XDEVICEFAMILY">artix7</spirit:configurableElementValue> <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_XDEVICEFAMILY">artix7</spirit:configurableElementValue>
@@ -169,12 +169,12 @@
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.AXI_Type">AXI4_Full</spirit:configurableElementValue> <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.AXI_Type">AXI4_Full</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Additional_Inputs_for_Power_Estimation">false</spirit:configurableElementValue> <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Additional_Inputs_for_Power_Estimation">false</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Algorithm">Minimum_Area</spirit:configurableElementValue> <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Algorithm">Minimum_Area</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Assume_Synchronous_Clk">false</spirit:configurableElementValue> <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Assume_Synchronous_Clk">true</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Byte_Size">8</spirit:configurableElementValue> <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Byte_Size">8</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CTRL_ECC_ALGO">NONE</spirit:configurableElementValue> <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CTRL_ECC_ALGO">NONE</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Coe_File">no_coe_file_loaded</spirit:configurableElementValue> <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Coe_File">no_coe_file_loaded</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Collision_Warnings">ALL</spirit:configurableElementValue> <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Collision_Warnings">ALL</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Component_Name">data_ram</spirit:configurableElementValue> <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Component_Name">axi_ram</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Disable_Collision_Warnings">false</spirit:configurableElementValue> <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Disable_Collision_Warnings">false</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Disable_Out_of_Range_Warnings">false</spirit:configurableElementValue> <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Disable_Out_of_Range_Warnings">false</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.ECC">false</spirit:configurableElementValue> <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.ECC">false</spirit:configurableElementValue>
@@ -185,15 +185,15 @@
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.EN_SLEEP_PIN">false</spirit:configurableElementValue> <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.EN_SLEEP_PIN">false</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Enable_32bit_Address">false</spirit:configurableElementValue> <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Enable_32bit_Address">false</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Enable_A">Use_ENA_Pin</spirit:configurableElementValue> <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Enable_A">Use_ENA_Pin</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Enable_B">Always_Enabled</spirit:configurableElementValue> <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Enable_B">Use_ENB_Pin</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Error_Injection_Type">Single_Bit_Error_Injection</spirit:configurableElementValue> <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Error_Injection_Type">Single_Bit_Error_Injection</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Fill_Remaining_Memory_Locations">false</spirit:configurableElementValue> <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Fill_Remaining_Memory_Locations">false</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Interface_Type">Native</spirit:configurableElementValue> <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Interface_Type">AXI4</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Load_Init_File">false</spirit:configurableElementValue> <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Load_Init_File">false</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MEM_FILE">no_mem_loaded</spirit:configurableElementValue> <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MEM_FILE">no_mem_loaded</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Memory_Type">Single_Port_RAM</spirit:configurableElementValue> <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Memory_Type">Simple_Dual_Port_RAM</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Operating_Mode_A">WRITE_FIRST</spirit:configurableElementValue> <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Operating_Mode_A">READ_FIRST</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Operating_Mode_B">WRITE_FIRST</spirit:configurableElementValue> <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Operating_Mode_B">READ_FIRST</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Output_Reset_Value_A">0</spirit:configurableElementValue> <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Output_Reset_Value_A">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Output_Reset_Value_B">0</spirit:configurableElementValue> <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Output_Reset_Value_B">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PRIM_type_to_Implement">BRAM</spirit:configurableElementValue> <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PRIM_type_to_Implement">BRAM</spirit:configurableElementValue>
@@ -201,8 +201,8 @@
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Port_A_Clock">100</spirit:configurableElementValue> <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Port_A_Clock">100</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Port_A_Enable_Rate">100</spirit:configurableElementValue> <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Port_A_Enable_Rate">100</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Port_A_Write_Rate">50</spirit:configurableElementValue> <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Port_A_Write_Rate">50</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Port_B_Clock">0</spirit:configurableElementValue> <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Port_B_Clock">100</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Port_B_Enable_Rate">0</spirit:configurableElementValue> <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Port_B_Enable_Rate">100</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Port_B_Write_Rate">0</spirit:configurableElementValue> <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Port_B_Write_Rate">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Primitive">8kx2</spirit:configurableElementValue> <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Primitive">8kx2</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.RD_ADDR_CHNG_A">false</spirit:configurableElementValue> <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.RD_ADDR_CHNG_A">false</spirit:configurableElementValue>
@@ -220,15 +220,15 @@
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Reset_Memory_Latch_B">false</spirit:configurableElementValue> <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Reset_Memory_Latch_B">false</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Reset_Priority_A">CE</spirit:configurableElementValue> <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Reset_Priority_A">CE</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Reset_Priority_B">CE</spirit:configurableElementValue> <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Reset_Priority_B">CE</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Reset_Type">SYNC</spirit:configurableElementValue> <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Reset_Type">ASYNC</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Use_AXI_ID">false</spirit:configurableElementValue> <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Use_AXI_ID">true</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Use_Byte_Write_Enable">true</spirit:configurableElementValue> <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Use_Byte_Write_Enable">true</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Use_Error_Injection_Pins">false</spirit:configurableElementValue> <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Use_Error_Injection_Pins">false</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Use_REGCEA_Pin">false</spirit:configurableElementValue> <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Use_REGCEA_Pin">false</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Use_REGCEB_Pin">false</spirit:configurableElementValue> <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Use_REGCEB_Pin">false</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Use_RSTA_Pin">false</spirit:configurableElementValue> <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Use_RSTA_Pin">false</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Use_RSTB_Pin">false</spirit:configurableElementValue> <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Use_RSTB_Pin">true</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Write_Depth_A">65536</spirit:configurableElementValue> <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Write_Depth_A">262144</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Write_Width_A">32</spirit:configurableElementValue> <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Write_Width_A">32</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Write_Width_B">32</spirit:configurableElementValue> <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Write_Width_B">32</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.ecctype">No_ECC</spirit:configurableElementValue> <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.ecctype">No_ECC</spirit:configurableElementValue>
@@ -239,8 +239,8 @@
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.ARCHITECTURE">artix7</spirit:configurableElementValue> <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.ARCHITECTURE">artix7</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.BASE_BOARD_PART"/> <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.BASE_BOARD_PART"/>
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.BOARD_CONNECTIONS"/> <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.BOARD_CONNECTIONS"/>
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.DEVICE">xc7a100t</spirit:configurableElementValue> <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.DEVICE">xc7a200t</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.PACKAGE">csg324</spirit:configurableElementValue> <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.PACKAGE">fbg676</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.PREFHDL">VERILOG</spirit:configurableElementValue> <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.PREFHDL">VERILOG</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.SILICON_REVISION"/> <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.SILICON_REVISION"/>
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.SIMULATOR_LANGUAGE">MIXED</spirit:configurableElementValue> <spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.SIMULATOR_LANGUAGE">MIXED</spirit:configurableElementValue>
@@ -261,47 +261,47 @@
<spirit:vendorExtensions> <spirit:vendorExtensions>
<xilinx:componentInstanceExtensions> <xilinx:componentInstanceExtensions>
<xilinx:configElementInfos> <xilinx:configElementInfos>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AXILITE_SLAVE_S_AXI.ADDR_WIDTH" xilinx:valueSource="auto"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AXILITE_SLAVE_S_AXI.ARUSER_WIDTH" xilinx:valueSource="constant"/> <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AXILITE_SLAVE_S_AXI.ARUSER_WIDTH" xilinx:valueSource="constant"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AXILITE_SLAVE_S_AXI.AWUSER_WIDTH" xilinx:valueSource="constant"/> <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AXILITE_SLAVE_S_AXI.AWUSER_WIDTH" xilinx:valueSource="constant"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AXILITE_SLAVE_S_AXI.BUSER_WIDTH" xilinx:valueSource="constant"/> <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AXILITE_SLAVE_S_AXI.BUSER_WIDTH" xilinx:valueSource="constant"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AXILITE_SLAVE_S_AXI.DATA_WIDTH" xilinx:valueSource="auto"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AXILITE_SLAVE_S_AXI.HAS_BRESP" xilinx:valueSource="auto"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AXILITE_SLAVE_S_AXI.HAS_BURST" xilinx:valueSource="auto"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AXILITE_SLAVE_S_AXI.HAS_CACHE" xilinx:valueSource="constant"/> <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AXILITE_SLAVE_S_AXI.HAS_CACHE" xilinx:valueSource="constant"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AXILITE_SLAVE_S_AXI.HAS_LOCK" xilinx:valueSource="constant"/> <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AXILITE_SLAVE_S_AXI.HAS_LOCK" xilinx:valueSource="constant"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AXILITE_SLAVE_S_AXI.HAS_PROT" xilinx:valueSource="constant"/> <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AXILITE_SLAVE_S_AXI.HAS_PROT" xilinx:valueSource="constant"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AXILITE_SLAVE_S_AXI.HAS_QOS" xilinx:valueSource="constant"/> <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AXILITE_SLAVE_S_AXI.HAS_QOS" xilinx:valueSource="constant"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AXILITE_SLAVE_S_AXI.HAS_REGION" xilinx:valueSource="constant"/> <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AXILITE_SLAVE_S_AXI.HAS_REGION" xilinx:valueSource="constant"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AXILITE_SLAVE_S_AXI.HAS_RRESP" xilinx:valueSource="auto"/> <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AXILITE_SLAVE_S_AXI.ID_WIDTH" xilinx:valueSource="auto"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AXILITE_SLAVE_S_AXI.HAS_WSTRB" xilinx:valueSource="auto"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AXILITE_SLAVE_S_AXI.PROTOCOL" xilinx:valueSource="auto"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AXILITE_SLAVE_S_AXI.RUSER_WIDTH" xilinx:valueSource="constant"/> <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AXILITE_SLAVE_S_AXI.RUSER_WIDTH" xilinx:valueSource="constant"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AXILITE_SLAVE_S_AXI.WUSER_WIDTH" xilinx:valueSource="constant"/> <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AXILITE_SLAVE_S_AXI.WUSER_WIDTH" xilinx:valueSource="constant"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AXI_SLAVE_S_AXI.ADDR_WIDTH" xilinx:valueSource="auto"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AXI_SLAVE_S_AXI.ARUSER_WIDTH" xilinx:valueSource="constant"/> <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AXI_SLAVE_S_AXI.ARUSER_WIDTH" xilinx:valueSource="constant"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AXI_SLAVE_S_AXI.AWUSER_WIDTH" xilinx:valueSource="constant"/> <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AXI_SLAVE_S_AXI.AWUSER_WIDTH" xilinx:valueSource="constant"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AXI_SLAVE_S_AXI.BUSER_WIDTH" xilinx:valueSource="constant"/> <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AXI_SLAVE_S_AXI.BUSER_WIDTH" xilinx:valueSource="constant"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AXI_SLAVE_S_AXI.DATA_WIDTH" xilinx:valueSource="auto"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AXI_SLAVE_S_AXI.HAS_BRESP" xilinx:valueSource="auto"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AXI_SLAVE_S_AXI.HAS_BURST" xilinx:valueSource="auto"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AXI_SLAVE_S_AXI.HAS_CACHE" xilinx:valueSource="constant"/> <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AXI_SLAVE_S_AXI.HAS_CACHE" xilinx:valueSource="constant"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AXI_SLAVE_S_AXI.HAS_LOCK" xilinx:valueSource="constant"/> <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AXI_SLAVE_S_AXI.HAS_LOCK" xilinx:valueSource="constant"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AXI_SLAVE_S_AXI.HAS_PROT" xilinx:valueSource="constant"/> <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AXI_SLAVE_S_AXI.HAS_PROT" xilinx:valueSource="constant"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AXI_SLAVE_S_AXI.HAS_QOS" xilinx:valueSource="constant"/> <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AXI_SLAVE_S_AXI.HAS_QOS" xilinx:valueSource="constant"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AXI_SLAVE_S_AXI.HAS_REGION" xilinx:valueSource="constant"/> <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AXI_SLAVE_S_AXI.HAS_REGION" xilinx:valueSource="constant"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AXI_SLAVE_S_AXI.HAS_RRESP" xilinx:valueSource="auto"/> <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AXI_SLAVE_S_AXI.ID_WIDTH" xilinx:valueSource="auto"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AXI_SLAVE_S_AXI.HAS_WSTRB" xilinx:valueSource="auto"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AXI_SLAVE_S_AXI.PROTOCOL" xilinx:valueSource="auto"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AXI_SLAVE_S_AXI.RUSER_WIDTH" xilinx:valueSource="constant"/> <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AXI_SLAVE_S_AXI.RUSER_WIDTH" xilinx:valueSource="constant"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AXI_SLAVE_S_AXI.WUSER_WIDTH" xilinx:valueSource="constant"/> <xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AXI_SLAVE_S_AXI.WUSER_WIDTH" xilinx:valueSource="constant"/>
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Assume_Synchronous_Clk" xilinx:valueSource="user"/>
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Byte_Size" xilinx:valueSource="user"/> <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Byte_Size" xilinx:valueSource="user"/>
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Coe_File" xilinx:valueSource="user"/> <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Coe_File" xilinx:valueSource="user"/>
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Enable_B" xilinx:valueSource="user"/>
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Fill_Remaining_Memory_Locations" xilinx:valueSource="user"/>
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Interface_Type" xilinx:valueSource="user"/>
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Load_Init_File" xilinx:valueSource="user"/> <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Load_Init_File" xilinx:valueSource="user"/>
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Memory_Type" xilinx:valueSource="user"/>
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Operating_Mode_A" xilinx:valueSource="user"/>
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Operating_Mode_B" xilinx:valueSource="user"/>
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Port_B_Clock" xilinx:valueSource="user"/>
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Port_B_Enable_Rate" xilinx:valueSource="user"/>
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Read_Width_A" xilinx:valueSource="user"/> <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Read_Width_A" xilinx:valueSource="user"/>
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Read_Width_B" xilinx:valueSource="user"/> <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Read_Width_B" xilinx:valueSource="user"/>
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Register_PortA_Output_of_Memory_Primitives" xilinx:valueSource="user"/> <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Register_PortA_Output_of_Memory_Primitives" xilinx:valueSource="user"/>
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Reset_Type" xilinx:valueSource="user"/>
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Use_AXI_ID" xilinx:valueSource="user"/>
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Use_Byte_Write_Enable" xilinx:valueSource="user"/> <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Use_Byte_Write_Enable" xilinx:valueSource="user"/>
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Use_RSTB_Pin" xilinx:valueSource="user"/>
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Write_Depth_A" xilinx:valueSource="user"/> <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Write_Depth_A" xilinx:valueSource="user"/>
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Write_Width_A" xilinx:valueSource="user"/> <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Write_Width_A" xilinx:valueSource="user"/>
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Write_Width_B" xilinx:valueSource="user"/> <xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Write_Width_B" xilinx:valueSource="user"/>

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lacpu/rtl/xilinx_ip/clk_pll/clk_pll.xci Normal file
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<?xml version="1.0" encoding="UTF-8"?>
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<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT1_PHASE">0.000</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT1_REQUESTED_DUTY_CYCLE">50.000</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT1_REQUESTED_OUT_FREQ">45.000</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT1_REQUESTED_PHASE">0.000</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT1_SEQUENCE_NUMBER">1</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT2_1">0000</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT2_2">0000</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT2_ACTUAL_FREQ">100.000</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT2_DRIVES">BUFG</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT2_DUTY_CYCLE">50.0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT2_MATCHED_ROUTING">false</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT2_OUT_FREQ">90.00000</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT2_PHASE">0.000</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT2_REQUESTED_DUTY_CYCLE">50.000</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT2_REQUESTED_OUT_FREQ">90.000</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT2_REQUESTED_PHASE">0.000</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT2_SEQUENCE_NUMBER">1</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT2_USED">1</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT3_1">0000</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT3_2">0000</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT3_ACTUAL_FREQ">100.000</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT3_DRIVES">BUFG</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT3_DUTY_CYCLE">50.000</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT3_MATCHED_ROUTING">false</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT3_OUT_FREQ">100.000</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT3_PHASE">0.000</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT3_REQUESTED_DUTY_CYCLE">50.000</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT3_REQUESTED_OUT_FREQ">100.000</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT3_REQUESTED_PHASE">0.000</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT3_SEQUENCE_NUMBER">1</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT3_USED">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT4_1">0000</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT4_2">0000</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT4_ACTUAL_FREQ">100.000</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT4_DRIVES">BUFG</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT4_DUTY_CYCLE">50.000</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT4_MATCHED_ROUTING">false</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT4_OUT_FREQ">100.000</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT4_PHASE">0.000</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT4_REQUESTED_DUTY_CYCLE">50.000</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT4_REQUESTED_OUT_FREQ">100.000</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT4_REQUESTED_PHASE">0.000</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT4_SEQUENCE_NUMBER">1</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT4_USED">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT5_1">0000</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT5_2">0000</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT5_ACTUAL_FREQ">100.000</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT5_DRIVES">BUFG</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT5_DUTY_CYCLE">50.000</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT5_MATCHED_ROUTING">false</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT5_OUT_FREQ">100.000</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT5_PHASE">0.000</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT5_REQUESTED_DUTY_CYCLE">50.000</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT5_REQUESTED_OUT_FREQ">100.000</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT5_REQUESTED_PHASE">0.000</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT5_SEQUENCE_NUMBER">1</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT5_USED">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT6_1">0000</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT6_2">0000</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT6_ACTUAL_FREQ">100.000</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT6_DRIVES">BUFG</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT6_DUTY_CYCLE">50.000</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT6_MATCHED_ROUTING">false</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT6_OUT_FREQ">100.000</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT6_PHASE">0.000</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT6_REQUESTED_DUTY_CYCLE">50.000</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT6_REQUESTED_OUT_FREQ">100.000</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT6_REQUESTED_PHASE">0.000</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT6_SEQUENCE_NUMBER">1</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT6_USED">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT7_DRIVES">BUFG</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT7_DUTY_CYCLE">50.000</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT7_MATCHED_ROUTING">false</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT7_OUT_FREQ">100.000</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT7_PHASE">0.000</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT7_REQUESTED_DUTY_CYCLE">50.000</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT7_REQUESTED_OUT_FREQ">100.000</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT7_REQUESTED_PHASE">0.000</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT7_SEQUENCE_NUMBER">1</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT7_USED">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUTPHY_MODE">VCO</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLK_IN_SEL_PORT">clk_in_sel</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLK_OUT1_PORT">cpu_clk</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLK_OUT2_PORT">timer_clk</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLK_OUT3_PORT">clk_out3</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLK_OUT4_PORT">clk_out4</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLK_OUT5_PORT">clk_out5</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLK_OUT6_PORT">clk_out6</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLK_OUT7_PORT">clk_out7</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLK_VALID_PORT">CLK_VALID</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLOCK_MGR_TYPE">NA</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_DADDR_PORT">daddr</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_DCLK_PORT">dclk</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_DEN_PORT">den</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_DIN_PORT">din</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_DIVCLK">0000</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_DIVIDE1_AUTO">1</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_DIVIDE2_AUTO">0.5</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_DIVIDE3_AUTO">0.45</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_DIVIDE4_AUTO">0.45</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_DIVIDE5_AUTO">0.45</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_DIVIDE6_AUTO">0.45</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_DIVIDE7_AUTO">0.45</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_DOUT_PORT">dout</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_DRDY_PORT">drdy</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_DWE_PORT">dwe</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_D_MAX">42.000</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_D_MIN">1.000</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_ENABLE_CLKOUTPHY">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_ENABLE_CLOCK_MONITOR">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_ENABLE_USER_CLOCK0">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_ENABLE_USER_CLOCK1">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_ENABLE_USER_CLOCK2">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_ENABLE_USER_CLOCK3">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_Enable_PLL0">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_Enable_PLL1">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_FEEDBACK_SOURCE">FDBK_AUTO</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_FILTER_1">0000</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_FILTER_2">0000</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_HAS_CDDC">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_INCLK_SUM_ROW0">Input Clock Freq (MHz) Input Jitter (UI)</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_INCLK_SUM_ROW1">__primary_________100.000____________0.010</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_INCLK_SUM_ROW2">no_secondary_input_clock </spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_INPUT_CLK_STOPPED_PORT">input_clk_stopped</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_INTERFACE_SELECTION">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_IN_FREQ_UNITS">Units_MHz</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_JITTER_SEL">No_Jitter</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_LOCKED_PORT">locked</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_LOCK_1">0000</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_LOCK_2">0000</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_LOCK_3">0000</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCMBUFGCEDIV">false</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCMBUFGCEDIV1">false</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCMBUFGCEDIV2">false</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCMBUFGCEDIV3">false</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCMBUFGCEDIV4">false</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCMBUFGCEDIV5">false</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCMBUFGCEDIV6">false</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCMBUFGCEDIV7">false</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_BANDWIDTH">OPTIMIZED</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_CLKFBOUT_MULT_F">9.000</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_CLKFBOUT_PHASE">0.000</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_CLKFBOUT_USE_FINE_PS">FALSE</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_CLKIN1_PERIOD">10.000</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_CLKIN2_PERIOD">10.000</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_CLKOUT0_DIVIDE_F">20.000</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_CLKOUT0_DUTY_CYCLE">0.500</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_CLKOUT0_PHASE">0.000</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_CLKOUT0_USE_FINE_PS">FALSE</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_CLKOUT1_DIVIDE">10</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_CLKOUT1_DUTY_CYCLE">0.500</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_CLKOUT1_PHASE">0.000</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_CLKOUT1_USE_FINE_PS">FALSE</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_CLKOUT2_DIVIDE">1</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_CLKOUT2_DUTY_CYCLE">0.500</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_CLKOUT2_PHASE">0.000</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_CLKOUT2_USE_FINE_PS">FALSE</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_CLKOUT3_DIVIDE">1</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_CLKOUT3_DUTY_CYCLE">0.500</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_CLKOUT3_PHASE">0.000</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_CLKOUT3_USE_FINE_PS">FALSE</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_CLKOUT4_CASCADE">FALSE</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_CLKOUT4_DIVIDE">1</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_CLKOUT4_DUTY_CYCLE">0.500</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_CLKOUT4_PHASE">0.000</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_CLKOUT4_USE_FINE_PS">FALSE</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_CLKOUT5_DIVIDE">1</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_CLKOUT5_DUTY_CYCLE">0.500</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_CLKOUT5_PHASE">0.000</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_CLKOUT5_USE_FINE_PS">FALSE</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_CLKOUT6_DIVIDE">1</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_CLKOUT6_DUTY_CYCLE">0.500</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_CLKOUT6_PHASE">0.000</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_CLKOUT6_USE_FINE_PS">FALSE</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_CLOCK_HOLD">FALSE</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_COMPENSATION">ZHOLD</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_DIVCLK_DIVIDE">1</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_NOTES">None</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_REF_JITTER1">0.010</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_REF_JITTER2">0.010</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_STARTUP_WAIT">FALSE</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_M_MAX">64.000</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_M_MIN">2.000</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_NUM_OUT_CLKS">2</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_OUTCLK_SUM_ROW0A"> Output Output Phase Duty Cycle Pk-to-Pk Phase</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_OUTCLK_SUM_ROW0B"> Clock Freq (MHz) (degrees) (%) Jitter (ps) Error (ps)</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_OUTCLK_SUM_ROW1">_cpu_clk__45.00000______0.000______50.0______163.238____105.461</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_OUTCLK_SUM_ROW2">timer_clk__90.00000______0.000______50.0______140.709____105.461</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_OUTCLK_SUM_ROW3">no_CLK_OUT3_output</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_OUTCLK_SUM_ROW4">no_CLK_OUT4_output</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_OUTCLK_SUM_ROW5">no_CLK_OUT5_output</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_OUTCLK_SUM_ROW6">no_CLK_OUT6_output</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_OUTCLK_SUM_ROW7">no_CLK_OUT7_output</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_OVERRIDE_MMCM">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_OVERRIDE_PLL">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_O_MAX">128.000</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_O_MIN">1.000</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PHASESHIFT_MODE">WAVEFORM</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PLATFORM">UNKNOWN</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PLLBUFGCEDIV">false</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PLLBUFGCEDIV1">false</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PLLBUFGCEDIV2">false</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PLLBUFGCEDIV3">false</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PLLBUFGCEDIV4">false</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PLL_BANDWIDTH">OPTIMIZED</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PLL_CLKFBOUT_MULT">1</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PLL_CLKFBOUT_PHASE">0.000</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PLL_CLKIN_PERIOD">1.000</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PLL_CLKOUT0_DIVIDE">1</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PLL_CLKOUT0_DUTY_CYCLE">0.500</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PLL_CLKOUT0_PHASE">0.000</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PLL_CLKOUT1_DIVIDE">1</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PLL_CLKOUT1_DUTY_CYCLE">0.500</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PLL_CLKOUT1_PHASE">0.000</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PLL_CLKOUT2_DIVIDE">1</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PLL_CLKOUT2_DUTY_CYCLE">0.500</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PLL_CLKOUT2_PHASE">0.000</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PLL_CLKOUT3_DIVIDE">1</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PLL_CLKOUT3_DUTY_CYCLE">0.500</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PLL_CLKOUT3_PHASE">0.000</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PLL_CLKOUT4_DIVIDE">1</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PLL_CLKOUT4_DUTY_CYCLE">0.500</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PLL_CLKOUT4_PHASE">0.000</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PLL_CLKOUT5_DIVIDE">1</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PLL_CLKOUT5_DUTY_CYCLE">0.500</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PLL_CLKOUT5_PHASE">0.000</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PLL_CLK_FEEDBACK">CLKFBOUT</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PLL_COMPENSATION">SYSTEM_SYNCHRONOUS</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PLL_DIVCLK_DIVIDE">1</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PLL_NOTES">No notes</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PLL_REF_JITTER">0.010</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_POWER_DOWN_PORT">power_down</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_POWER_REG">0000</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PRECISION">1</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PRIMARY_PORT">clk_in1</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PRIMITIVE">PLL</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PRIMTYPE_SEL">AUTO</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PRIM_IN_FREQ">100.000</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PRIM_IN_JITTER">0.010</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PRIM_IN_TIMEPERIOD">10.000</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PRIM_SOURCE">Single_ended_clock_capable_pin</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PSCLK_PORT">psclk</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PSDONE_PORT">psdone</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PSEN_PORT">psen</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_PSINCDEC_PORT">psincdec</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_REF_CLK_FREQ">100.0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_RESET_LOW">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_RESET_PORT">reset</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_SECONDARY_IN_FREQ">100.000</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_SECONDARY_IN_JITTER">0.010</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_SECONDARY_IN_TIMEPERIOD">10.000</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_SECONDARY_PORT">clk_in2</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_SECONDARY_SOURCE">Single_ended_clock_capable_pin</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_SS_MODE">CENTER_HIGH</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_SS_MOD_PERIOD">4000</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_SS_MOD_TIME">0.004</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_STATUS_PORT">STATUS</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_S_AXI_ADDR_WIDTH">11</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_S_AXI_DATA_WIDTH">32</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USER_CLK_FREQ0">100.0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USER_CLK_FREQ1">100.0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USER_CLK_FREQ2">100.0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USER_CLK_FREQ3">100.0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_CLKFB_STOPPED">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_CLKOUT1_BAR">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_CLKOUT2_BAR">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_CLKOUT3_BAR">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_CLKOUT4_BAR">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_CLK_VALID">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_CLOCK_SEQUENCING">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_DYN_PHASE_SHIFT">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_DYN_RECONFIG">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_FAST_SIMULATION">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_FREEZE">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_FREQ_SYNTH">1</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_INCLK_STOPPED">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_INCLK_SWITCHOVER">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_LOCKED">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_MAX_I_JITTER">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_MIN_O_JITTER">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_MIN_POWER">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_PHASE_ALIGNMENT">1</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_POWER_DOWN">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_RESET">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_SAFE_CLOCK_STARTUP">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_SPREAD_SPECTRUM">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_STATUS">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_VCO_MAX">1600.000</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_VCO_MIN">800.000</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.c_component_name">clk_pll</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.AUTO_PRIMITIVE">MMCM</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.AXI_DRP">false</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CALC_DONE">empty</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CDDCDONE_PORT">cddcdone</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CDDCREQ_PORT">cddcreq</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKFB_IN_N_PORT">clkfb_in_n</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKFB_IN_PORT">clkfb_in</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKFB_IN_P_PORT">clkfb_in_p</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKFB_IN_SIGNALING">SINGLE</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKFB_OUT_N_PORT">clkfb_out_n</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKFB_OUT_PORT">clkfb_out</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKFB_OUT_P_PORT">clkfb_out_p</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKFB_STOPPED_PORT">clkfb_stopped</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKIN1_JITTER_PS">100.0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKIN1_UI_JITTER">0.010</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKIN2_JITTER_PS">100.0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKIN2_UI_JITTER">0.010</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT1_DRIVES">BUFG</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT1_JITTER">163.238</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT1_MATCHED_ROUTING">false</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT1_PHASE_ERROR">105.461</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT1_REQUESTED_DUTY_CYCLE">50.000</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT1_REQUESTED_OUT_FREQ">45.000</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT1_REQUESTED_PHASE">0.000</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT1_SEQUENCE_NUMBER">1</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT1_USED">true</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT2_DRIVES">BUFG</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT2_JITTER">140.709</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT2_MATCHED_ROUTING">false</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT2_PHASE_ERROR">105.461</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT2_REQUESTED_DUTY_CYCLE">50.000</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT2_REQUESTED_OUT_FREQ">90.000</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT2_REQUESTED_PHASE">0.000</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT2_SEQUENCE_NUMBER">1</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT2_USED">true</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT3_DRIVES">BUFG</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT3_JITTER">0.0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT3_MATCHED_ROUTING">false</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT3_PHASE_ERROR">0.0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT3_REQUESTED_DUTY_CYCLE">50.000</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT3_REQUESTED_OUT_FREQ">100.000</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT3_REQUESTED_PHASE">0.000</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT3_SEQUENCE_NUMBER">1</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT3_USED">false</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT4_DRIVES">BUFG</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT4_JITTER">0.0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT4_MATCHED_ROUTING">false</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT4_PHASE_ERROR">0.0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT4_REQUESTED_DUTY_CYCLE">50.000</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT4_REQUESTED_OUT_FREQ">100.000</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT4_REQUESTED_PHASE">0.000</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT4_SEQUENCE_NUMBER">1</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT4_USED">false</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT5_DRIVES">BUFG</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT5_JITTER">0.0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT5_MATCHED_ROUTING">false</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT5_PHASE_ERROR">0.0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT5_REQUESTED_DUTY_CYCLE">50.000</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT5_REQUESTED_OUT_FREQ">100.000</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT5_REQUESTED_PHASE">0.000</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT5_SEQUENCE_NUMBER">1</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT5_USED">false</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT6_DRIVES">BUFG</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT6_JITTER">0.0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT6_MATCHED_ROUTING">false</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT6_PHASE_ERROR">0.0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT6_REQUESTED_DUTY_CYCLE">50.000</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT6_REQUESTED_OUT_FREQ">100.000</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT6_REQUESTED_PHASE">0.000</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT6_SEQUENCE_NUMBER">1</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT6_USED">false</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT7_DRIVES">BUFG</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT7_JITTER">0.0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT7_MATCHED_ROUTING">false</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT7_PHASE_ERROR">0.0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT7_REQUESTED_DUTY_CYCLE">50.000</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT7_REQUESTED_OUT_FREQ">100.000</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT7_REQUESTED_PHASE">0.000</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT7_SEQUENCE_NUMBER">1</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT7_USED">false</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUTPHY_REQUESTED_FREQ">600.000</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLK_IN1_BOARD_INTERFACE">Custom</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLK_IN2_BOARD_INTERFACE">Custom</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLK_IN_SEL_PORT">clk_in_sel</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLK_OUT1_PORT">cpu_clk</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLK_OUT1_USE_FINE_PS_GUI">false</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLK_OUT2_PORT">timer_clk</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLK_OUT2_USE_FINE_PS_GUI">false</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLK_OUT3_PORT">clk_out3</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLK_OUT3_USE_FINE_PS_GUI">false</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLK_OUT4_PORT">clk_out4</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLK_OUT4_USE_FINE_PS_GUI">false</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLK_OUT5_PORT">clk_out5</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLK_OUT5_USE_FINE_PS_GUI">false</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLK_OUT6_PORT">clk_out6</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLK_OUT6_USE_FINE_PS_GUI">false</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLK_OUT7_PORT">clk_out7</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLK_OUT7_USE_FINE_PS_GUI">false</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLK_VALID_PORT">CLK_VALID</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLOCK_MGR_TYPE">auto</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Component_Name">clk_pll</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.DADDR_PORT">daddr</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.DCLK_PORT">dclk</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.DEN_PORT">den</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.DIFF_CLK_IN1_BOARD_INTERFACE">Custom</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.DIFF_CLK_IN2_BOARD_INTERFACE">Custom</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.DIN_PORT">din</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.DOUT_PORT">dout</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.DRDY_PORT">drdy</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.DWE_PORT">dwe</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.ENABLE_CDDC">false</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.ENABLE_CLKOUTPHY">false</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.ENABLE_CLOCK_MONITOR">false</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.ENABLE_USER_CLOCK0">false</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.ENABLE_USER_CLOCK1">false</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.ENABLE_USER_CLOCK2">false</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.ENABLE_USER_CLOCK3">false</spirit:configurableElementValue>
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lacpu/rtl/xilinx_ip/data_bram_bank.xcix Normal file
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lacpu/rtl/xilinx_ip/data_ram/data_ram.coe
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@@ -1,3 +0,0 @@
memory_initialization_radix = 16;
memory_initialization_vector =
4c000020

104339
lacpu/rtl/xilinx_ip/inst_ram/inst_ram.coe
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lacpu/rtl/xilinx_ip/inst_ram/inst_ram.xci
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@@ -1,313 +0,0 @@
<?xml version="1.0" encoding="UTF-8"?>
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<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_EST_POWER_SUMMARY">Estimated Power for IP : 10.193999 mW</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PRIM_type_to_Implement">BRAM</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Pipeline_Stages">0</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Primitive">8kx2</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Read_Width_B">32</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Register_PortA_Output_of_Memory_Core">false</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Register_PortA_Output_of_Memory_Primitives">false</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Register_PortB_Output_of_Memory_Core">false</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Register_PortB_Output_of_Memory_Primitives">false</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Remaining_Memory_Locations">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Reset_Memory_Latch_A">false</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Reset_Memory_Latch_B">false</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Reset_Priority_A">CE</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Reset_Priority_B">CE</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Reset_Type">SYNC</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Use_AXI_ID">false</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Use_Byte_Write_Enable">true</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Use_Error_Injection_Pins">false</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Use_REGCEA_Pin">false</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Use_REGCEB_Pin">false</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Use_RSTA_Pin">false</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Use_RSTB_Pin">false</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Write_Depth_A">65535</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Write_Width_A">32</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Write_Width_B">32</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.ecctype">No_ECC</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.register_porta_input_of_softecc">false</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.register_portb_output_of_softecc">false</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.softecc">false</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.use_bram_block">Stand_Alone</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.ARCHITECTURE">artix7</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.BASE_BOARD_PART"/>
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.BOARD_CONNECTIONS"/>
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.DEVICE">xc7a100t</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.PACKAGE">csg324</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.PREFHDL">VERILOG</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.SILICON_REVISION"/>
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.SIMULATOR_LANGUAGE">MIXED</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.SPEEDGRADE">-1</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.STATIC_POWER"/>
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.TEMPERATURE_GRADE"/>
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.USE_RDI_CUSTOMIZATION">TRUE</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.USE_RDI_GENERATION">TRUE</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.IPCONTEXT">IP_Flow</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.IPREVISION">4</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.MANAGED">TRUE</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.OUTPUTDIR">.</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SELECTEDSIMMODEL"/>
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SHAREDDIR">.</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SWVERSION">2019.2</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SYNTHESISFLOW">OUT_OF_CONTEXT</spirit:configurableElementValue>
</spirit:configurableElementValues>
<spirit:vendorExtensions>
<xilinx:componentInstanceExtensions>
<xilinx:configElementInfos>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AXILITE_SLAVE_S_AXI.ADDR_WIDTH" xilinx:valueSource="auto"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AXILITE_SLAVE_S_AXI.ARUSER_WIDTH" xilinx:valueSource="constant"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AXILITE_SLAVE_S_AXI.AWUSER_WIDTH" xilinx:valueSource="constant"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AXILITE_SLAVE_S_AXI.BUSER_WIDTH" xilinx:valueSource="constant"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AXILITE_SLAVE_S_AXI.DATA_WIDTH" xilinx:valueSource="auto"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AXILITE_SLAVE_S_AXI.HAS_BRESP" xilinx:valueSource="auto"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AXILITE_SLAVE_S_AXI.HAS_BURST" xilinx:valueSource="auto"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AXILITE_SLAVE_S_AXI.HAS_CACHE" xilinx:valueSource="constant"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AXILITE_SLAVE_S_AXI.HAS_LOCK" xilinx:valueSource="constant"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AXILITE_SLAVE_S_AXI.HAS_PROT" xilinx:valueSource="constant"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AXILITE_SLAVE_S_AXI.HAS_QOS" xilinx:valueSource="constant"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AXILITE_SLAVE_S_AXI.HAS_REGION" xilinx:valueSource="constant"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AXILITE_SLAVE_S_AXI.HAS_RRESP" xilinx:valueSource="auto"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AXILITE_SLAVE_S_AXI.HAS_WSTRB" xilinx:valueSource="auto"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AXILITE_SLAVE_S_AXI.PROTOCOL" xilinx:valueSource="auto"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AXILITE_SLAVE_S_AXI.RUSER_WIDTH" xilinx:valueSource="constant"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AXILITE_SLAVE_S_AXI.WUSER_WIDTH" xilinx:valueSource="constant"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AXI_SLAVE_S_AXI.ADDR_WIDTH" xilinx:valueSource="auto"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AXI_SLAVE_S_AXI.ARUSER_WIDTH" xilinx:valueSource="constant"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AXI_SLAVE_S_AXI.AWUSER_WIDTH" xilinx:valueSource="constant"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AXI_SLAVE_S_AXI.BUSER_WIDTH" xilinx:valueSource="constant"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AXI_SLAVE_S_AXI.DATA_WIDTH" xilinx:valueSource="auto"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AXI_SLAVE_S_AXI.HAS_BRESP" xilinx:valueSource="auto"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AXI_SLAVE_S_AXI.HAS_BURST" xilinx:valueSource="auto"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AXI_SLAVE_S_AXI.HAS_CACHE" xilinx:valueSource="constant"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AXI_SLAVE_S_AXI.HAS_LOCK" xilinx:valueSource="constant"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AXI_SLAVE_S_AXI.HAS_PROT" xilinx:valueSource="constant"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AXI_SLAVE_S_AXI.HAS_QOS" xilinx:valueSource="constant"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AXI_SLAVE_S_AXI.HAS_REGION" xilinx:valueSource="constant"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AXI_SLAVE_S_AXI.HAS_RRESP" xilinx:valueSource="auto"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AXI_SLAVE_S_AXI.HAS_WSTRB" xilinx:valueSource="auto"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AXI_SLAVE_S_AXI.PROTOCOL" xilinx:valueSource="auto"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AXI_SLAVE_S_AXI.RUSER_WIDTH" xilinx:valueSource="constant"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AXI_SLAVE_S_AXI.WUSER_WIDTH" xilinx:valueSource="constant"/>
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Byte_Size" xilinx:valueSource="user"/>
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Coe_File" xilinx:valueSource="user"/>
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Load_Init_File" xilinx:valueSource="user"/>
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Read_Width_A" xilinx:valueSource="user"/>
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Read_Width_B" xilinx:valueSource="user"/>
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Register_PortA_Output_of_Memory_Primitives" xilinx:valueSource="user"/>
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Use_Byte_Write_Enable" xilinx:valueSource="user"/>
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Write_Depth_A" xilinx:valueSource="user"/>
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Write_Width_A" xilinx:valueSource="user"/>
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Write_Width_B" xilinx:valueSource="user"/>
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</spirit:vendorExtensions>
</spirit:componentInstance>
</spirit:componentInstances>
</spirit:design>

260
lacpu/run_vivado/la32r/la32r.xpr
View File

@@ -7,7 +7,7 @@
<DefaultLaunch Dir="$PRUNDIR"/> <DefaultLaunch Dir="$PRUNDIR"/>
<Configuration> <Configuration>
<Option Name="Id" Val="b071601f1fd144c49e8a7855a3da572b"/> <Option Name="Id" Val="b071601f1fd144c49e8a7855a3da572b"/>
<Option Name="Part" Val="xc7a100tcsg324-1"/> <Option Name="Part" Val="xc7a200tfbg676-1"/>
<Option Name="CompiledLibDir" Val="$PCACHEDIR/compile_simlib"/> <Option Name="CompiledLibDir" Val="$PCACHEDIR/compile_simlib"/>
<Option Name="CompiledLibDirXSim" Val=""/> <Option Name="CompiledLibDirXSim" Val=""/>
<Option Name="CompiledLibDirModelSim" Val="$PCACHEDIR/compile_simlib/modelsim"/> <Option Name="CompiledLibDirModelSim" Val="$PCACHEDIR/compile_simlib/modelsim"/>
@@ -24,25 +24,25 @@
<Option Name="IPOutputRepo" Val="$PCACHEDIR/ip"/> <Option Name="IPOutputRepo" Val="$PCACHEDIR/ip"/>
<Option Name="IPCachePermission" Val="read"/> <Option Name="IPCachePermission" Val="read"/>
<Option Name="IPCachePermission" Val="write"/> <Option Name="IPCachePermission" Val="write"/>
<Option Name="EnableCoreContainer" Val="FALSE"/> <Option Name="EnableCoreContainer" Val="TRUE"/>
<Option Name="CreateRefXciForCoreContainers" Val="FALSE"/> <Option Name="CreateRefXciForCoreContainers" Val="FALSE"/>
<Option Name="IPUserFilesDir" Val="$PIPUSERFILESDIR"/> <Option Name="IPUserFilesDir" Val="$PIPUSERFILESDIR"/>
<Option Name="IPStaticSourceDir" Val="$PIPUSERFILESDIR/ipstatic"/> <Option Name="IPStaticSourceDir" Val="$PIPUSERFILESDIR/ipstatic"/>
<Option Name="EnableBDX" Val="FALSE"/> <Option Name="EnableBDX" Val="FALSE"/>
<Option Name="WTXSimLaunchSim" Val="36"/> <Option Name="WTXSimLaunchSim" Val="37"/>
<Option Name="WTModelSimLaunchSim" Val="0"/> <Option Name="WTModelSimLaunchSim" Val="0"/>
<Option Name="WTQuestaLaunchSim" Val="0"/> <Option Name="WTQuestaLaunchSim" Val="0"/>
<Option Name="WTIesLaunchSim" Val="0"/> <Option Name="WTIesLaunchSim" Val="0"/>
<Option Name="WTVcsLaunchSim" Val="0"/> <Option Name="WTVcsLaunchSim" Val="0"/>
<Option Name="WTRivieraLaunchSim" Val="0"/> <Option Name="WTRivieraLaunchSim" Val="0"/>
<Option Name="WTActivehdlLaunchSim" Val="0"/> <Option Name="WTActivehdlLaunchSim" Val="0"/>
<Option Name="WTXSimExportSim" Val="23"/> <Option Name="WTXSimExportSim" Val="37"/>
<Option Name="WTModelSimExportSim" Val="23"/> <Option Name="WTModelSimExportSim" Val="37"/>
<Option Name="WTQuestaExportSim" Val="23"/> <Option Name="WTQuestaExportSim" Val="37"/>
<Option Name="WTIesExportSim" Val="23"/> <Option Name="WTIesExportSim" Val="37"/>
<Option Name="WTVcsExportSim" Val="23"/> <Option Name="WTVcsExportSim" Val="37"/>
<Option Name="WTRivieraExportSim" Val="23"/> <Option Name="WTRivieraExportSim" Val="37"/>
<Option Name="WTActivehdlExportSim" Val="23"/> <Option Name="WTActivehdlExportSim" Val="37"/>
<Option Name="GenerateIPUpgradeLog" Val="TRUE"/> <Option Name="GenerateIPUpgradeLog" Val="TRUE"/>
<Option Name="XSimRadix" Val="hex"/> <Option Name="XSimRadix" Val="hex"/>
<Option Name="XSimTimeUnit" Val="ns"/> <Option Name="XSimTimeUnit" Val="ns"/>
@@ -54,133 +54,203 @@
<FileSets Version="1" Minor="31"> <FileSets Version="1" Minor="31">
<FileSet Name="sources_1" Type="DesignSrcs" RelSrcDir="$PSRCDIR/sources_1"> <FileSet Name="sources_1" Type="DesignSrcs" RelSrcDir="$PSRCDIR/sources_1">
<Filter Type="Srcs"/> <Filter Type="Srcs"/>
<File Path="$PPRDIR/../../rtl/xilinx_ip/data_ram/data_ram.xci"> <File Path="$PPRDIR/../../rtl/mycpu/alu.v">
<FileInfo> <FileInfo>
<Attr Name="UsedIn" Val="synthesis"/> <Attr Name="UsedIn" Val="synthesis"/>
<Attr Name="UsedIn" Val="implementation"/> <Attr Name="UsedIn" Val="implementation"/>
<Attr Name="UsedIn" Val="simulation"/> <Attr Name="UsedIn" Val="simulation"/>
</FileInfo> </FileInfo>
</File> </File>
<File Path="$PPRDIR/../../rtl/cpu/alu.v"> <File Path="$PPRDIR/../../rtl/mycpu/axi_ctrl.v">
<FileInfo> <FileInfo>
<Attr Name="UsedIn" Val="synthesis"/> <Attr Name="UsedIn" Val="synthesis"/>
<Attr Name="UsedIn" Val="implementation"/> <Attr Name="UsedIn" Val="implementation"/>
<Attr Name="UsedIn" Val="simulation"/> <Attr Name="UsedIn" Val="simulation"/>
</FileInfo> </FileInfo>
</File> </File>
<File Path="$PPRDIR/../../rtl/cpu/bru.v"> <File Path="$PPRDIR/../../rtl/axi_wrap/axi_wrap.v">
<FileInfo> <FileInfo>
<Attr Name="UsedIn" Val="synthesis"/> <Attr Name="UsedIn" Val="synthesis"/>
<Attr Name="UsedIn" Val="implementation"/> <Attr Name="UsedIn" Val="implementation"/>
<Attr Name="UsedIn" Val="simulation"/> <Attr Name="UsedIn" Val="simulation"/>
</FileInfo> </FileInfo>
</File> </File>
<File Path="$PPRDIR/../../rtl/cpu/csr.v"> <File Path="$PPRDIR/../../rtl/ram_wrap/axi_wrap_ram.v">
<FileInfo> <FileInfo>
<Attr Name="UsedIn" Val="synthesis"/> <Attr Name="UsedIn" Val="synthesis"/>
<Attr Name="UsedIn" Val="implementation"/> <Attr Name="UsedIn" Val="implementation"/>
<Attr Name="UsedIn" Val="simulation"/> <Attr Name="UsedIn" Val="simulation"/>
</FileInfo> </FileInfo>
</File> </File>
<File Path="$PPRDIR/../../rtl/cpu/div.v"> <File Path="$PPRDIR/../../rtl/mycpu/bru.v">
<FileInfo> <FileInfo>
<Attr Name="UsedIn" Val="synthesis"/> <Attr Name="UsedIn" Val="synthesis"/>
<Attr Name="UsedIn" Val="implementation"/> <Attr Name="UsedIn" Val="implementation"/>
<Attr Name="UsedIn" Val="simulation"/> <Attr Name="UsedIn" Val="simulation"/>
</FileInfo> </FileInfo>
</File> </File>
<File Path="$PPRDIR/../../rtl/cpu/exe_stage.v"> <File Path="$PPRDIR/../../rtl/mycpu/cache_data.v">
<FileInfo> <FileInfo>
<Attr Name="UsedIn" Val="synthesis"/> <Attr Name="UsedIn" Val="synthesis"/>
<Attr Name="UsedIn" Val="implementation"/> <Attr Name="UsedIn" Val="implementation"/>
<Attr Name="UsedIn" Val="simulation"/> <Attr Name="UsedIn" Val="simulation"/>
</FileInfo> </FileInfo>
</File> </File>
<File Path="$PPRDIR/../../rtl/cpu/id_stage.v"> <File Path="$PPRDIR/../../rtl/mycpu/cache_tag.v">
<FileInfo> <FileInfo>
<Attr Name="UsedIn" Val="synthesis"/> <Attr Name="UsedIn" Val="synthesis"/>
<Attr Name="UsedIn" Val="implementation"/> <Attr Name="UsedIn" Val="implementation"/>
<Attr Name="UsedIn" Val="simulation"/> <Attr Name="UsedIn" Val="simulation"/>
</FileInfo> </FileInfo>
</File> </File>
<File Path="$PPRDIR/../../rtl/cpu/if_stage.v"> <File Path="$PPRDIR/../../rtl/CONFREG/confreg.v">
<FileInfo> <FileInfo>
<Attr Name="UsedIn" Val="synthesis"/> <Attr Name="UsedIn" Val="synthesis"/>
<Attr Name="UsedIn" Val="implementation"/> <Attr Name="UsedIn" Val="implementation"/>
<Attr Name="UsedIn" Val="simulation"/> <Attr Name="UsedIn" Val="simulation"/>
</FileInfo> </FileInfo>
</File> </File>
<File Path="$PPRDIR/../../rtl/cpu/inst_decoder.v"> <File Path="$PPRDIR/../../rtl/mycpu/csr.v">
<FileInfo> <FileInfo>
<Attr Name="UsedIn" Val="synthesis"/> <Attr Name="UsedIn" Val="synthesis"/>
<Attr Name="UsedIn" Val="implementation"/> <Attr Name="UsedIn" Val="implementation"/>
<Attr Name="UsedIn" Val="simulation"/> <Attr Name="UsedIn" Val="simulation"/>
</FileInfo> </FileInfo>
</File> </File>
<File Path="$PPRDIR/../../rtl/cpu/lsu.v"> <File Path="$PPRDIR/../../rtl/mycpu/dcache.v">
<FileInfo> <FileInfo>
<Attr Name="UsedIn" Val="synthesis"/> <Attr Name="UsedIn" Val="synthesis"/>
<Attr Name="UsedIn" Val="implementation"/> <Attr Name="UsedIn" Val="implementation"/>
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</FileInfo> </FileInfo>
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<File Path="$PPRDIR/../../rtl/cpu/mem_stage.v"> <File Path="$PPRDIR/../../rtl/mycpu/div.v">
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</File> </File>
<File Path="$PPRDIR/../../rtl/cpu/mul.v"> <File Path="$PPRDIR/../../rtl/mycpu/exe_stage.v">
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<Attr Name="UsedIn" Val="synthesis"/> <Attr Name="UsedIn" Val="synthesis"/>
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</FileInfo> </FileInfo>
</File> </File>
<File Path="$PPRDIR/../../rtl/cpu/mul_div_lock.v"> <File Path="$PPRDIR/../../rtl/mycpu/icache.v">
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<Attr Name="UsedIn" Val="synthesis"/> <Attr Name="UsedIn" Val="synthesis"/>
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<Attr Name="UsedIn" Val="simulation"/> <Attr Name="UsedIn" Val="simulation"/>
</FileInfo> </FileInfo>
</File> </File>
<File Path="$PPRDIR/../../rtl/cpu/mul_div_top.v"> <File Path="$PPRDIR/../../rtl/mycpu/id_stage.v">
<FileInfo> <FileInfo>
<Attr Name="UsedIn" Val="synthesis"/> <Attr Name="UsedIn" Val="synthesis"/>
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<Attr Name="UsedIn" Val="synthesis"/> <Attr Name="UsedIn" Val="synthesis"/>
<Attr Name="UsedIn" Val="implementation"/> <Attr Name="UsedIn" Val="implementation"/>
<Attr Name="UsedIn" Val="simulation"/> <Attr Name="UsedIn" Val="simulation"/>
</FileInfo> </FileInfo>
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<Attr Name="UsedIn" Val="synthesis"/> <Attr Name="UsedIn" Val="synthesis"/>
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</FileInfo> </FileInfo>
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</FileInfo> </FileInfo>
</File> </File>
<File Path="$PPRDIR/../../rtl/cpu/tools.v"> <File Path="$PPRDIR/../../rtl/mycpu/mem_stage.v">
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</FileInfo> </FileInfo>
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<Attr Name="UsedIn" Val="synthesis"/>
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<Attr Name="UsedIn" Val="synthesis"/>
<Attr Name="UsedIn" Val="implementation"/>
<Attr Name="UsedIn" Val="simulation"/>
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<Attr Name="UsedIn" Val="synthesis"/>
<Attr Name="UsedIn" Val="implementation"/>
<Attr Name="UsedIn" Val="simulation"/>
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<Attr Name="UsedIn" Val="synthesis"/>
<Attr Name="UsedIn" Val="implementation"/>
<Attr Name="UsedIn" Val="simulation"/>
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</File>
<File Path="$PPRDIR/../../rtl/mycpu/mycpu_core.v">
<FileInfo>
<Attr Name="UsedIn" Val="synthesis"/>
<Attr Name="UsedIn" Val="implementation"/>
<Attr Name="UsedIn" Val="simulation"/>
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<Attr Name="UsedIn" Val="synthesis"/>
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<Attr Name="UsedIn" Val="synthesis"/>
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<Attr Name="UsedIn" Val="simulation"/>
</FileInfo>
</File>
<File Path="$PPRDIR/../../rtl/mycpu/regfile.v">
<FileInfo>
<Attr Name="UsedIn" Val="synthesis"/>
<Attr Name="UsedIn" Val="implementation"/>
<Attr Name="UsedIn" Val="simulation"/>
</FileInfo>
</File>
<File Path="$PPRDIR/../../rtl/mycpu/tools.v">
<FileInfo>
<Attr Name="UsedIn" Val="synthesis"/>
<Attr Name="UsedIn" Val="implementation"/>
<Attr Name="UsedIn" Val="simulation"/>
</FileInfo>
</File>
<File Path="$PPRDIR/../../rtl/mycpu/uncache.v">
<FileInfo>
<Attr Name="UsedIn" Val="synthesis"/>
<Attr Name="UsedIn" Val="implementation"/>
<Attr Name="UsedIn" Val="simulation"/>
</FileInfo>
</File>
<File Path="$PPRDIR/../../rtl/mycpu/wb_stage.v">
<FileInfo> <FileInfo>
<Attr Name="UsedIn" Val="synthesis"/> <Attr Name="UsedIn" Val="synthesis"/>
<Attr Name="UsedIn" Val="implementation"/> <Attr Name="UsedIn" Val="implementation"/>
@@ -194,15 +264,11 @@
<Attr Name="UsedIn" Val="simulation"/> <Attr Name="UsedIn" Val="simulation"/>
</FileInfo> </FileInfo>
</File> </File>
<File Path="$PPRDIR/../../rtl/xilinx_ip/inst_ram/inst_ram.coe"> <File Path="$PPRDIR/../../rtl/mycpu/tlb.v">
<FileInfo>
<Attr Name="UsedIn" Val="synthesis"/>
<Attr Name="UsedIn" Val="simulation"/>
</FileInfo>
</File>
<File Path="$PPRDIR/../../rtl/xilinx_ip/data_ram/data_ram.coe">
<FileInfo> <FileInfo>
<Attr Name="AutoDisabled" Val="1"/>
<Attr Name="UsedIn" Val="synthesis"/> <Attr Name="UsedIn" Val="synthesis"/>
<Attr Name="UsedIn" Val="implementation"/>
<Attr Name="UsedIn" Val="simulation"/> <Attr Name="UsedIn" Val="simulation"/>
</FileInfo> </FileInfo>
</File> </File>
@@ -214,7 +280,7 @@
</FileSet> </FileSet>
<FileSet Name="constrs_1" Type="Constrs" RelSrcDir="$PSRCDIR/constrs_1"> <FileSet Name="constrs_1" Type="Constrs" RelSrcDir="$PSRCDIR/constrs_1">
<Filter Type="Constrs"/> <Filter Type="Constrs"/>
<File Path="$PPRDIR/../Nexys4DDR.xdc"> <File Path="$PPRDIR/../soc_lite.xdc">
<FileInfo> <FileInfo>
<Attr Name="UsedIn" Val="synthesis"/> <Attr Name="UsedIn" Val="synthesis"/>
<Attr Name="UsedIn" Val="implementation"/> <Attr Name="UsedIn" Val="implementation"/>
@@ -226,13 +292,6 @@
</FileSet> </FileSet>
<FileSet Name="sim_1" Type="SimulationSrcs" RelSrcDir="$PSRCDIR/sim_1"> <FileSet Name="sim_1" Type="SimulationSrcs" RelSrcDir="$PSRCDIR/sim_1">
<Filter Type="Srcs"/> <Filter Type="Srcs"/>
<File Path="$PPRDIR/sim/soc_tb.v">
<FileInfo>
<Attr Name="UsedIn" Val="synthesis"/>
<Attr Name="UsedIn" Val="implementation"/>
<Attr Name="UsedIn" Val="simulation"/>
</FileInfo>
</File>
<File Path="$PPRDIR/sim/cpu_tb_behav.wcfg"> <File Path="$PPRDIR/sim/cpu_tb_behav.wcfg">
<FileInfo> <FileInfo>
<Attr Name="UsedIn" Val="simulation"/> <Attr Name="UsedIn" Val="simulation"/>
@@ -240,7 +299,7 @@
</File> </File>
<Config> <Config>
<Option Name="DesignMode" Val="RTL"/> <Option Name="DesignMode" Val="RTL"/>
<Option Name="TopModule" Val="cpu_tb"/> <Option Name="TopModule" Val="cache_data_v6"/>
<Option Name="TopLib" Val="xil_defaultlib"/> <Option Name="TopLib" Val="xil_defaultlib"/>
<Option Name="TopAutoSet" Val="TRUE"/> <Option Name="TopAutoSet" Val="TRUE"/>
<Option Name="TransportPathDelay" Val="0"/> <Option Name="TransportPathDelay" Val="0"/>
@@ -258,8 +317,15 @@
<Option Name="TopAutoSet" Val="TRUE"/> <Option Name="TopAutoSet" Val="TRUE"/>
</Config> </Config>
</FileSet> </FileSet>
<FileSet Name="pll" Type="BlockSrcs" RelSrcDir="$PSRCDIR/pll"> <FileSet Name="data_bram_bank" Type="BlockSrcs" RelSrcDir="$PSRCDIR/data_bram_bank">
<File Path="$PSRCDIR/sources_1/ip/pll/pll.xci"> <File Path="$PPRDIR/../../rtl/xilinx_ip/data_bram_bank.xcix">
<FileInfo>
<Attr Name="UsedIn" Val="synthesis"/>
<Attr Name="UsedIn" Val="implementation"/>
<Attr Name="UsedIn" Val="simulation"/>
</FileInfo>
</File>
<File Path="$PPRDIR/../../rtl/xilinx_ip/data_bram_bank/data_bram_bank.xci">
<FileInfo> <FileInfo>
<Attr Name="UsedIn" Val="synthesis"/> <Attr Name="UsedIn" Val="synthesis"/>
<Attr Name="UsedIn" Val="implementation"/> <Attr Name="UsedIn" Val="implementation"/>
@@ -267,12 +333,12 @@
</FileInfo> </FileInfo>
</File> </File>
<Config> <Config>
<Option Name="TopModule" Val="pll"/> <Option Name="TopModule" Val="data_bram_bank"/>
<Option Name="UseBlackboxStub" Val="1"/> <Option Name="UseBlackboxStub" Val="1"/>
</Config> </Config>
</FileSet> </FileSet>
<FileSet Name="inst_ram" Type="BlockSrcs" RelSrcDir="$PSRCDIR/inst_ram"> <FileSet Name="axi_ram" Type="BlockSrcs" RelSrcDir="$PSRCDIR/axi_ram">
<File Path="$PPRDIR/../../rtl/xilinx_ip/inst_ram/inst_ram.xci"> <File Path="$PPRDIR/../../rtl/xilinx_ip/axi_ram/axi_ram.xci">
<FileInfo> <FileInfo>
<Attr Name="UsedIn" Val="synthesis"/> <Attr Name="UsedIn" Val="synthesis"/>
<Attr Name="UsedIn" Val="implementation"/> <Attr Name="UsedIn" Val="implementation"/>
@@ -280,7 +346,33 @@
</FileInfo> </FileInfo>
</File> </File>
<Config> <Config>
<Option Name="TopModule" Val="inst_ram"/> <Option Name="TopModule" Val="axi_ram"/>
<Option Name="UseBlackboxStub" Val="1"/>
</Config>
</FileSet>
<FileSet Name="axi_crossbar_1x2" Type="BlockSrcs" RelSrcDir="$PSRCDIR/axi_crossbar_1x2">
<File Path="$PPRDIR/../../rtl/xilinx_ip/axi_crossbar_1x2/axi_crossbar_1x2.xci">
<FileInfo>
<Attr Name="UsedIn" Val="synthesis"/>
<Attr Name="UsedIn" Val="implementation"/>
<Attr Name="UsedIn" Val="simulation"/>
</FileInfo>
</File>
<Config>
<Option Name="TopModule" Val="axi_crossbar_1x2"/>
<Option Name="UseBlackboxStub" Val="1"/>
</Config>
</FileSet>
<FileSet Name="clk_pll" Type="BlockSrcs" RelSrcDir="$PSRCDIR/clk_pll">
<File Path="$PPRDIR/../../rtl/xilinx_ip/clk_pll/clk_pll.xci">
<FileInfo>
<Attr Name="UsedIn" Val="synthesis"/>
<Attr Name="UsedIn" Val="implementation"/>
<Attr Name="UsedIn" Val="simulation"/>
</FileInfo>
</File>
<Config>
<Option Name="TopModule" Val="clk_pll"/>
<Option Name="UseBlackboxStub" Val="1"/> <Option Name="UseBlackboxStub" Val="1"/>
</Config> </Config>
</FileSet> </FileSet>
@@ -304,7 +396,7 @@
</Simulator> </Simulator>
</Simulators> </Simulators>
<Runs Version="1" Minor="11"> <Runs Version="1" Minor="11">
<Run Id="synth_1" Type="Ft3:Synth" SrcSet="sources_1" Part="xc7a100tcsg324-1" ConstrsSet="constrs_1" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" State="current" Dir="$PRUNDIR/synth_1" IncludeInArchive="true"> <Run Id="synth_1" Type="Ft3:Synth" SrcSet="sources_1" Part="xc7a200tfbg676-1" ConstrsSet="constrs_1" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" State="current" Dir="$PRUNDIR/synth_1" IncludeInArchive="true">
<Strategy Version="1" Minor="2"> <Strategy Version="1" Minor="2">
<StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2019"/> <StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2019"/>
<Step Id="synth_design"/> <Step Id="synth_design"/>
@@ -314,7 +406,7 @@
<Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/> <Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
<RQSFiles/> <RQSFiles/>
</Run> </Run>
<Run Id="pll_synth_1" Type="Ft3:Synth" SrcSet="pll" Part="xc7a100tcsg324-1" ConstrsSet="pll" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" Dir="$PRUNDIR/pll_synth_1" IncludeInArchive="true"> <Run Id="data_bram_bank_synth_1" Type="Ft3:Synth" SrcSet="data_bram_bank" Part="xc7a200tfbg676-1" ConstrsSet="data_bram_bank" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" Dir="$PRUNDIR/data_bram_bank_synth_1" IncludeInArchive="true">
<Strategy Version="1" Minor="2"> <Strategy Version="1" Minor="2">
<StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2019"/> <StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2019"/>
<Step Id="synth_design"/> <Step Id="synth_design"/>
@@ -324,7 +416,27 @@
<Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/> <Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
<RQSFiles/> <RQSFiles/>
</Run> </Run>
<Run Id="inst_ram_synth_1" Type="Ft3:Synth" SrcSet="inst_ram" Part="xc7a100tcsg324-1" ConstrsSet="inst_ram" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" Dir="$PRUNDIR/inst_ram_synth_1" IncludeInArchive="true"> <Run Id="axi_ram_synth_1" Type="Ft3:Synth" SrcSet="axi_ram" Part="xc7a200tfbg676-1" ConstrsSet="axi_ram" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" Dir="$PRUNDIR/axi_ram_synth_1" IncludeInArchive="true">
<Strategy Version="1" Minor="2">
<StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2019"/>
<Step Id="synth_design"/>
</Strategy>
<GeneratedRun Dir="$PRUNDIR" File="gen_run.xml"/>
<ReportStrategy Name="Vivado Synthesis Default Reports" Flow="Vivado Synthesis 2019"/>
<Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
<RQSFiles/>
</Run>
<Run Id="axi_crossbar_1x2_synth_1" Type="Ft3:Synth" SrcSet="axi_crossbar_1x2" Part="xc7a200tfbg676-1" ConstrsSet="axi_crossbar_1x2" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" Dir="$PRUNDIR/axi_crossbar_1x2_synth_1" IncludeInArchive="true">
<Strategy Version="1" Minor="2">
<StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2019"/>
<Step Id="synth_design"/>
</Strategy>
<GeneratedRun Dir="$PRUNDIR" File="gen_run.xml"/>
<ReportStrategy Name="Vivado Synthesis Default Reports" Flow="Vivado Synthesis 2019"/>
<Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
<RQSFiles/>
</Run>
<Run Id="clk_pll_synth_1" Type="Ft3:Synth" SrcSet="clk_pll" Part="xc7a200tfbg676-1" ConstrsSet="clk_pll" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" Dir="$PRUNDIR/clk_pll_synth_1" IncludeInArchive="true">
<Strategy Version="1" Minor="2"> <Strategy Version="1" Minor="2">
<StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2019"> <StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2019">
<Desc>Vivado Synthesis Defaults</Desc> <Desc>Vivado Synthesis Defaults</Desc>
@@ -336,7 +448,7 @@
<Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/> <Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
<RQSFiles/> <RQSFiles/>
</Run> </Run>
<Run Id="impl_1" Type="Ft2:EntireDesign" Part="xc7a100tcsg324-1" ConstrsSet="constrs_1" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" State="current" Dir="$PRUNDIR/impl_1" SynthRun="synth_1" IncludeInArchive="true" GenFullBitstream="true"> <Run Id="impl_1" Type="Ft2:EntireDesign" Part="xc7a200tfbg676-1" ConstrsSet="constrs_1" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" State="current" Dir="$PRUNDIR/impl_1" SynthRun="synth_1" IncludeInArchive="true" GenFullBitstream="true">
<Strategy Version="1" Minor="2"> <Strategy Version="1" Minor="2">
<StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2019"/> <StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2019"/>
<Step Id="init_design"/> <Step Id="init_design"/>
@@ -354,7 +466,7 @@
<Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/> <Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
<RQSFiles/> <RQSFiles/>
</Run> </Run>
<Run Id="pll_impl_1" Type="Ft2:EntireDesign" Part="xc7a100tcsg324-1" ConstrsSet="pll" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" SynthRun="pll_synth_1" IncludeInArchive="false" GenFullBitstream="true"> <Run Id="data_bram_bank_impl_1" Type="Ft2:EntireDesign" Part="xc7a200tfbg676-1" ConstrsSet="data_bram_bank" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" SynthRun="data_bram_bank_synth_1" IncludeInArchive="false" GenFullBitstream="true">
<Strategy Version="1" Minor="2"> <Strategy Version="1" Minor="2">
<StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2019"/> <StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2019"/>
<Step Id="init_design"/> <Step Id="init_design"/>
@@ -371,7 +483,41 @@
<Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/> <Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
<RQSFiles/> <RQSFiles/>
</Run> </Run>
<Run Id="inst_ram_impl_1" Type="Ft2:EntireDesign" Part="xc7a100tcsg324-1" ConstrsSet="inst_ram" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" SynthRun="inst_ram_synth_1" IncludeInArchive="false" GenFullBitstream="true"> <Run Id="axi_ram_impl_1" Type="Ft2:EntireDesign" Part="xc7a200tfbg676-1" ConstrsSet="axi_ram" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" SynthRun="axi_ram_synth_1" IncludeInArchive="false" GenFullBitstream="true">
<Strategy Version="1" Minor="2">
<StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2019"/>
<Step Id="init_design"/>
<Step Id="opt_design"/>
<Step Id="power_opt_design"/>
<Step Id="place_design"/>
<Step Id="post_place_power_opt_design"/>
<Step Id="phys_opt_design" EnableStepBool="1"/>
<Step Id="route_design"/>
<Step Id="post_route_phys_opt_design"/>
<Step Id="write_bitstream"/>
</Strategy>
<ReportStrategy Name="Vivado Implementation Default Reports" Flow="Vivado Implementation 2019"/>
<Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
<RQSFiles/>
</Run>
<Run Id="axi_crossbar_1x2_impl_1" Type="Ft2:EntireDesign" Part="xc7a200tfbg676-1" ConstrsSet="axi_crossbar_1x2" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" SynthRun="axi_crossbar_1x2_synth_1" IncludeInArchive="false" GenFullBitstream="true">
<Strategy Version="1" Minor="2">
<StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2019"/>
<Step Id="init_design"/>
<Step Id="opt_design"/>
<Step Id="power_opt_design"/>
<Step Id="place_design"/>
<Step Id="post_place_power_opt_design"/>
<Step Id="phys_opt_design" EnableStepBool="1"/>
<Step Id="route_design"/>
<Step Id="post_route_phys_opt_design"/>
<Step Id="write_bitstream"/>
</Strategy>
<ReportStrategy Name="Vivado Implementation Default Reports" Flow="Vivado Implementation 2019"/>
<Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
<RQSFiles/>
</Run>
<Run Id="clk_pll_impl_1" Type="Ft2:EntireDesign" Part="xc7a200tfbg676-1" ConstrsSet="clk_pll" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" SynthRun="clk_pll_synth_1" IncludeInArchive="false" GenFullBitstream="true">
<Strategy Version="1" Minor="2"> <Strategy Version="1" Minor="2">
<StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2019"> <StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2019">
<Desc>Default settings for Implementation.</Desc> <Desc>Default settings for Implementation.</Desc>

92
lacpu/run_vivado/soc_lite.xdc Normal file
View File

@@ -0,0 +1,92 @@
#set_property SEVERITY {Warning} [get_drc_checks RTSTAT-2]
#时钟信号连接
set_property PACKAGE_PIN AC19 [get_ports clk]
set_property CLOCK_DEDICATED_ROUTE BACKBONE [get_nets clk]
create_clock -period 10.000 -name clk -waveform {0.000 5.000} [get_ports clk]
#reset
set_property PACKAGE_PIN Y3 [get_ports resetn]
#LED
set_property PACKAGE_PIN K23 [get_ports {led[0]}]
set_property PACKAGE_PIN J21 [get_ports {led[1]}]
set_property PACKAGE_PIN H23 [get_ports {led[2]}]
set_property PACKAGE_PIN J19 [get_ports {led[3]}]
set_property PACKAGE_PIN G9 [get_ports {led[4]}]
set_property PACKAGE_PIN J26 [get_ports {led[5]}]
set_property PACKAGE_PIN J23 [get_ports {led[6]}]
set_property PACKAGE_PIN J8 [get_ports {led[7]}]
set_property PACKAGE_PIN H8 [get_ports {led[8]}]
set_property PACKAGE_PIN G8 [get_ports {led[9]}]
set_property PACKAGE_PIN F7 [get_ports {led[10]}]
set_property PACKAGE_PIN A4 [get_ports {led[11]}]
set_property PACKAGE_PIN A5 [get_ports {led[12]}]
set_property PACKAGE_PIN A3 [get_ports {led[13]}]
set_property PACKAGE_PIN D5 [get_ports {led[14]}]
set_property PACKAGE_PIN H7 [get_ports {led[15]}]
#led_rg 0/1
set_property PACKAGE_PIN G7 [get_ports {led_rg0[0]}]
set_property PACKAGE_PIN F8 [get_ports {led_rg0[1]}]
set_property PACKAGE_PIN B5 [get_ports {led_rg1[0]}]
set_property PACKAGE_PIN D6 [get_ports {led_rg1[1]}]
#NUM
set_property PACKAGE_PIN D3 [get_ports {num_csn[7]}]
set_property PACKAGE_PIN D25 [get_ports {num_csn[6]}]
set_property PACKAGE_PIN D26 [get_ports {num_csn[5]}]
set_property PACKAGE_PIN E25 [get_ports {num_csn[4]}]
set_property PACKAGE_PIN E26 [get_ports {num_csn[3]}]
set_property PACKAGE_PIN G25 [get_ports {num_csn[2]}]
set_property PACKAGE_PIN G26 [get_ports {num_csn[1]}]
set_property PACKAGE_PIN H26 [get_ports {num_csn[0]}]
set_property PACKAGE_PIN C3 [get_ports {num_a_g[0]}]
set_property PACKAGE_PIN E6 [get_ports {num_a_g[1]}]
set_property PACKAGE_PIN B2 [get_ports {num_a_g[2]}]
set_property PACKAGE_PIN B4 [get_ports {num_a_g[3]}]
set_property PACKAGE_PIN E5 [get_ports {num_a_g[4]}]
set_property PACKAGE_PIN D4 [get_ports {num_a_g[5]}]
set_property PACKAGE_PIN A2 [get_ports {num_a_g[6]}]
#set_property PACKAGE_PIN C4 :DP
#switch
set_property PACKAGE_PIN AC21 [get_ports {switch[7]}]
set_property PACKAGE_PIN AD24 [get_ports {switch[6]}]
set_property PACKAGE_PIN AC22 [get_ports {switch[5]}]
set_property PACKAGE_PIN AC23 [get_ports {switch[4]}]
set_property PACKAGE_PIN AB6 [get_ports {switch[3]}]
set_property PACKAGE_PIN W6 [get_ports {switch[2]}]
set_property PACKAGE_PIN AA7 [get_ports {switch[1]}]
set_property PACKAGE_PIN Y6 [get_ports {switch[0]}]
#btn_key
set_property PACKAGE_PIN V8 [get_ports {btn_key_col[0]}]
set_property PACKAGE_PIN V9 [get_ports {btn_key_col[1]}]
set_property PACKAGE_PIN Y8 [get_ports {btn_key_col[2]}]
set_property PACKAGE_PIN V7 [get_ports {btn_key_col[3]}]
set_property PACKAGE_PIN U7 [get_ports {btn_key_row[0]}]
set_property PACKAGE_PIN W8 [get_ports {btn_key_row[1]}]
set_property PACKAGE_PIN Y7 [get_ports {btn_key_row[2]}]
set_property PACKAGE_PIN AA8 [get_ports {btn_key_row[3]}]
#btn_step
set_property PACKAGE_PIN Y5 [get_ports {btn_step[0]}]
set_property PACKAGE_PIN V6 [get_ports {btn_step[1]}]
set_property IOSTANDARD LVCMOS33 [get_ports clk]
set_property IOSTANDARD LVCMOS33 [get_ports resetn]
set_property IOSTANDARD LVCMOS33 [get_ports {led[*]}]
set_property IOSTANDARD LVCMOS33 [get_ports {led_rg0[*]}]
set_property IOSTANDARD LVCMOS33 [get_ports {led_rg1[*]}]
set_property IOSTANDARD LVCMOS33 [get_ports {num_a_g[*]}]
set_property IOSTANDARD LVCMOS33 [get_ports {num_csn[*]}]
set_property IOSTANDARD LVCMOS33 [get_ports {switch[*]}]
set_property IOSTANDARD LVCMOS33 [get_ports {btn_key_col[*]}]
set_property IOSTANDARD LVCMOS33 [get_ports {btn_key_row[*]}]
set_property IOSTANDARD LVCMOS33 [get_ports {btn_step[*]}]
set_false_path -from [get_clocks -of_objects [get_pins pll.clk_pll/inst/plle2_adv_inst/CLKOUT1]] -to [get_clocks -of_objects [get_pins pll.clk_pll/inst/plle2_adv_inst/CLKOUT0]]
set_false_path -from [get_clocks -of_objects [get_pins pll.clk_pll/inst/plle2_adv_inst/CLKOUT0]] -to [get_clocks -of_objects [get_pins pll.clk_pll/inst/plle2_adv_inst/CLKOUT1]]