[Modified] Switch soc_top&board to axi&xc7a200t
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293
lacpu/rtl/ram_wrap/axi_wrap_ram.v
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293
lacpu/rtl/ram_wrap/axi_wrap_ram.v
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/*------------------------------------------------------------------------------
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--------------------------------------------------------------------------------
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Copyright (c) 2016, Loongson Technology Corporation Limited.
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All rights reserved.
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Redistribution and use in source and binary forms, with or without modification,
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are permitted provided that the following conditions are met:
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1. Redistributions of source code must retain the above copyright notice, this
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list of conditions and the following disclaimer.
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2. Redistributions in binary form must reproduce the above copyright notice,
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this list of conditions and the following disclaimer in the documentation and/or
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other materials provided with the distribution.
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3. Neither the name of Loongson Technology Corporation Limited nor the names of
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its contributors may be used to endorse or promote products derived from this
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software without specific prior written permission.
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THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
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ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
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WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
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DISCLAIMED. IN NO EVENT SHALL LOONGSON TECHNOLOGY CORPORATION LIMITED BE LIABLE
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TO ANY PARTY FOR DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE
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GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
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THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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--------------------------------------------------------------------------------
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------------------------------------------------------------------------------*/
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//for func test, no define RUN_PERF_TEST
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`define _RUN_PERF_TEST
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module axi_wrap_ram(
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input wire aclk,
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input wire aresetn,
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//ar
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input wire [3 :0] axi_arid ,
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input wire [31:0] axi_araddr ,
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input wire [7 :0] axi_arlen ,
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input wire [2 :0] axi_arsize ,
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input wire [1 :0] axi_arburst,
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input wire [1 :0] axi_arlock ,
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input wire [3 :0] axi_arcache,
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input wire [2 :0] axi_arprot ,
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input wire axi_arvalid,
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output wire axi_arready,
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//r
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output wire [3 :0] axi_rid ,
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output wire [31:0] axi_rdata ,
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output wire [1 :0] axi_rresp ,
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output wire axi_rlast ,
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output wire axi_rvalid ,
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input wire axi_rready ,
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//aw
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input wire [3 :0] axi_awid ,
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input wire [31:0] axi_awaddr ,
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input wire [7 :0] axi_awlen ,
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input wire [2 :0] axi_awsize ,
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input wire [1 :0] axi_awburst,
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input wire [1 :0] axi_awlock ,
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input wire [3 :0] axi_awcache,
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input wire [2 :0] axi_awprot ,
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input wire axi_awvalid,
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output wire axi_awready,
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//w
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input wire [3 :0] axi_wid ,
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input wire [31:0] axi_wdata ,
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input wire [3 :0] axi_wstrb ,
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input wire axi_wlast ,
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input wire axi_wvalid ,
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output wire axi_wready ,
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//b
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output wire [3 :0] axi_bid ,
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output wire [1 :0] axi_bresp ,
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output wire axi_bvalid ,
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input wire axi_bready ,
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//from confreg
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input wire [4 :0] ram_random_mask
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);
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wire axi_arvalid_m_masked;
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wire axi_rready_m_masked;
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wire axi_awvalid_m_masked;
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wire axi_wvalid_m_masked;
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wire axi_bready_m_masked;
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wire axi_arready_s_unmasked;
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wire axi_rvalid_s_unmasked;
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wire axi_awready_s_unmasked;
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wire axi_wready_s_unmasked;
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wire axi_bvalid_s_unmasked;
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wire ar_and;
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wire r_and;
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wire aw_and;
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wire w_and;
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wire b_and;
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reg ar_nomask;
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reg aw_nomask;
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reg w_nomask;
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reg [4:0] pf_r2r;
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reg [1:0] pf_b2b;
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wire pf_r2r_nomask= pf_r2r==5'd0;
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wire pf_b2b_nomask= pf_b2b==2'd0;
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//mask
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`ifdef RUN_PERF_TEST
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assign ar_and = 1'b1;
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assign r_and = pf_r2r_nomask;
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assign aw_and = 1'b1;
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assign w_and = 1'b1;
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assign b_and = pf_b2b_nomask;
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`else
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assign ar_and = ram_random_mask[4] | ar_nomask;
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assign r_and = ram_random_mask[3] ;
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assign aw_and = ram_random_mask[2] | aw_nomask;
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assign w_and = ram_random_mask[1] | w_nomask;
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assign b_and = ram_random_mask[0] ;
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`endif
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always @(posedge aclk)
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begin
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//for func test, random mask
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ar_nomask <= !aresetn ? 1'b0 :
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axi_arvalid_m_masked&&axi_arready ? 1'b0 :
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axi_arvalid_m_masked ? 1'b1 : ar_nomask;
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aw_nomask <= !aresetn ? 1'b0 :
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axi_awvalid_m_masked&&axi_awready ? 1'b0 :
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axi_awvalid_m_masked ? 1'b1 : aw_nomask;
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w_nomask <= !aresetn ? 1'b0 :
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axi_wvalid_m_masked&&axi_wready ? 1'b0 :
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axi_wvalid_m_masked ? 1'b1 : w_nomask;
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//for perf test
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pf_r2r <= !aresetn ? 5'd0 :
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axi_arvalid_m_masked&&axi_arready ? 5'd25 :
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!pf_r2r_nomask ? pf_r2r-1'b1 : pf_r2r;
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pf_b2b <= !aresetn ? 2'd0 :
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axi_awvalid_m_masked&&axi_awready ? 2'd3 :
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!pf_b2b_nomask ? pf_b2b-1'b1 : pf_b2b;
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end
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//-----{master -> slave}-----
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assign axi_arvalid_m_masked = axi_arvalid & ar_and;
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assign axi_rready_m_masked = axi_rready & r_and;
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assign axi_awvalid_m_masked = axi_awvalid & aw_and;
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assign axi_wvalid_m_masked = axi_wvalid & w_and;
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assign axi_bready_m_masked = axi_bready & b_and;
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//-----{slave -> master}-----
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assign axi_arready = axi_arready_s_unmasked & ar_and;
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assign axi_rvalid = axi_rvalid_s_unmasked & r_and;
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assign axi_awready = axi_awready_s_unmasked & aw_and;
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assign axi_wready = axi_wready_s_unmasked & w_and;
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assign axi_bvalid = axi_bvalid_s_unmasked & b_and;
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//ram axi
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//ar
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wire [3 :0] ram_arid ;
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wire [31:0] ram_araddr ;
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wire [7 :0] ram_arlen ;
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wire [2 :0] ram_arsize ;
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wire [1 :0] ram_arburst;
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wire [1 :0] ram_arlock ;
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wire [3 :0] ram_arcache;
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wire [2 :0] ram_arprot ;
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wire ram_arvalid;
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wire ram_arready;
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//r
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wire [3 :0] ram_rid ;
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wire [31:0] ram_rdata ;
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wire [1 :0] ram_rresp ;
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wire ram_rlast ;
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wire ram_rvalid ;
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wire ram_rready ;
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//aw
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wire [3 :0] ram_awid ;
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wire [31:0] ram_awaddr ;
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wire [7 :0] ram_awlen ;
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wire [2 :0] ram_awsize ;
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wire [1 :0] ram_awburst;
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wire [1 :0] ram_awlock ;
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wire [3 :0] ram_awcache;
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wire [2 :0] ram_awprot ;
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wire ram_awvalid;
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wire ram_awready;
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//w
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wire [3 :0] ram_wid ;
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wire [31:0] ram_wdata ;
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wire [3 :0] ram_wstrb ;
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wire ram_wlast ;
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wire ram_wvalid ;
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wire ram_wready ;
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//b
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wire [3 :0] ram_bid ;
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wire [1 :0] ram_bresp ;
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wire ram_bvalid ;
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wire ram_bready ;
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// inst ram axi
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axi_ram ram(
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.s_aclk (aclk ),
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.s_aresetn (aresetn ),
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//ar
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.s_axi_arid (ram_arid ),
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.s_axi_araddr (ram_araddr ),
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.s_axi_arlen (ram_arlen ),
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.s_axi_arsize (ram_arsize ),
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.s_axi_arburst (ram_arburst ),
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.s_axi_arvalid (ram_arvalid ),
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.s_axi_arready (ram_arready ),
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//r
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.s_axi_rid (ram_rid ),
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.s_axi_rdata (ram_rdata ),
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.s_axi_rresp (ram_rresp ),
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.s_axi_rlast (ram_rlast ),
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.s_axi_rvalid (ram_rvalid ),
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.s_axi_rready (ram_rready ),
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//aw
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.s_axi_awid (ram_awid ),
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.s_axi_awaddr (ram_awaddr ),
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.s_axi_awlen (ram_awlen ),
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.s_axi_awsize (ram_awsize ),
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.s_axi_awburst (ram_awburst ),
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.s_axi_awvalid (ram_awvalid ),
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.s_axi_awready (ram_awready ),
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//w
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.s_axi_wdata (ram_wdata ),
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.s_axi_wstrb (ram_wstrb ),
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.s_axi_wlast (ram_wlast ),
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.s_axi_wvalid (ram_wvalid ),
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.s_axi_wready (ram_wready ),
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//b
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.s_axi_bid (ram_bid ),
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.s_axi_bresp (ram_bresp ),
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.s_axi_bvalid (ram_bvalid ),
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.s_axi_bready (ram_bready )
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);
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//ar
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assign ram_arid = axi_arid ;
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assign ram_araddr = (axi_araddr[31:28] == 4'h0 ||
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axi_araddr[31:28] == 4'h1 ||
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axi_araddr[31:28] == 4'h7) ? axi_araddr :
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{12'b0, 4'hf, axi_araddr[31:28], axi_araddr[11:0]};
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assign ram_arlen = axi_arlen ;
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assign ram_arsize = axi_arsize ;
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assign ram_arburst = axi_arburst;
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assign ram_arlock = axi_arlock ;
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assign ram_arcache = axi_arcache;
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assign ram_arprot = axi_arprot ;
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assign ram_arvalid = axi_arvalid_m_masked;
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assign axi_arready_s_unmasked = ram_arready;
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//r
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assign axi_rid = axi_rvalid ? ram_rid : 4'd0 ;
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assign axi_rdata = axi_rvalid ? ram_rdata : 32'd0 ;
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assign axi_rresp = axi_rvalid ? ram_rresp : 2'd0 ;
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assign axi_rlast = axi_rvalid ? ram_rlast : 1'd0 ;
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assign axi_rvalid_s_unmasked = ram_rvalid;
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assign ram_rready = axi_rready_m_masked;
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//aw
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assign ram_awid = axi_awid ;
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assign ram_awaddr = (axi_awaddr[31:28] == 4'h0 ||
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axi_awaddr[31:28] == 4'h1 ||
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axi_awaddr[31:28] == 4'h7) ? axi_awaddr :
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{12'b0, 4'hf, axi_awaddr[31:28], axi_awaddr[11:0]};
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assign ram_awlen = axi_awlen ;
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assign ram_awsize = axi_awsize ;
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assign ram_awburst = axi_awburst;
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assign ram_awlock = axi_awlock ;
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assign ram_awcache = axi_awcache;
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assign ram_awprot = axi_awprot ;
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assign ram_awvalid = axi_awvalid_m_masked;
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assign axi_awready_s_unmasked = ram_awready;
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//w
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assign ram_wid = axi_wid ;
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assign ram_wdata = axi_wdata ;
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assign ram_wstrb = axi_wstrb ;
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assign ram_wlast = axi_wlast ;
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assign ram_wvalid = axi_wvalid_m_masked;
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assign axi_wready_s_unmasked = ram_wready ;
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//b
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assign axi_bid = axi_bvalid ? ram_bid : 4'd0 ;
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assign axi_bresp = axi_bvalid ? ram_bresp : 2'd0 ;
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assign axi_bvalid_s_unmasked = ram_bvalid ;
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assign ram_bready = axi_bready_m_masked;
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endmodule
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