[Modified] Switch soc_top&board to axi&xc7a200t
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166
lacpu/rtl/axi_wrap/axi_wrap.v
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166
lacpu/rtl/axi_wrap/axi_wrap.v
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/*------------------------------------------------------------------------------
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--------------------------------------------------------------------------------
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Copyright (c) 2016, Loongson Technology Corporation Limited.
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All rights reserved.
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Redistribution and use in source and binary forms, with or without modification,
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are permitted provided that the following conditions are met:
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1. Redistributions of source code must retain the above copyright notice, this
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list of conditions and the following disclaimer.
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2. Redistributions in binary form must reproduce the above copyright notice,
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this list of conditions and the following disclaimer in the documentation and/or
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other materials provided with the distribution.
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3. Neither the name of Loongson Technology Corporation Limited nor the names of
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its contributors may be used to endorse or promote products derived from this
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software without specific prior written permission.
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THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
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ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
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WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
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DISCLAIMED. IN NO EVENT SHALL LOONGSON TECHNOLOGY CORPORATION LIMITED BE LIABLE
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TO ANY PARTY FOR DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE
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GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
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THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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--------------------------------------------------------------------------------
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------------------------------------------------------------------------------*/
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module axi_wrap(
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input wire m_aclk,
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input wire m_aresetn,
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//ar
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input wire [3 :0] m_arid ,
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input wire [31:0] m_araddr ,
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input wire [7 :0] m_arlen ,
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input wire [2 :0] m_arsize ,
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input wire [1 :0] m_arburst,
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input wire [1 :0] m_arlock ,
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input wire [3 :0] m_arcache,
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input wire [2 :0] m_arprot ,
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input wire m_arvalid,
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output wire m_arready,
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//r
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output wire [3 :0] m_rid ,
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output wire [31:0] m_rdata ,
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output wire [1 :0] m_rresp ,
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output wire m_rlast ,
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output wire m_rvalid ,
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input wire m_rready ,
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//aw
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input wire [3 :0] m_awid ,
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input wire [31:0] m_awaddr ,
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input wire [7 :0] m_awlen ,
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input wire [2 :0] m_awsize ,
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input wire [1 :0] m_awburst,
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input wire [1 :0] m_awlock ,
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input wire [3 :0] m_awcache,
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input wire [2 :0] m_awprot ,
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input wire m_awvalid,
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output wire m_awready,
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//w
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input wire [3 :0] m_wid ,
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input wire [31:0] m_wdata ,
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input wire [3 :0] m_wstrb ,
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input wire m_wlast ,
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input wire m_wvalid ,
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output wire m_wready ,
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//b
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output wire [3 :0] m_bid ,
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output wire [1 :0] m_bresp ,
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output wire m_bvalid ,
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input wire m_bready ,
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output wire s_aclk,
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output wire s_aresetn,
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//ar
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output wire [3 :0] s_arid ,
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output wire [31:0] s_araddr ,
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output wire [7 :0] s_arlen ,
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output wire [2 :0] s_arsize ,
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output wire [1 :0] s_arburst,
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output wire [1 :0] s_arlock ,
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output wire [3 :0] s_arcache,
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output wire [2 :0] s_arprot ,
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output wire s_arvalid,
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input wire s_arready,
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//r
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input wire [3 :0] s_rid ,
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input wire [31:0] s_rdata ,
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input wire [1 :0] s_rresp ,
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input wire s_rlast ,
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input wire s_rvalid ,
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output wire s_rready ,
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//aw
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output wire [3 :0] s_awid ,
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output wire [31:0] s_awaddr ,
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output wire [7 :0] s_awlen ,
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output wire [2 :0] s_awsize ,
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output wire [1 :0] s_awburst,
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output wire [1 :0] s_awlock ,
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output wire [3 :0] s_awcache,
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output wire [2 :0] s_awprot ,
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output wire s_awvalid,
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input wire s_awready,
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//w
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output wire [3 :0] s_wid ,
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output wire [31:0] s_wdata ,
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output wire [3 :0] s_wstrb ,
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output wire s_wlast ,
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output wire s_wvalid ,
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input wire s_wready ,
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//b
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input wire [3 :0] s_bid ,
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input wire [1 :0] s_bresp ,
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input wire s_bvalid ,
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output wire s_bready
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);
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assign s_aclk = m_aclk ;
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assign s_aresetn = m_aresetn;
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//ar
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assign s_arid = m_arid ;
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assign s_araddr = m_araddr ;
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assign s_arlen = m_arlen ;
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assign s_arsize = m_arsize ;
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assign s_arburst = m_arburst;
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assign s_arlock = m_arlock ;
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assign s_arcache = m_arcache;
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assign s_arprot = m_arprot ;
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assign s_arvalid = m_arvalid;
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assign m_arready = s_arready;
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//r
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assign m_rid = m_rvalid ? s_rid : 4'd0 ;
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assign m_rdata = m_rvalid ? s_rdata : 32'd0 ;
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assign m_rresp = m_rvalid ? s_rresp : 2'd0 ;
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assign m_rlast = m_rvalid ? s_rlast : 1'd0 ;
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assign m_rvalid = s_rvalid;
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assign s_rready = m_rready;
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//aw
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assign s_awid = m_awid ;
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assign s_awaddr = m_awaddr ;
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assign s_awlen = m_awlen ;
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assign s_awsize = m_awsize ;
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assign s_awburst = m_awburst;
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assign s_awlock = m_awlock ;
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assign s_awcache = m_awcache;
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assign s_awprot = m_awprot ;
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assign s_awvalid = m_awvalid;
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assign m_awready = s_awready;
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//w
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assign s_wid = m_wid ;
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assign s_wdata = m_wdata ;
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assign s_wstrb = m_wstrb ;
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assign s_wlast = m_wlast ;
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assign s_wvalid = m_wvalid ;
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assign m_wready = s_wready ;
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//b
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assign m_bid = m_bvalid ? s_bid : 4'd0 ;
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assign m_bresp = m_bvalid ? s_bresp : 2'd0 ;
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assign m_bvalid = s_bvalid ;
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assign s_bready = m_bready ;
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endmodule
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