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[Modified] 8-stage v0.2. optimize mul stall, pass pref test but ail func test

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包焕垲
2023-07-31 16:05:29 +08:00
parent b38d04cc35
commit 9f40b5f1bb
24 changed files with 5711 additions and 234 deletions
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lacpu/rtl/xilinx_ip/data_sram_bank/summary.log Normal file
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User Configuration
--------------------------------------------------------------------------------
Algorithm : Minimum_Area
Memory Type : Single_Port_RAM
Port A Read Width : [32]
Port A Write Width : [32]
Memory Depth : [64]
----------------------------------------------------------------------------------
Block RAM resource(s) (18K BRAMs) : [1]
Block RAM resource(s) (36K BRAMs) : [0]
----------------------------------------------------------------------------------
Clock A Frequency : [100]
Port A Enable Rate : [100]
Port A Write Rate : [50]
----------------------------------------------------------------------------------
Estimated Power for IP : 3.53845 mW
----------------------------------------------------------------------------------