[Modified] 8-stage v0.2. optimize mul stall, pass pref test but ail func test
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lacpu/rtl/xilinx_ip/data_sram_bank/sim/data_bram_bank.v
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lacpu/rtl/xilinx_ip/data_sram_bank/sim/data_bram_bank.v
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// (c) Copyright 1995-2023 Xilinx, Inc. All rights reserved.
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//
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// This file contains confidential and proprietary information
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// of Xilinx, Inc. and is protected under U.S. and
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// international copyright and other intellectual property
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// laws.
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//
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// DISCLAIMER
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// This disclaimer is not a license and does not grant any
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// rights to the materials distributed herewith. Except as
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// otherwise provided in a valid license issued to you by
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// Xilinx, and to the maximum extent permitted by applicable
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// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
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// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
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// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
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// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
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// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
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// (2) Xilinx shall not be liable (whether in contract or tort,
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// including negligence, or under any other theory of
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// liability) for any loss or damage of any kind or nature
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// related to, arising under or in connection with these
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// materials, including for any direct, or any indirect,
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// special, incidental, or consequential loss or damage
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// (including loss of data, profits, goodwill, or any type of
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// loss or damage suffered as a result of any action brought
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// by a third party) even if such damage or loss was
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// reasonably foreseeable or Xilinx had been advised of the
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// possibility of the same.
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//
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// CRITICAL APPLICATIONS
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// Xilinx products are not designed or intended to be fail-
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// safe, or for use in any application requiring fail-safe
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// performance, such as life-support or safety devices or
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// systems, Class III medical devices, nuclear facilities,
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// applications related to the deployment of airbags, or any
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// other applications that could lead to death, personal
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// injury, or severe property or environmental damage
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// (individually and collectively, "Critical
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// Applications"). Customer assumes the sole risk and
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// liability of any use of Xilinx products in Critical
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// Applications, subject only to applicable laws and
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// regulations governing limitations on product liability.
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//
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// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
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// PART OF THIS FILE AT ALL TIMES.
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//
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// DO NOT MODIFY THIS FILE.
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// IP VLNV: xilinx.com:ip:blk_mem_gen:8.4
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// IP Revision: 4
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`timescale 1ns/1ps
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(* DowngradeIPIdentifiedWarnings = "yes" *)
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module data_bram_bank (
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clka,
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ena,
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wea,
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addra,
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dina,
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douta
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);
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(* X_INTERFACE_INFO = "xilinx.com:interface:bram:1.0 BRAM_PORTA CLK" *)
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input wire clka;
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(* X_INTERFACE_INFO = "xilinx.com:interface:bram:1.0 BRAM_PORTA EN" *)
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input wire ena;
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(* X_INTERFACE_INFO = "xilinx.com:interface:bram:1.0 BRAM_PORTA WE" *)
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input wire [3 : 0] wea;
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(* X_INTERFACE_INFO = "xilinx.com:interface:bram:1.0 BRAM_PORTA ADDR" *)
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input wire [5 : 0] addra;
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(* X_INTERFACE_INFO = "xilinx.com:interface:bram:1.0 BRAM_PORTA DIN" *)
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input wire [31 : 0] dina;
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(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME BRAM_PORTA, MEM_SIZE 8192, MEM_WIDTH 32, MEM_ECC NONE, MASTER_TYPE OTHER, READ_LATENCY 1" *)
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(* X_INTERFACE_INFO = "xilinx.com:interface:bram:1.0 BRAM_PORTA DOUT" *)
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output wire [31 : 0] douta;
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blk_mem_gen_v8_4_4 #(
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.C_FAMILY("artix7"),
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.C_XDEVICEFAMILY("artix7"),
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.C_ELABORATION_DIR("./"),
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.C_INTERFACE_TYPE(0),
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.C_AXI_TYPE(1),
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.C_AXI_SLAVE_TYPE(0),
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.C_USE_BRAM_BLOCK(0),
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.C_ENABLE_32BIT_ADDRESS(0),
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.C_CTRL_ECC_ALGO("NONE"),
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.C_HAS_AXI_ID(0),
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.C_AXI_ID_WIDTH(4),
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.C_MEM_TYPE(0),
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.C_BYTE_SIZE(8),
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.C_ALGORITHM(1),
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.C_PRIM_TYPE(1),
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.C_LOAD_INIT_FILE(0),
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.C_INIT_FILE_NAME("no_coe_file_loaded"),
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.C_INIT_FILE("data_bram_bank.mem"),
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.C_USE_DEFAULT_DATA(0),
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.C_DEFAULT_DATA("0"),
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.C_HAS_RSTA(0),
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.C_RST_PRIORITY_A("CE"),
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.C_RSTRAM_A(0),
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.C_INITA_VAL("0"),
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.C_HAS_ENA(1),
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.C_HAS_REGCEA(0),
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.C_USE_BYTE_WEA(1),
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.C_WEA_WIDTH(4),
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.C_WRITE_MODE_A("WRITE_FIRST"),
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.C_WRITE_WIDTH_A(32),
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.C_READ_WIDTH_A(32),
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.C_WRITE_DEPTH_A(64),
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.C_READ_DEPTH_A(64),
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.C_ADDRA_WIDTH(6),
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.C_HAS_RSTB(0),
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.C_RST_PRIORITY_B("CE"),
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.C_RSTRAM_B(0),
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.C_INITB_VAL("0"),
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.C_HAS_ENB(0),
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.C_HAS_REGCEB(0),
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.C_USE_BYTE_WEB(1),
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.C_WEB_WIDTH(4),
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.C_WRITE_MODE_B("WRITE_FIRST"),
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.C_WRITE_WIDTH_B(32),
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.C_READ_WIDTH_B(32),
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.C_WRITE_DEPTH_B(64),
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.C_READ_DEPTH_B(64),
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.C_ADDRB_WIDTH(6),
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.C_HAS_MEM_OUTPUT_REGS_A(0),
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.C_HAS_MEM_OUTPUT_REGS_B(0),
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.C_HAS_MUX_OUTPUT_REGS_A(0),
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.C_HAS_MUX_OUTPUT_REGS_B(0),
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.C_MUX_PIPELINE_STAGES(0),
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.C_HAS_SOFTECC_INPUT_REGS_A(0),
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.C_HAS_SOFTECC_OUTPUT_REGS_B(0),
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.C_USE_SOFTECC(0),
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.C_USE_ECC(0),
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.C_EN_ECC_PIPE(0),
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.C_READ_LATENCY_A(1),
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.C_READ_LATENCY_B(1),
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.C_HAS_INJECTERR(0),
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.C_SIM_COLLISION_CHECK("ALL"),
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.C_COMMON_CLK(0),
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.C_DISABLE_WARN_BHV_COLL(0),
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.C_EN_SLEEP_PIN(0),
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.C_USE_URAM(0),
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.C_EN_RDADDRA_CHG(0),
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.C_EN_RDADDRB_CHG(0),
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.C_EN_DEEPSLEEP_PIN(0),
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.C_EN_SHUTDOWN_PIN(0),
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.C_EN_SAFETY_CKT(0),
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.C_DISABLE_WARN_BHV_RANGE(0),
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.C_COUNT_36K_BRAM("0"),
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.C_COUNT_18K_BRAM("1"),
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.C_EST_POWER_SUMMARY("Estimated Power for IP : 3.53845 mW")
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) inst (
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.clka(clka),
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.rsta(1'D0),
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.ena(ena),
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.regcea(1'D0),
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.wea(wea),
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.addra(addra),
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.dina(dina),
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.douta(douta),
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.clkb(1'D0),
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.rstb(1'D0),
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.enb(1'D0),
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.regceb(1'D0),
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.web(4'B0),
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.addrb(6'B0),
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.dinb(32'B0),
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.doutb(),
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.injectsbiterr(1'D0),
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.injectdbiterr(1'D0),
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.eccpipece(1'D0),
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.sbiterr(),
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.dbiterr(),
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.rdaddrecc(),
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.sleep(1'D0),
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.deepsleep(1'D0),
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.shutdown(1'D0),
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.rsta_busy(),
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.rstb_busy(),
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.s_aclk(1'H0),
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.s_aresetn(1'D0),
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.s_axi_awid(4'B0),
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.s_axi_awaddr(32'B0),
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.s_axi_awlen(8'B0),
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.s_axi_awsize(3'B0),
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.s_axi_awburst(2'B0),
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.s_axi_awvalid(1'D0),
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.s_axi_awready(),
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.s_axi_wdata(32'B0),
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.s_axi_wstrb(4'B0),
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.s_axi_wlast(1'D0),
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.s_axi_wvalid(1'D0),
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.s_axi_wready(),
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.s_axi_bid(),
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.s_axi_bresp(),
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.s_axi_bvalid(),
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.s_axi_bready(1'D0),
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.s_axi_arid(4'B0),
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.s_axi_araddr(32'B0),
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.s_axi_arlen(8'B0),
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.s_axi_arsize(3'B0),
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.s_axi_arburst(2'B0),
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.s_axi_arvalid(1'D0),
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.s_axi_arready(),
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.s_axi_rid(),
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.s_axi_rdata(),
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.s_axi_rresp(),
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.s_axi_rlast(),
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.s_axi_rvalid(),
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.s_axi_rready(1'D0),
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.s_axi_injectsbiterr(1'D0),
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.s_axi_injectdbiterr(1'D0),
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.s_axi_sbiterr(),
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.s_axi_dbiterr(),
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.s_axi_rdaddrecc()
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);
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endmodule
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