[Modified] 8-stage v0.2. optimize mul stall, pass pref test but ail func test

lacpu/rtl/xilinx_ip/data_sram_bank/doc/blk_mem_gen_v8_4_changelog.txt

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+2019.2:
+ * Version 8.4 (Rev. 4)
+ * Feature Enhancement: Read Latency parameters exposed to IP GUI for URAM configurations
+
+2019.1.3:
+ * Version 8.4 (Rev. 3)
+ * No changes
+
+2019.1.2:
+ * Version 8.4 (Rev. 3)
+ * No changes
+
+2019.1.1:
+ * Version 8.4 (Rev. 3)
+ * No changes
+
+2019.1:
+ * Version 8.4 (Rev. 3)
+ * General: Internal device family change, no functional changes
+
+2018.3.1:
+ * Version 8.4 (Rev. 2)
+ * No changes
+
+2018.3:
+ * Version 8.4 (Rev. 2)
+ * Feature Enhancement: Read Latency Support added for URAM when selected through IP Integrator
+ * Other: Power Calculations disabled for URAM primitives in IP GUI, no functional changes
+ * Other: Internal device family change, no functional changes
+
+2018.2:
+ * Version 8.4 (Rev. 1)
+ * No changes
+
+2018.1:
+ * Version 8.4 (Rev. 1)
+ * No changes
+
+2017.4:
+ * Version 8.4 (Rev. 1)
+ * General: Write depth shown in IP GUI is now dependent on number of BRAMs available in a chosen device, no functional changes
+
+2017.3:
+ * Version 8.4
+ * General: Safety Circuit option is enabled by default if reset option in any one port is enabled
+
+2017.2:
+ * Version 8.3 (Rev. 6)
+ * No changes
+
+2017.1:
+ * Version 8.3 (Rev. 6)
+ * General: Internal device family change, no functional changes
+ * General: When common_clock is selected clkb is internally connected to clka, but the interface remains same to support the backword compatiability. User make sure of connecting the both the clocks to same clock source when in common_clock mode
+
+2016.4:
+ * Version 8.3 (Rev. 5)
+ * General: Fixes for behavioral Model issues when built-IN ECC is enabled (to be consistent with RTL)
+
+2016.3:
+ * Version 8.3 (Rev. 4)
+ * Feature Enhancement: URAM addressing updates while calling XPM_Memory when 32-bit addressing is enabled
+ * Other: Enable support for future devices
+ * Other: Source HDL files are concatenated into a single file to speed up synthesis and simulation. No changes required by the user
+
+2016.2:
+ * Version 8.3 (Rev. 3)
+ * updated the IP,not to set WRITE_DEPTH parameter to 8192 everytime when the mode is switched to BRAM_Controller
+ * Updated the IP to support the device package changes
+
+2016.1:
+ * Version 8.3 (Rev. 2)
+ * Updated the IP to deliver only verilog behavioral model
+ * Updated the IP to support UltraRAM in IP Integrator
+ * Updated the IP to support the device package changes
+
+2015.4.2:
+ * Version 8.3 (Rev. 1)
+ * No changes
+
+2015.4.1:
+ * Version 8.3 (Rev. 1)
+ * No changes
+
+2015.4:
+ * Version 8.3 (Rev. 1)
+ * Updated the IP to support the device package changes
+
+2015.3:
+ * Version 8.3
+ * IP revision number added to HDL module, library, and include file names, to support designs with both locked and upgraded IP instances
+ * New ports rsta_busy and rstb_busy are added to enable the safety circuitry to minimize the occurrence of BRAM data corruption
+ * Simulation models are delivered in VHDL only
+
+2015.2.1:
+ * Version 8.2 (Rev. 5)
+ * No changes
+
+2015.2:
+ * Version 8.2 (Rev. 5)
+ * No changes
+
+2015.1:
+ * Version 8.2 (Rev. 5)
+ * Delivering non encrypted behavioral models
+ * Supported memory depth is increased up to 1M words
+ * Added the power saving feature (RDADDRCHG) for ultrascale devices
+ * Supported devices and production status are now determined automatically, to simplify support for future devices
+
+2014.4.1:
+ * Version 8.2 (Rev. 4)
+ * Updated the IP to support the device package changes
+
+2014.4:
+ * Version 8.2 (Rev. 3)
+ * Encrypted source files are concatenated together to reduce the number of files and to reduce simulator compile time
+ * Added support for 7-series Automotive (XA) and Defense Grade (XQ) devices
+ * Internal device family change, no functional changes
+
+2014.3:
+ * Version 8.2 (Rev. 2)
+ * Fixed the Memory Resource Doubling issue in Simple Dual Port RAM when aspect ratio is used
+ * Fixed the GUI crash in Simple Dual Port RAM
+ * Added support of all write modes in Simple Dual Port RAM when ECC is not used
+ * Increased the supported depth to a maximum value of 256k
+
+2014.2:
+ * Version 8.2 (Rev. 1)
+ * Updated the GUI tool tip for Byte write enable in the page-1 of block memory generator GUI
+
+2014.1:
+ * Version 8.2
+ * Added support of the cascaded Primitives of widths 1 and 2 for ultra-scale devices
+ * Added support of the ECCPIPE register in the built-in ecc mode for ultra-scale devices
+ * Added support of the dynamic power saving for ultra-scale devices
+ * Improved timing efficiency in the IP Integrator by minimizing the use of output mux for the 7-series devices
+ * Internal device family name change, no functional changes
+
+2013.4:
+ * Version 8.1
+ * The Primitive output registers are made "ON" by default in the stand alone mode
+ * Added cascaded support for ultrascale devices to construct 64Kx1 primitive by using two 32Kx1 primitives
+ * Added support for ultrascale devices
+
+2013.3:
+ * Version 8.0 (Rev. 2)
+ * Added parameter "CTRL_ECC_ALGO" for supporting ECC in  IP Integrator.
+ * Improved GUI speed and responsivness, no functional changes
+ * Reduced synthesis and simulation warnings
+ * Added support for Cadence IES and Synopsys VCS simulators
+ * Changed the default option of ENABLE PORT TYPE to "USE_ENA_PIN"
+ * Changed BRAM Interface DIN and DOUT to match bus interface directions.
+
+2013.2:
+ * Version 8.0 (Rev. 1)
+ * No Changes
+
+2013.1:
+ * Version 8.0
+ * Native Vivado Release
+ * There have been no functional or interface changes to this IP.  The version number has changed to support unique versioning in Vivado starting with 2013.1.
+
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