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[Modified] 8-stage v0.2. optimize mul stall, pass pref test but ail func test

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包焕垲
2023-07-31 16:05:29 +08:00
parent b38d04cc35
commit 9f40b5f1bb
24 changed files with 5711 additions and 234 deletions
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lacpu/rtl/xilinx_ip/data_sram_bank/data_bram_bank.dcp
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70
lacpu/rtl/xilinx_ip/data_sram_bank/data_bram_bank.veo Normal file
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@@ -0,0 +1,70 @@
// (c) Copyright 1995-2023 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
// DO NOT MODIFY THIS FILE.
// IP VLNV: xilinx.com:ip:blk_mem_gen:8.4
// IP Revision: 4
// The following must be inserted into your Verilog file for this
// core to be instantiated. Change the instance name and port connections
// (in parentheses) to your own signal names.
//----------- Begin Cut here for INSTANTIATION Template ---// INST_TAG
data_bram_bank your_instance_name (
.clka(clka), // input wire clka
.ena(ena), // input wire ena
.wea(wea), // input wire [3 : 0] wea
.addra(addra), // input wire [5 : 0] addra
.dina(dina), // input wire [31 : 0] dina
.douta(douta) // output wire [31 : 0] douta
);
// INST_TAG_END ------ End INSTANTIATION Template ---------
// You must compile the wrapper file data_bram_bank.v when simulating
// the core, data_bram_bank. When compiling the wrapper file, be sure to
// reference the Verilog simulation library.

85
lacpu/rtl/xilinx_ip/data_sram_bank/data_bram_bank.vho Normal file
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@@ -0,0 +1,85 @@
-- (c) Copyright 1995-2023 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:ip:blk_mem_gen:8.4
-- IP Revision: 4
-- The following code must appear in the VHDL architecture header.
------------- Begin Cut here for COMPONENT Declaration ------ COMP_TAG
COMPONENT data_bram_bank
PORT (
clka : IN STD_LOGIC;
ena : IN STD_LOGIC;
wea : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
addra : IN STD_LOGIC_VECTOR(5 DOWNTO 0);
dina : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
douta : OUT STD_LOGIC_VECTOR(31 DOWNTO 0)
);
END COMPONENT;
-- COMP_TAG_END ------ End COMPONENT Declaration ------------
-- The following code must appear in the VHDL architecture
-- body. Substitute your own instance name and net names.
------------- Begin Cut here for INSTANTIATION Template ----- INST_TAG
your_instance_name : data_bram_bank
PORT MAP (
clka => clka,
ena => ena,
wea => wea,
addra => addra,
dina => dina,
douta => douta
);
-- INST_TAG_END ------ End INSTANTIATION Template ---------
-- You must compile the wrapper file data_bram_bank.vhd when simulating
-- the core, data_bram_bank. When compiling the wrapper file, be sure to
-- reference the VHDL simulation library.

16
lacpu/rtl/xilinx_ip/data_sram_bank/data_bram_bank.xci
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@@ -95,7 +95,7 @@
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_AXI_ID_WIDTH">4</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_AXI_SLAVE_TYPE">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_AXI_TYPE">1</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_BYTE_SIZE">9</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_BYTE_SIZE">8</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_COMMON_CLK">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_COUNT_18K_BRAM">1</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_COUNT_36K_BRAM">0</spirit:configurableElementValue>
@@ -149,14 +149,14 @@
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_RST_PRIORITY_B">CE</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_SIM_COLLISION_CHECK">ALL</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_BRAM_BLOCK">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_BYTE_WEA">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_BYTE_WEB">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_BYTE_WEA">1</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_BYTE_WEB">1</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_DEFAULT_DATA">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_ECC">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_SOFTECC">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_USE_URAM">0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WEA_WIDTH">1</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WEB_WIDTH">1</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WEA_WIDTH">4</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WEB_WIDTH">4</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WRITE_DEPTH_A">64</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WRITE_DEPTH_B">64</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_WRITE_MODE_A">WRITE_FIRST</spirit:configurableElementValue>
@@ -170,7 +170,7 @@
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Additional_Inputs_for_Power_Estimation">false</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Algorithm">Minimum_Area</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Assume_Synchronous_Clk">false</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Byte_Size">9</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Byte_Size">8</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CTRL_ECC_ALGO">NONE</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Coe_File">no_coe_file_loaded</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Collision_Warnings">ALL</spirit:configurableElementValue>
@@ -222,7 +222,7 @@
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Reset_Priority_B">CE</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Reset_Type">SYNC</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Use_AXI_ID">false</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Use_Byte_Write_Enable">false</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Use_Byte_Write_Enable">true</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Use_Error_Injection_Pins">false</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Use_REGCEA_Pin">false</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Use_REGCEB_Pin">false</spirit:configurableElementValue>
@@ -295,9 +295,11 @@
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AXI_SLAVE_S_AXI.PROTOCOL" xilinx:valueSource="auto"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AXI_SLAVE_S_AXI.RUSER_WIDTH" xilinx:valueSource="constant"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AXI_SLAVE_S_AXI.WUSER_WIDTH" xilinx:valueSource="constant"/>
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Byte_Size" xilinx:valueSource="user"/>
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Read_Width_A" xilinx:valueSource="user"/>
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Read_Width_B" xilinx:valueSource="user"/>
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Register_PortA_Output_of_Memory_Primitives" xilinx:valueSource="user"/>
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Use_Byte_Write_Enable" xilinx:valueSource="user"/>
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Write_Depth_A" xilinx:valueSource="user"/>
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Write_Width_A" xilinx:valueSource="user"/>
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Write_Width_B" xilinx:valueSource="user"/>

277
lacpu/rtl/xilinx_ip/data_sram_bank/data_bram_bank.xml
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@@ -1446,6 +1446,25 @@
</spirit:memoryMaps>
<spirit:model>
<spirit:views>
<spirit:view>
<spirit:name>xilinx_veriloginstantiationtemplate</spirit:name>
<spirit:displayName>Verilog Instantiation Template</spirit:displayName>
<spirit:envIdentifier>verilogSource:vivado.xilinx.com:synthesis.template</spirit:envIdentifier>
<spirit:language>verilog</spirit:language>
<spirit:fileSetRef>
<spirit:localName>xilinx_veriloginstantiationtemplate_view_fileset</spirit:localName>
</spirit:fileSetRef>
<spirit:parameters>
<spirit:parameter>
<spirit:name>GENtimestamp</spirit:name>
<spirit:value>Sun Jul 30 23:02:01 UTC 2023</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>outputProductCRC</spirit:name>
<spirit:value>9:52a41c7b</spirit:value>
</spirit:parameter>
</spirit:parameters>
</spirit:view>
<spirit:view>
<spirit:name>xilinx_vhdlsynthesis</spirit:name>
<spirit:displayName>VHDL Synthesis</spirit:displayName>
@@ -1458,11 +1477,11 @@
<spirit:parameters>
<spirit:parameter>
<spirit:name>GENtimestamp</spirit:name>
<spirit:value>Fri Jul 21 10:48:56 UTC 2023</spirit:value>
<spirit:value>Sun Jul 30 23:02:01 UTC 2023</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>outputProductCRC</spirit:name>
<spirit:value>9:7399d8a8</spirit:value>
<spirit:value>9:52a41c7b</spirit:value>
</spirit:parameter>
</spirit:parameters>
</spirit:view>
@@ -1473,7 +1492,7 @@
<spirit:parameters>
<spirit:parameter>
<spirit:name>outputProductCRC</spirit:name>
<spirit:value>9:7399d8a8</spirit:value>
<spirit:value>9:52a41c7b</spirit:value>
</spirit:parameter>
</spirit:parameters>
</spirit:view>
@@ -1489,11 +1508,86 @@
<spirit:parameters>
<spirit:parameter>
<spirit:name>GENtimestamp</spirit:name>
<spirit:value>Fri Jul 21 10:48:56 UTC 2023</spirit:value>
<spirit:value>Sun Jul 30 23:02:01 UTC 2023</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>outputProductCRC</spirit:name>
<spirit:value>9:7399d8a8</spirit:value>
<spirit:value>9:52a41c7b</spirit:value>
</spirit:parameter>
</spirit:parameters>
</spirit:view>
<spirit:view>
<spirit:name>xilinx_anylanguagebehavioralsimulation</spirit:name>
<spirit:displayName>Simulation</spirit:displayName>
<spirit:envIdentifier>:vivado.xilinx.com:simulation</spirit:envIdentifier>
<spirit:modelName>blk_mem_gen_v8_4_4</spirit:modelName>
<spirit:fileSetRef>
<spirit:localName>xilinx_anylanguagebehavioralsimulation_view_fileset</spirit:localName>
</spirit:fileSetRef>
<spirit:parameters>
<spirit:parameter>
<spirit:name>GENtimestamp</spirit:name>
<spirit:value>Sun Jul 30 23:02:01 UTC 2023</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>outputProductCRC</spirit:name>
<spirit:value>9:949760af</spirit:value>
</spirit:parameter>
</spirit:parameters>
</spirit:view>
<spirit:view>
<spirit:name>xilinx_verilogsimulationwrapper</spirit:name>
<spirit:displayName>Verilog Simulation Wrapper</spirit:displayName>
<spirit:envIdentifier>verilogSource:vivado.xilinx.com:simulation.wrapper</spirit:envIdentifier>
<spirit:language>verilog</spirit:language>
<spirit:modelName>data_bram_bank</spirit:modelName>
<spirit:fileSetRef>
<spirit:localName>xilinx_verilogsimulationwrapper_view_fileset</spirit:localName>
</spirit:fileSetRef>
<spirit:parameters>
<spirit:parameter>
<spirit:name>GENtimestamp</spirit:name>
<spirit:value>Sun Jul 30 23:02:01 UTC 2023</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>outputProductCRC</spirit:name>
<spirit:value>9:949760af</spirit:value>
</spirit:parameter>
</spirit:parameters>
</spirit:view>
<spirit:view>
<spirit:name>xilinx_project_archive</spirit:name>
<spirit:displayName>Miscellaneous</spirit:displayName>
<spirit:envIdentifier>:vivado.xilinx.com:misc.files</spirit:envIdentifier>
<spirit:fileSetRef>
<spirit:localName>xilinx_project_archive_view_fileset</spirit:localName>
</spirit:fileSetRef>
<spirit:parameters>
<spirit:parameter>
<spirit:name>GENtimestamp</spirit:name>
<spirit:value>Sun Jul 30 23:02:01 UTC 2023</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>outputProductCRC</spirit:name>
<spirit:value>9:52a41c7b</spirit:value>
</spirit:parameter>
</spirit:parameters>
</spirit:view>
<spirit:view>
<spirit:name>xilinx_versioninformation</spirit:name>
<spirit:displayName>Version Information</spirit:displayName>
<spirit:envIdentifier>:vivado.xilinx.com:docs.versioninfo</spirit:envIdentifier>
<spirit:fileSetRef>
<spirit:localName>xilinx_versioninformation_view_fileset</spirit:localName>
</spirit:fileSetRef>
<spirit:parameters>
<spirit:parameter>
<spirit:name>GENtimestamp</spirit:name>
<spirit:value>Sun Jul 30 23:02:01 UTC 2023</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>outputProductCRC</spirit:name>
<spirit:value>9:52a41c7b</spirit:value>
</spirit:parameter>
</spirit:parameters>
</spirit:view>
@@ -1507,11 +1601,11 @@
<spirit:parameters>
<spirit:parameter>
<spirit:name>GENtimestamp</spirit:name>
<spirit:value>Fri Jul 21 10:49:49 UTC 2023</spirit:value>
<spirit:value>Sun Jul 30 23:02:57 UTC 2023</spirit:value>
</spirit:parameter>
<spirit:parameter>
<spirit:name>outputProductCRC</spirit:name>
<spirit:value>9:7399d8a8</spirit:value>
<spirit:value>9:52a41c7b</spirit:value>
</spirit:parameter>
</spirit:parameters>
</spirit:view>
@@ -1525,6 +1619,7 @@
<spirit:wireTypeDef>
<spirit:typeName>std_logic</spirit:typeName>
<spirit:viewNameRef>xilinx_vhdlsynthesis</spirit:viewNameRef>
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
<spirit:driver>
@@ -1547,6 +1642,7 @@
<spirit:wireTypeDef>
<spirit:typeName>std_logic</spirit:typeName>
<spirit:viewNameRef>xilinx_vhdlsynthesis</spirit:viewNameRef>
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
<spirit:driver>
@@ -1569,6 +1665,7 @@
<spirit:wireTypeDef>
<spirit:typeName>std_logic</spirit:typeName>
<spirit:viewNameRef>xilinx_vhdlsynthesis</spirit:viewNameRef>
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
<spirit:driver>
@@ -1591,6 +1688,7 @@
<spirit:wireTypeDef>
<spirit:typeName>std_logic</spirit:typeName>
<spirit:viewNameRef>xilinx_vhdlsynthesis</spirit:viewNameRef>
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
<spirit:driver>
@@ -1610,13 +1708,14 @@
<spirit:wire>
<spirit:direction>in</spirit:direction>
<spirit:vector>
<spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency="spirit:decode(id(&apos;MODELPARAM_VALUE.C_WEA_WIDTH&apos;))-1">0</spirit:left>
<spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency="spirit:decode(id(&apos;MODELPARAM_VALUE.C_WEA_WIDTH&apos;))-1">3</spirit:left>
<spirit:right spirit:format="long">0</spirit:right>
</spirit:vector>
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>std_logic_vector</spirit:typeName>
<spirit:viewNameRef>xilinx_vhdlsynthesis</spirit:viewNameRef>
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
<spirit:driver>
@@ -1643,6 +1742,7 @@
<spirit:wireTypeDef>
<spirit:typeName>std_logic_vector</spirit:typeName>
<spirit:viewNameRef>xilinx_vhdlsynthesis</spirit:viewNameRef>
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
<spirit:driver>
@@ -1669,6 +1769,7 @@
<spirit:wireTypeDef>
<spirit:typeName>std_logic_vector</spirit:typeName>
<spirit:viewNameRef>xilinx_vhdlsynthesis</spirit:viewNameRef>
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
<spirit:driver>
@@ -1695,6 +1796,7 @@
<spirit:wireTypeDef>
<spirit:typeName>std_logic_vector</spirit:typeName>
<spirit:viewNameRef>xilinx_vhdlsynthesis</spirit:viewNameRef>
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
</spirit:wire>
@@ -1714,6 +1816,7 @@
<spirit:wireTypeDef>
<spirit:typeName>std_logic</spirit:typeName>
<spirit:viewNameRef>xilinx_vhdlsynthesis</spirit:viewNameRef>
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
<spirit:driver>
@@ -1736,6 +1839,7 @@
<spirit:wireTypeDef>
<spirit:typeName>std_logic</spirit:typeName>
<spirit:viewNameRef>xilinx_vhdlsynthesis</spirit:viewNameRef>
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
<spirit:driver>
@@ -1758,6 +1862,7 @@
<spirit:wireTypeDef>
<spirit:typeName>std_logic</spirit:typeName>
<spirit:viewNameRef>xilinx_vhdlsynthesis</spirit:viewNameRef>
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
<spirit:driver>
@@ -1780,6 +1885,7 @@
<spirit:wireTypeDef>
<spirit:typeName>std_logic</spirit:typeName>
<spirit:viewNameRef>xilinx_vhdlsynthesis</spirit:viewNameRef>
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
<spirit:driver>
@@ -1799,13 +1905,14 @@
<spirit:wire>
<spirit:direction>in</spirit:direction>
<spirit:vector>
<spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency="spirit:decode(id(&apos;MODELPARAM_VALUE.C_WEB_WIDTH&apos;))-1">0</spirit:left>
<spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency="spirit:decode(id(&apos;MODELPARAM_VALUE.C_WEB_WIDTH&apos;))-1">3</spirit:left>
<spirit:right spirit:format="long">0</spirit:right>
</spirit:vector>
<spirit:wireTypeDefs>
<spirit:wireTypeDef>
<spirit:typeName>std_logic_vector</spirit:typeName>
<spirit:viewNameRef>xilinx_vhdlsynthesis</spirit:viewNameRef>
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
<spirit:driver>
@@ -1832,6 +1939,7 @@
<spirit:wireTypeDef>
<spirit:typeName>std_logic_vector</spirit:typeName>
<spirit:viewNameRef>xilinx_vhdlsynthesis</spirit:viewNameRef>
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
</spirit:wireTypeDef>
</spirit:wireTypeDefs>
<spirit:driver>
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<spirit:typeName>std_logic_vector</spirit:typeName>
<spirit:viewNameRef>xilinx_vhdlsynthesis</spirit:viewNameRef>
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
</spirit:wireTypeDef>
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@@ -1884,6 +1993,7 @@
<spirit:wireTypeDef>
<spirit:typeName>std_logic_vector</spirit:typeName>
<spirit:viewNameRef>xilinx_vhdlsynthesis</spirit:viewNameRef>
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
</spirit:wireTypeDef>
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@@ -1903,6 +2013,7 @@
<spirit:wireTypeDef>
<spirit:typeName>std_logic</spirit:typeName>
<spirit:viewNameRef>xilinx_vhdlsynthesis</spirit:viewNameRef>
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
</spirit:wireTypeDef>
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<spirit:driver>
@@ -1925,6 +2036,7 @@
<spirit:wireTypeDef>
<spirit:typeName>std_logic</spirit:typeName>
<spirit:viewNameRef>xilinx_vhdlsynthesis</spirit:viewNameRef>
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
</spirit:wireTypeDef>
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<spirit:driver>
@@ -1947,6 +2059,7 @@
<spirit:wireTypeDef>
<spirit:typeName>std_logic</spirit:typeName>
<spirit:viewNameRef>xilinx_vhdlsynthesis</spirit:viewNameRef>
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
</spirit:wireTypeDef>
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@@ -1969,6 +2082,7 @@
<spirit:wireTypeDef>
<spirit:typeName>std_logic</spirit:typeName>
<spirit:viewNameRef>xilinx_vhdlsynthesis</spirit:viewNameRef>
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
</spirit:wireTypeDef>
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@@ -1988,6 +2102,7 @@
<spirit:wireTypeDef>
<spirit:typeName>std_logic</spirit:typeName>
<spirit:viewNameRef>xilinx_vhdlsynthesis</spirit:viewNameRef>
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
</spirit:wireTypeDef>
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@@ -2011,6 +2126,7 @@
<spirit:wireTypeDef>
<spirit:typeName>std_logic_vector</spirit:typeName>
<spirit:viewNameRef>xilinx_vhdlsynthesis</spirit:viewNameRef>
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
</spirit:wireTypeDef>
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@@ -2030,6 +2146,7 @@
<spirit:wireTypeDef>
<spirit:typeName>std_logic</spirit:typeName>
<spirit:viewNameRef>xilinx_vhdlsynthesis</spirit:viewNameRef>
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
</spirit:wireTypeDef>
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@@ -2052,6 +2169,7 @@
<spirit:wireTypeDef>
<spirit:typeName>std_logic</spirit:typeName>
<spirit:viewNameRef>xilinx_vhdlsynthesis</spirit:viewNameRef>
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
</spirit:wireTypeDef>
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@@ -2074,6 +2192,7 @@
<spirit:wireTypeDef>
<spirit:typeName>std_logic</spirit:typeName>
<spirit:viewNameRef>xilinx_vhdlsynthesis</spirit:viewNameRef>
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
</spirit:wireTypeDef>
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@@ -2096,6 +2215,7 @@
<spirit:wireTypeDef>
<spirit:typeName>std_logic</spirit:typeName>
<spirit:viewNameRef>xilinx_vhdlsynthesis</spirit:viewNameRef>
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
</spirit:wireTypeDef>
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@@ -2115,6 +2235,7 @@
<spirit:wireTypeDef>
<spirit:typeName>std_logic</spirit:typeName>
<spirit:viewNameRef>xilinx_vhdlsynthesis</spirit:viewNameRef>
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
</spirit:wireTypeDef>
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@@ -2134,6 +2255,7 @@
<spirit:wireTypeDef>
<spirit:typeName>std_logic</spirit:typeName>
<spirit:viewNameRef>xilinx_vhdlsynthesis</spirit:viewNameRef>
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
</spirit:wireTypeDef>
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@@ -2156,6 +2278,7 @@
<spirit:wireTypeDef>
<spirit:typeName>std_logic</spirit:typeName>
<spirit:viewNameRef>xilinx_vhdlsynthesis</spirit:viewNameRef>
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
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@@ -2182,6 +2305,7 @@
<spirit:wireTypeDef>
<spirit:typeName>std_logic_vector</spirit:typeName>
<spirit:viewNameRef>xilinx_vhdlsynthesis</spirit:viewNameRef>
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
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@@ -2208,6 +2332,7 @@
<spirit:wireTypeDef>
<spirit:typeName>std_logic_vector</spirit:typeName>
<spirit:viewNameRef>xilinx_vhdlsynthesis</spirit:viewNameRef>
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
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@@ -2234,6 +2359,7 @@
<spirit:wireTypeDef>
<spirit:typeName>std_logic_vector</spirit:typeName>
<spirit:viewNameRef>xilinx_vhdlsynthesis</spirit:viewNameRef>
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
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@@ -2260,6 +2386,7 @@
<spirit:wireTypeDef>
<spirit:typeName>std_logic_vector</spirit:typeName>
<spirit:viewNameRef>xilinx_vhdlsynthesis</spirit:viewNameRef>
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
</spirit:wireTypeDef>
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@@ -2286,6 +2413,7 @@
<spirit:wireTypeDef>
<spirit:typeName>std_logic_vector</spirit:typeName>
<spirit:viewNameRef>xilinx_vhdlsynthesis</spirit:viewNameRef>
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
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@@ -2308,6 +2436,7 @@
<spirit:wireTypeDef>
<spirit:typeName>std_logic</spirit:typeName>
<spirit:viewNameRef>xilinx_vhdlsynthesis</spirit:viewNameRef>
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
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@@ -2330,6 +2459,7 @@
<spirit:wireTypeDef>
<spirit:typeName>std_logic</spirit:typeName>
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<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
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@@ -2353,6 +2483,7 @@
<spirit:wireTypeDef>
<spirit:typeName>std_logic_vector</spirit:typeName>
<spirit:viewNameRef>xilinx_vhdlsynthesis</spirit:viewNameRef>
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
</spirit:wireTypeDef>
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<spirit:driver>
@@ -2372,13 +2503,14 @@
<spirit:wire>
<spirit:direction>in</spirit:direction>
<spirit:vector>
<spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency="spirit:decode(id(&apos;MODELPARAM_VALUE.C_WEA_WIDTH&apos;))-1">0</spirit:left>
<spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency="spirit:decode(id(&apos;MODELPARAM_VALUE.C_WEA_WIDTH&apos;))-1">3</spirit:left>
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<spirit:wireTypeDef>
<spirit:typeName>std_logic_vector</spirit:typeName>
<spirit:viewNameRef>xilinx_vhdlsynthesis</spirit:viewNameRef>
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
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<spirit:wireTypeDef>
<spirit:typeName>std_logic</spirit:typeName>
<spirit:viewNameRef>xilinx_vhdlsynthesis</spirit:viewNameRef>
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
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@@ -2423,6 +2556,7 @@
<spirit:wireTypeDef>
<spirit:typeName>std_logic</spirit:typeName>
<spirit:viewNameRef>xilinx_vhdlsynthesis</spirit:viewNameRef>
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
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@@ -2445,6 +2579,7 @@
<spirit:wireTypeDef>
<spirit:typeName>std_logic</spirit:typeName>
<spirit:viewNameRef>xilinx_vhdlsynthesis</spirit:viewNameRef>
<spirit:viewNameRef>xilinx_anylanguagebehavioralsimulation</spirit:viewNameRef>
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@@ -2468,6 +2603,7 @@
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<spirit:typeName>std_logic_vector</spirit:typeName>
<spirit:viewNameRef>xilinx_vhdlsynthesis</spirit:viewNameRef>
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@@ -2491,6 +2627,7 @@
<spirit:wireTypeDef>
<spirit:typeName>std_logic_vector</spirit:typeName>
<spirit:viewNameRef>xilinx_vhdlsynthesis</spirit:viewNameRef>
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@@ -2510,6 +2647,7 @@
<spirit:wireTypeDef>
<spirit:typeName>std_logic</spirit:typeName>
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@@ -2529,6 +2667,7 @@
<spirit:wireTypeDef>
<spirit:typeName>std_logic</spirit:typeName>
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@@ -2555,6 +2694,7 @@
<spirit:wireTypeDef>
<spirit:typeName>std_logic_vector</spirit:typeName>
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<spirit:typeName>std_logic_vector</spirit:typeName>
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<spirit:typeName>std_logic</spirit:typeName>
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@@ -2726,6 +2872,7 @@
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</xilinx:parameterInfo>
</spirit:vendorExtensions>
@@ -3669,7 +3866,7 @@
</spirit:parameter>
<spirit:parameter>
<spirit:name>Use_Byte_Write_Enable</spirit:name>
<spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.Use_Byte_Write_Enable" spirit:order="15">false</spirit:value>
<spirit:value spirit:format="bool" spirit:resolve="user" spirit:id="PARAM_VALUE.Use_Byte_Write_Enable" spirit:order="15">true</spirit:value>
<spirit:vendorExtensions>
<xilinx:parameterInfo>
<xilinx:enablement>
@@ -3680,11 +3877,11 @@
</spirit:parameter>
<spirit:parameter>
<spirit:name>Byte_Size</spirit:name>
<spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.Byte_Size" spirit:choiceRef="choice_list_89a27b2f" spirit:order="16">9</spirit:value>
<spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.Byte_Size" spirit:choiceRef="choice_list_89a27b2f" spirit:order="16">8</spirit:value>
<spirit:vendorExtensions>
<xilinx:parameterInfo>
<xilinx:enablement>
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.Byte_Size">false</xilinx:isEnabled>
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:id="PARAM_ENABLEMENT.Byte_Size">true</xilinx:isEnabled>
</xilinx:enablement>
</xilinx:parameterInfo>
</spirit:vendorExtensions>
@@ -3724,7 +3921,7 @@
</spirit:parameter>
<spirit:parameter>
<spirit:name>Write_Width_A</spirit:name>
<spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.Write_Width_A" spirit:order="18" spirit:minimum="1" spirit:maximum="4608" spirit:rangeType="long">32</spirit:value>
<spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.Write_Width_A" spirit:order="18" spirit:minimum="8" spirit:maximum="4096" spirit:rangeType="long">32</spirit:value>
<spirit:vendorExtensions>
<xilinx:parameterInfo>
<xilinx:enablement>
@@ -3746,7 +3943,7 @@
</spirit:parameter>
<spirit:parameter>
<spirit:name>Read_Width_A</spirit:name>
<spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.Read_Width_A" spirit:choiceRef="choice_list_784e1e2a" spirit:order="22">32</spirit:value>
<spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.Read_Width_A" spirit:choiceRef="choice_list_9ad8826b" spirit:order="22">32</spirit:value>
<spirit:vendorExtensions>
<xilinx:parameterInfo>
<xilinx:enablement>
@@ -3757,7 +3954,7 @@
</spirit:parameter>
<spirit:parameter>
<spirit:name>Operating_Mode_A</spirit:name>
<spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.Operating_Mode_A" spirit:choiceRef="choice_pairs_07c32259" spirit:order="23">WRITE_FIRST</spirit:value>
<spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.Operating_Mode_A" spirit:choiceRef="choice_pairs_246d8066" spirit:order="23">WRITE_FIRST</spirit:value>
<spirit:vendorExtensions>
<xilinx:parameterInfo>
<xilinx:enablement>
@@ -3779,7 +3976,7 @@
</spirit:parameter>
<spirit:parameter>
<spirit:name>Write_Width_B</spirit:name>
<spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.Write_Width_B" spirit:choiceRef="choice_list_784e1e2a" spirit:order="25">32</spirit:value>
<spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.Write_Width_B" spirit:choiceRef="choice_list_9ad8826b" spirit:order="25">32</spirit:value>
<spirit:vendorExtensions>
<xilinx:parameterInfo>
<xilinx:enablement>
@@ -3790,7 +3987,7 @@
</spirit:parameter>
<spirit:parameter>
<spirit:name>Read_Width_B</spirit:name>
<spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.Read_Width_B" spirit:choiceRef="choice_list_784e1e2a" spirit:order="26">32</spirit:value>
<spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.Read_Width_B" spirit:choiceRef="choice_list_9ad8826b" spirit:order="26">32</spirit:value>
<spirit:vendorExtensions>
<xilinx:parameterInfo>
<xilinx:enablement>
@@ -3801,7 +3998,7 @@
</spirit:parameter>
<spirit:parameter>
<spirit:name>Operating_Mode_B</spirit:name>
<spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.Operating_Mode_B" spirit:choiceRef="choice_pairs_07c32259" spirit:order="27">WRITE_FIRST</spirit:value>
<spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.Operating_Mode_B" spirit:choiceRef="choice_pairs_246d8066" spirit:order="27">WRITE_FIRST</spirit:value>
<spirit:vendorExtensions>
<xilinx:parameterInfo>
<xilinx:enablement>
@@ -4282,9 +4479,11 @@
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AXI_SLAVE_S_AXI.PROTOCOL" xilinx:valueSource="auto"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AXI_SLAVE_S_AXI.RUSER_WIDTH" xilinx:valueSource="constant"/>
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AXI_SLAVE_S_AXI.WUSER_WIDTH" xilinx:valueSource="constant"/>
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Byte_Size" xilinx:valueSource="user"/>
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Read_Width_A" xilinx:valueSource="user"/>
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Read_Width_B" xilinx:valueSource="user"/>
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Register_PortA_Output_of_Memory_Primitives" xilinx:valueSource="user"/>
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Use_Byte_Write_Enable" xilinx:valueSource="user"/>
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Write_Depth_A" xilinx:valueSource="user"/>
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Write_Width_A" xilinx:valueSource="user"/>
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Write_Width_B" xilinx:valueSource="user"/>

58
lacpu/rtl/xilinx_ip/data_sram_bank/data_bram_bank_sim_netlist.v
View File

@@ -1,7 +1,7 @@
// Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2019.2 (win64) Build 2708876 Wed Nov 6 21:40:23 MST 2019
// Date : Fri Jul 21 18:49:49 2023
// Date : Mon Jul 31 07:02:57 2023
// Host : BHKLaptop running 64-bit major release (build 9200)
// Command : write_verilog -force -mode funcsim
// C:/Users/Unbal/Desktop/LoongArch/neulacpu/lacpu/rtl/xilinx_ip/data_sram_bank/data_bram_bank_sim_netlist.v
@@ -23,7 +23,7 @@ module data_bram_bank
douta);
(* x_interface_info = "xilinx.com:interface:bram:1.0 BRAM_PORTA CLK" *) (* x_interface_parameter = "XIL_INTERFACENAME BRAM_PORTA, MEM_SIZE 8192, MEM_WIDTH 32, MEM_ECC NONE, MASTER_TYPE OTHER, READ_LATENCY 1" *) input clka;
(* x_interface_info = "xilinx.com:interface:bram:1.0 BRAM_PORTA EN" *) input ena;
(* x_interface_info = "xilinx.com:interface:bram:1.0 BRAM_PORTA WE" *) input [0:0]wea;
(* x_interface_info = "xilinx.com:interface:bram:1.0 BRAM_PORTA WE" *) input [3:0]wea;
(* x_interface_info = "xilinx.com:interface:bram:1.0 BRAM_PORTA ADDR" *) input [5:0]addra;
(* x_interface_info = "xilinx.com:interface:bram:1.0 BRAM_PORTA DIN" *) input [31:0]dina;
(* x_interface_info = "xilinx.com:interface:bram:1.0 BRAM_PORTA DOUT" *) output [31:0]douta;
@@ -33,7 +33,7 @@ module data_bram_bank
wire [31:0]dina;
wire [31:0]douta;
wire ena;
wire [0:0]wea;
wire [3:0]wea;
wire NLW_U0_dbiterr_UNCONNECTED;
wire NLW_U0_rsta_busy_UNCONNECTED;
wire NLW_U0_rstb_busy_UNCONNECTED;
@@ -61,7 +61,7 @@ module data_bram_bank
(* C_AXI_ID_WIDTH = "4" *)
(* C_AXI_SLAVE_TYPE = "0" *)
(* C_AXI_TYPE = "1" *)
(* C_BYTE_SIZE = "9" *)
(* C_BYTE_SIZE = "8" *)
(* C_COMMON_CLK = "0" *)
(* C_COUNT_18K_BRAM = "1" *)
(* C_COUNT_36K_BRAM = "0" *)
@@ -115,14 +115,14 @@ module data_bram_bank
(* C_RST_PRIORITY_B = "CE" *)
(* C_SIM_COLLISION_CHECK = "ALL" *)
(* C_USE_BRAM_BLOCK = "0" *)
(* C_USE_BYTE_WEA = "0" *)
(* C_USE_BYTE_WEB = "0" *)
(* C_USE_BYTE_WEA = "1" *)
(* C_USE_BYTE_WEB = "1" *)
(* C_USE_DEFAULT_DATA = "0" *)
(* C_USE_ECC = "0" *)
(* C_USE_SOFTECC = "0" *)
(* C_USE_URAM = "0" *)
(* C_WEA_WIDTH = "1" *)
(* C_WEB_WIDTH = "1" *)
(* C_WEA_WIDTH = "4" *)
(* C_WEB_WIDTH = "4" *)
(* C_WRITE_DEPTH_A = "64" *)
(* C_WRITE_DEPTH_B = "64" *)
(* C_WRITE_MODE_A = "WRITE_FIRST" *)
@@ -188,13 +188,13 @@ module data_bram_bank
.s_axi_wdata({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
.s_axi_wlast(1'b0),
.s_axi_wready(NLW_U0_s_axi_wready_UNCONNECTED),
.s_axi_wstrb(1'b0),
.s_axi_wstrb({1'b0,1'b0,1'b0,1'b0}),
.s_axi_wvalid(1'b0),
.sbiterr(NLW_U0_sbiterr_UNCONNECTED),
.shutdown(1'b0),
.sleep(1'b0),
.wea(wea),
.web(1'b0));
.web({1'b0,1'b0,1'b0,1'b0}));
endmodule
(* ORIG_REF_NAME = "blk_mem_gen_generic_cstr" *)
@@ -210,14 +210,14 @@ module data_bram_bank_blk_mem_gen_generic_cstr
input ena;
input [5:0]addra;
input [31:0]dina;
input [0:0]wea;
input [3:0]wea;
wire [5:0]addra;
wire clka;
wire [31:0]dina;
wire [31:0]douta;
wire ena;
wire [0:0]wea;
wire [3:0]wea;
data_bram_bank_blk_mem_gen_prim_width \ramloop[0].ram.r
(.addra(addra),
@@ -241,14 +241,14 @@ module data_bram_bank_blk_mem_gen_prim_width
input ena;
input [5:0]addra;
input [31:0]dina;
input [0:0]wea;
input [3:0]wea;
wire [5:0]addra;
wire clka;
wire [31:0]dina;
wire [31:0]douta;
wire ena;
wire [0:0]wea;
wire [3:0]wea;
data_bram_bank_blk_mem_gen_prim_wrapper \prim_noinit.ram
(.addra(addra),
@@ -272,7 +272,7 @@ module data_bram_bank_blk_mem_gen_prim_wrapper
input ena;
input [5:0]addra;
input [31:0]dina;
input [0:0]wea;
input [3:0]wea;
wire \DEVICE_7SERIES.NO_BMM_INFO.SP.WIDE_PRIM18.ram_n_32 ;
wire \DEVICE_7SERIES.NO_BMM_INFO.SP.WIDE_PRIM18.ram_n_33 ;
@@ -283,7 +283,7 @@ module data_bram_bank_blk_mem_gen_prim_wrapper
wire [31:0]dina;
wire [31:0]douta;
wire ena;
wire [0:0]wea;
wire [3:0]wea;
(* box_type = "PRIMITIVE" *)
RAMB18E1 #(
@@ -407,8 +407,8 @@ module data_bram_bank_blk_mem_gen_prim_wrapper
.RSTRAMB(1'b0),
.RSTREGARSTREG(1'b0),
.RSTREGB(1'b0),
.WEA({wea,wea}),
.WEBWE({1'b0,1'b0,wea,wea}));
.WEA(wea[1:0]),
.WEBWE({1'b0,1'b0,wea[3:2]}));
endmodule
(* ORIG_REF_NAME = "blk_mem_gen_top" *)
@@ -424,14 +424,14 @@ module data_bram_bank_blk_mem_gen_top
input ena;
input [5:0]addra;
input [31:0]dina;
input [0:0]wea;
input [3:0]wea;
wire [5:0]addra;
wire clka;
wire [31:0]dina;
wire [31:0]douta;
wire ena;
wire [0:0]wea;
wire [3:0]wea;
data_bram_bank_blk_mem_gen_generic_cstr \valid.cstr
(.addra(addra),
@@ -444,7 +444,7 @@ endmodule
(* C_ADDRA_WIDTH = "6" *) (* C_ADDRB_WIDTH = "6" *) (* C_ALGORITHM = "1" *)
(* C_AXI_ID_WIDTH = "4" *) (* C_AXI_SLAVE_TYPE = "0" *) (* C_AXI_TYPE = "1" *)
(* C_BYTE_SIZE = "9" *) (* C_COMMON_CLK = "0" *) (* C_COUNT_18K_BRAM = "1" *)
(* C_BYTE_SIZE = "8" *) (* C_COMMON_CLK = "0" *) (* C_COUNT_18K_BRAM = "1" *)
(* C_COUNT_36K_BRAM = "0" *) (* C_CTRL_ECC_ALGO = "NONE" *) (* C_DEFAULT_DATA = "0" *)
(* C_DISABLE_WARN_BHV_COLL = "0" *) (* C_DISABLE_WARN_BHV_RANGE = "0" *) (* C_ELABORATION_DIR = "./" *)
(* C_ENABLE_32BIT_ADDRESS = "0" *) (* C_EN_DEEPSLEEP_PIN = "0" *) (* C_EN_ECC_PIPE = "0" *)
@@ -462,9 +462,9 @@ endmodule
(* C_READ_LATENCY_B = "1" *) (* C_READ_WIDTH_A = "32" *) (* C_READ_WIDTH_B = "32" *)
(* C_RSTRAM_A = "0" *) (* C_RSTRAM_B = "0" *) (* C_RST_PRIORITY_A = "CE" *)
(* C_RST_PRIORITY_B = "CE" *) (* C_SIM_COLLISION_CHECK = "ALL" *) (* C_USE_BRAM_BLOCK = "0" *)
(* C_USE_BYTE_WEA = "0" *) (* C_USE_BYTE_WEB = "0" *) (* C_USE_DEFAULT_DATA = "0" *)
(* C_USE_BYTE_WEA = "1" *) (* C_USE_BYTE_WEB = "1" *) (* C_USE_DEFAULT_DATA = "0" *)
(* C_USE_ECC = "0" *) (* C_USE_SOFTECC = "0" *) (* C_USE_URAM = "0" *)
(* C_WEA_WIDTH = "1" *) (* C_WEB_WIDTH = "1" *) (* C_WRITE_DEPTH_A = "64" *)
(* C_WEA_WIDTH = "4" *) (* C_WEB_WIDTH = "4" *) (* C_WRITE_DEPTH_A = "64" *)
(* C_WRITE_DEPTH_B = "64" *) (* C_WRITE_MODE_A = "WRITE_FIRST" *) (* C_WRITE_MODE_B = "WRITE_FIRST" *)
(* C_WRITE_WIDTH_A = "32" *) (* C_WRITE_WIDTH_B = "32" *) (* C_XDEVICEFAMILY = "artix7" *)
(* ORIG_REF_NAME = "blk_mem_gen_v8_4_4" *) (* downgradeipidentifiedwarnings = "yes" *)
@@ -536,7 +536,7 @@ module data_bram_bank_blk_mem_gen_v8_4_4
input rsta;
input ena;
input regcea;
input [0:0]wea;
input [3:0]wea;
input [5:0]addra;
input [31:0]dina;
output [31:0]douta;
@@ -544,7 +544,7 @@ module data_bram_bank_blk_mem_gen_v8_4_4
input rstb;
input enb;
input regceb;
input [0:0]web;
input [3:0]web;
input [5:0]addrb;
input [31:0]dinb;
output [31:0]doutb;
@@ -569,7 +569,7 @@ module data_bram_bank_blk_mem_gen_v8_4_4
input s_axi_awvalid;
output s_axi_awready;
input [31:0]s_axi_wdata;
input [0:0]s_axi_wstrb;
input [3:0]s_axi_wstrb;
input s_axi_wlast;
input s_axi_wvalid;
output s_axi_wready;
@@ -602,7 +602,7 @@ module data_bram_bank_blk_mem_gen_v8_4_4
wire [31:0]dina;
wire [31:0]douta;
wire ena;
wire [0:0]wea;
wire [3:0]wea;
assign dbiterr = \<const0> ;
assign doutb[31] = \<const0> ;
@@ -728,14 +728,14 @@ module data_bram_bank_blk_mem_gen_v8_4_4_synth
input ena;
input [5:0]addra;
input [31:0]dina;
input [0:0]wea;
input [3:0]wea;
wire [5:0]addra;
wire clka;
wire [31:0]dina;
wire [31:0]douta;
wire ena;
wire [0:0]wea;
wire [3:0]wea;
data_bram_bank_blk_mem_gen_top \gnbram.gnativebmg.native_blk_mem_gen
(.addra(addra),

62
lacpu/rtl/xilinx_ip/data_sram_bank/data_bram_bank_sim_netlist.vhdl
View File

@@ -1,7 +1,7 @@
-- Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2019.2 (win64) Build 2708876 Wed Nov 6 21:40:23 MST 2019
-- Date : Fri Jul 21 18:49:49 2023
-- Date : Mon Jul 31 07:02:57 2023
-- Host : BHKLaptop running 64-bit major release (build 9200)
-- Command : write_vhdl -force -mode funcsim
-- C:/Users/Unbal/Desktop/LoongArch/neulacpu/lacpu/rtl/xilinx_ip/data_sram_bank/data_bram_bank_sim_netlist.vhdl
@@ -21,7 +21,7 @@ entity data_bram_bank_blk_mem_gen_prim_wrapper is
ena : in STD_LOGIC;
addra : in STD_LOGIC_VECTOR ( 5 downto 0 );
dina : in STD_LOGIC_VECTOR ( 31 downto 0 );
wea : in STD_LOGIC_VECTOR ( 0 to 0 )
wea : in STD_LOGIC_VECTOR ( 3 downto 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of data_bram_bank_blk_mem_gen_prim_wrapper : entity is "blk_mem_gen_prim_wrapper";
@@ -164,11 +164,9 @@ begin
RSTRAMB => '0',
RSTREGARSTREG => '0',
RSTREGB => '0',
WEA(1) => wea(0),
WEA(0) => wea(0),
WEA(1 downto 0) => wea(1 downto 0),
WEBWE(3 downto 2) => B"00",
WEBWE(1) => wea(0),
WEBWE(0) => wea(0)
WEBWE(1 downto 0) => wea(3 downto 2)
);
end STRUCTURE;
library IEEE;
@@ -182,7 +180,7 @@ entity data_bram_bank_blk_mem_gen_prim_width is
ena : in STD_LOGIC;
addra : in STD_LOGIC_VECTOR ( 5 downto 0 );
dina : in STD_LOGIC_VECTOR ( 31 downto 0 );
wea : in STD_LOGIC_VECTOR ( 0 to 0 )
wea : in STD_LOGIC_VECTOR ( 3 downto 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of data_bram_bank_blk_mem_gen_prim_width : entity is "blk_mem_gen_prim_width";
@@ -197,7 +195,7 @@ begin
dina(31 downto 0) => dina(31 downto 0),
douta(31 downto 0) => douta(31 downto 0),
ena => ena,
wea(0) => wea(0)
wea(3 downto 0) => wea(3 downto 0)
);
end STRUCTURE;
library IEEE;
@@ -211,7 +209,7 @@ entity data_bram_bank_blk_mem_gen_generic_cstr is
ena : in STD_LOGIC;
addra : in STD_LOGIC_VECTOR ( 5 downto 0 );
dina : in STD_LOGIC_VECTOR ( 31 downto 0 );
wea : in STD_LOGIC_VECTOR ( 0 to 0 )
wea : in STD_LOGIC_VECTOR ( 3 downto 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of data_bram_bank_blk_mem_gen_generic_cstr : entity is "blk_mem_gen_generic_cstr";
@@ -226,7 +224,7 @@ begin
dina(31 downto 0) => dina(31 downto 0),
douta(31 downto 0) => douta(31 downto 0),
ena => ena,
wea(0) => wea(0)
wea(3 downto 0) => wea(3 downto 0)
);
end STRUCTURE;
library IEEE;
@@ -240,7 +238,7 @@ entity data_bram_bank_blk_mem_gen_top is
ena : in STD_LOGIC;
addra : in STD_LOGIC_VECTOR ( 5 downto 0 );
dina : in STD_LOGIC_VECTOR ( 31 downto 0 );
wea : in STD_LOGIC_VECTOR ( 0 to 0 )
wea : in STD_LOGIC_VECTOR ( 3 downto 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of data_bram_bank_blk_mem_gen_top : entity is "blk_mem_gen_top";
@@ -255,7 +253,7 @@ begin
dina(31 downto 0) => dina(31 downto 0),
douta(31 downto 0) => douta(31 downto 0),
ena => ena,
wea(0) => wea(0)
wea(3 downto 0) => wea(3 downto 0)
);
end STRUCTURE;
library IEEE;
@@ -269,7 +267,7 @@ entity data_bram_bank_blk_mem_gen_v8_4_4_synth is
ena : in STD_LOGIC;
addra : in STD_LOGIC_VECTOR ( 5 downto 0 );
dina : in STD_LOGIC_VECTOR ( 31 downto 0 );
wea : in STD_LOGIC_VECTOR ( 0 to 0 )
wea : in STD_LOGIC_VECTOR ( 3 downto 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of data_bram_bank_blk_mem_gen_v8_4_4_synth : entity is "blk_mem_gen_v8_4_4_synth";
@@ -284,7 +282,7 @@ begin
dina(31 downto 0) => dina(31 downto 0),
douta(31 downto 0) => douta(31 downto 0),
ena => ena,
wea(0) => wea(0)
wea(3 downto 0) => wea(3 downto 0)
);
end STRUCTURE;
library IEEE;
@@ -297,7 +295,7 @@ entity data_bram_bank_blk_mem_gen_v8_4_4 is
rsta : in STD_LOGIC;
ena : in STD_LOGIC;
regcea : in STD_LOGIC;
wea : in STD_LOGIC_VECTOR ( 0 to 0 );
wea : in STD_LOGIC_VECTOR ( 3 downto 0 );
addra : in STD_LOGIC_VECTOR ( 5 downto 0 );
dina : in STD_LOGIC_VECTOR ( 31 downto 0 );
douta : out STD_LOGIC_VECTOR ( 31 downto 0 );
@@ -305,7 +303,7 @@ entity data_bram_bank_blk_mem_gen_v8_4_4 is
rstb : in STD_LOGIC;
enb : in STD_LOGIC;
regceb : in STD_LOGIC;
web : in STD_LOGIC_VECTOR ( 0 to 0 );
web : in STD_LOGIC_VECTOR ( 3 downto 0 );
addrb : in STD_LOGIC_VECTOR ( 5 downto 0 );
dinb : in STD_LOGIC_VECTOR ( 31 downto 0 );
doutb : out STD_LOGIC_VECTOR ( 31 downto 0 );
@@ -330,7 +328,7 @@ entity data_bram_bank_blk_mem_gen_v8_4_4 is
s_axi_awvalid : in STD_LOGIC;
s_axi_awready : out STD_LOGIC;
s_axi_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_wstrb : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_wstrb : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_wlast : in STD_LOGIC;
s_axi_wvalid : in STD_LOGIC;
s_axi_wready : out STD_LOGIC;
@@ -370,7 +368,7 @@ entity data_bram_bank_blk_mem_gen_v8_4_4 is
attribute C_AXI_TYPE : integer;
attribute C_AXI_TYPE of data_bram_bank_blk_mem_gen_v8_4_4 : entity is 1;
attribute C_BYTE_SIZE : integer;
attribute C_BYTE_SIZE of data_bram_bank_blk_mem_gen_v8_4_4 : entity is 9;
attribute C_BYTE_SIZE of data_bram_bank_blk_mem_gen_v8_4_4 : entity is 8;
attribute C_COMMON_CLK : integer;
attribute C_COMMON_CLK of data_bram_bank_blk_mem_gen_v8_4_4 : entity is 0;
attribute C_COUNT_18K_BRAM : string;
@@ -478,9 +476,9 @@ entity data_bram_bank_blk_mem_gen_v8_4_4 is
attribute C_USE_BRAM_BLOCK : integer;
attribute C_USE_BRAM_BLOCK of data_bram_bank_blk_mem_gen_v8_4_4 : entity is 0;
attribute C_USE_BYTE_WEA : integer;
attribute C_USE_BYTE_WEA of data_bram_bank_blk_mem_gen_v8_4_4 : entity is 0;
attribute C_USE_BYTE_WEA of data_bram_bank_blk_mem_gen_v8_4_4 : entity is 1;
attribute C_USE_BYTE_WEB : integer;
attribute C_USE_BYTE_WEB of data_bram_bank_blk_mem_gen_v8_4_4 : entity is 0;
attribute C_USE_BYTE_WEB of data_bram_bank_blk_mem_gen_v8_4_4 : entity is 1;
attribute C_USE_DEFAULT_DATA : integer;
attribute C_USE_DEFAULT_DATA of data_bram_bank_blk_mem_gen_v8_4_4 : entity is 0;
attribute C_USE_ECC : integer;
@@ -490,9 +488,9 @@ entity data_bram_bank_blk_mem_gen_v8_4_4 is
attribute C_USE_URAM : integer;
attribute C_USE_URAM of data_bram_bank_blk_mem_gen_v8_4_4 : entity is 0;
attribute C_WEA_WIDTH : integer;
attribute C_WEA_WIDTH of data_bram_bank_blk_mem_gen_v8_4_4 : entity is 1;
attribute C_WEA_WIDTH of data_bram_bank_blk_mem_gen_v8_4_4 : entity is 4;
attribute C_WEB_WIDTH : integer;
attribute C_WEB_WIDTH of data_bram_bank_blk_mem_gen_v8_4_4 : entity is 1;
attribute C_WEB_WIDTH of data_bram_bank_blk_mem_gen_v8_4_4 : entity is 4;
attribute C_WRITE_DEPTH_A : integer;
attribute C_WRITE_DEPTH_A of data_bram_bank_blk_mem_gen_v8_4_4 : entity is 64;
attribute C_WRITE_DEPTH_B : integer;
@@ -627,7 +625,7 @@ inst_blk_mem_gen: entity work.data_bram_bank_blk_mem_gen_v8_4_4_synth
dina(31 downto 0) => dina(31 downto 0),
douta(31 downto 0) => douta(31 downto 0),
ena => ena,
wea(0) => wea(0)
wea(3 downto 0) => wea(3 downto 0)
);
end STRUCTURE;
library IEEE;
@@ -638,7 +636,7 @@ entity data_bram_bank is
port (
clka : in STD_LOGIC;
ena : in STD_LOGIC;
wea : in STD_LOGIC_VECTOR ( 0 to 0 );
wea : in STD_LOGIC_VECTOR ( 3 downto 0 );
addra : in STD_LOGIC_VECTOR ( 5 downto 0 );
dina : in STD_LOGIC_VECTOR ( 31 downto 0 );
douta : out STD_LOGIC_VECTOR ( 31 downto 0 )
@@ -687,7 +685,7 @@ architecture STRUCTURE of data_bram_bank is
attribute C_AXI_TYPE : integer;
attribute C_AXI_TYPE of U0 : label is 1;
attribute C_BYTE_SIZE : integer;
attribute C_BYTE_SIZE of U0 : label is 9;
attribute C_BYTE_SIZE of U0 : label is 8;
attribute C_COMMON_CLK : integer;
attribute C_COMMON_CLK of U0 : label is 0;
attribute C_COUNT_18K_BRAM : string;
@@ -795,9 +793,9 @@ architecture STRUCTURE of data_bram_bank is
attribute C_USE_BRAM_BLOCK : integer;
attribute C_USE_BRAM_BLOCK of U0 : label is 0;
attribute C_USE_BYTE_WEA : integer;
attribute C_USE_BYTE_WEA of U0 : label is 0;
attribute C_USE_BYTE_WEA of U0 : label is 1;
attribute C_USE_BYTE_WEB : integer;
attribute C_USE_BYTE_WEB of U0 : label is 0;
attribute C_USE_BYTE_WEB of U0 : label is 1;
attribute C_USE_DEFAULT_DATA : integer;
attribute C_USE_DEFAULT_DATA of U0 : label is 0;
attribute C_USE_ECC : integer;
@@ -807,9 +805,9 @@ architecture STRUCTURE of data_bram_bank is
attribute C_USE_URAM : integer;
attribute C_USE_URAM of U0 : label is 0;
attribute C_WEA_WIDTH : integer;
attribute C_WEA_WIDTH of U0 : label is 1;
attribute C_WEA_WIDTH of U0 : label is 4;
attribute C_WEB_WIDTH : integer;
attribute C_WEB_WIDTH of U0 : label is 1;
attribute C_WEB_WIDTH of U0 : label is 4;
attribute C_WRITE_DEPTH_A : integer;
attribute C_WRITE_DEPTH_A of U0 : label is 64;
attribute C_WRITE_DEPTH_B : integer;
@@ -893,12 +891,12 @@ U0: entity work.data_bram_bank_blk_mem_gen_v8_4_4
s_axi_wdata(31 downto 0) => B"00000000000000000000000000000000",
s_axi_wlast => '0',
s_axi_wready => NLW_U0_s_axi_wready_UNCONNECTED,
s_axi_wstrb(0) => '0',
s_axi_wstrb(3 downto 0) => B"0000",
s_axi_wvalid => '0',
sbiterr => NLW_U0_sbiterr_UNCONNECTED,
shutdown => '0',
sleep => '0',
wea(0) => wea(0),
web(0) => '0'
wea(3 downto 0) => wea(3 downto 0),
web(3 downto 0) => B"0000"
);
end STRUCTURE;

6
lacpu/rtl/xilinx_ip/data_sram_bank/data_bram_bank_stub.v
View File

@@ -1,7 +1,7 @@
// Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2019.2 (win64) Build 2708876 Wed Nov 6 21:40:23 MST 2019
// Date : Fri Jul 21 18:49:49 2023
// Date : Mon Jul 31 07:02:57 2023
// Host : BHKLaptop running 64-bit major release (build 9200)
// Command : write_verilog -force -mode synth_stub
// C:/Users/Unbal/Desktop/LoongArch/neulacpu/lacpu/rtl/xilinx_ip/data_sram_bank/data_bram_bank_stub.v
@@ -15,10 +15,10 @@
// Please paste the declaration into a Verilog source file or add the file as an additional source.
(* x_core_info = "blk_mem_gen_v8_4_4,Vivado 2019.2" *)
module data_bram_bank(clka, ena, wea, addra, dina, douta)
/* synthesis syn_black_box black_box_pad_pin="clka,ena,wea[0:0],addra[5:0],dina[31:0],douta[31:0]" */;
/* synthesis syn_black_box black_box_pad_pin="clka,ena,wea[3:0],addra[5:0],dina[31:0],douta[31:0]" */;
input clka;
input ena;
input [0:0]wea;
input [3:0]wea;
input [5:0]addra;
input [31:0]dina;
output [31:0]douta;

6
lacpu/rtl/xilinx_ip/data_sram_bank/data_bram_bank_stub.vhdl
View File

@@ -1,7 +1,7 @@
-- Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2019.2 (win64) Build 2708876 Wed Nov 6 21:40:23 MST 2019
-- Date : Fri Jul 21 18:49:49 2023
-- Date : Mon Jul 31 07:02:57 2023
-- Host : BHKLaptop running 64-bit major release (build 9200)
-- Command : write_vhdl -force -mode synth_stub
-- C:/Users/Unbal/Desktop/LoongArch/neulacpu/lacpu/rtl/xilinx_ip/data_sram_bank/data_bram_bank_stub.vhdl
@@ -16,7 +16,7 @@ entity data_bram_bank is
Port (
clka : in STD_LOGIC;
ena : in STD_LOGIC;
wea : in STD_LOGIC_VECTOR ( 0 to 0 );
wea : in STD_LOGIC_VECTOR ( 3 downto 0 );
addra : in STD_LOGIC_VECTOR ( 5 downto 0 );
dina : in STD_LOGIC_VECTOR ( 31 downto 0 );
douta : out STD_LOGIC_VECTOR ( 31 downto 0 )
@@ -28,7 +28,7 @@ architecture stub of data_bram_bank is
attribute syn_black_box : boolean;
attribute black_box_pad_pin : string;
attribute syn_black_box of stub : architecture is true;
attribute black_box_pad_pin of stub : architecture is "clka,ena,wea[0:0],addra[5:0],dina[31:0],douta[31:0]";
attribute black_box_pad_pin of stub : architecture is "clka,ena,wea[3:0],addra[5:0],dina[31:0],douta[31:0]";
attribute x_core_info : string;
attribute x_core_info of stub : architecture is "blk_mem_gen_v8_4_4,Vivado 2019.2";
begin

207
lacpu/rtl/xilinx_ip/data_sram_bank/doc/blk_mem_gen_v8_4_changelog.txt Normal file
View File

@@ -0,0 +1,207 @@
2019.2:
* Version 8.4 (Rev. 4)
* Feature Enhancement: Read Latency parameters exposed to IP GUI for URAM configurations
2019.1.3:
* Version 8.4 (Rev. 3)
* No changes
2019.1.2:
* Version 8.4 (Rev. 3)
* No changes
2019.1.1:
* Version 8.4 (Rev. 3)
* No changes
2019.1:
* Version 8.4 (Rev. 3)
* General: Internal device family change, no functional changes
2018.3.1:
* Version 8.4 (Rev. 2)
* No changes
2018.3:
* Version 8.4 (Rev. 2)
* Feature Enhancement: Read Latency Support added for URAM when selected through IP Integrator
* Other: Power Calculations disabled for URAM primitives in IP GUI, no functional changes
* Other: Internal device family change, no functional changes
2018.2:
* Version 8.4 (Rev. 1)
* No changes
2018.1:
* Version 8.4 (Rev. 1)
* No changes
2017.4:
* Version 8.4 (Rev. 1)
* General: Write depth shown in IP GUI is now dependent on number of BRAMs available in a chosen device, no functional changes
2017.3:
* Version 8.4
* General: Safety Circuit option is enabled by default if reset option in any one port is enabled
2017.2:
* Version 8.3 (Rev. 6)
* No changes
2017.1:
* Version 8.3 (Rev. 6)
* General: Internal device family change, no functional changes
* General: When common_clock is selected clkb is internally connected to clka, but the interface remains same to support the backword compatiability. User make sure of connecting the both the clocks to same clock source when in common_clock mode
2016.4:
* Version 8.3 (Rev. 5)
* General: Fixes for behavioral Model issues when built-IN ECC is enabled (to be consistent with RTL)
2016.3:
* Version 8.3 (Rev. 4)
* Feature Enhancement: URAM addressing updates while calling XPM_Memory when 32-bit addressing is enabled
* Other: Enable support for future devices
* Other: Source HDL files are concatenated into a single file to speed up synthesis and simulation. No changes required by the user
2016.2:
* Version 8.3 (Rev. 3)
* updated the IP,not to set WRITE_DEPTH parameter to 8192 everytime when the mode is switched to BRAM_Controller
* Updated the IP to support the device package changes
2016.1:
* Version 8.3 (Rev. 2)
* Updated the IP to deliver only verilog behavioral model
* Updated the IP to support UltraRAM in IP Integrator
* Updated the IP to support the device package changes
2015.4.2:
* Version 8.3 (Rev. 1)
* No changes
2015.4.1:
* Version 8.3 (Rev. 1)
* No changes
2015.4:
* Version 8.3 (Rev. 1)
* Updated the IP to support the device package changes
2015.3:
* Version 8.3
* IP revision number added to HDL module, library, and include file names, to support designs with both locked and upgraded IP instances
* New ports rsta_busy and rstb_busy are added to enable the safety circuitry to minimize the occurrence of BRAM data corruption
* Simulation models are delivered in VHDL only
2015.2.1:
* Version 8.2 (Rev. 5)
* No changes
2015.2:
* Version 8.2 (Rev. 5)
* No changes
2015.1:
* Version 8.2 (Rev. 5)
* Delivering non encrypted behavioral models
* Supported memory depth is increased up to 1M words
* Added the power saving feature (RDADDRCHG) for ultrascale devices
* Supported devices and production status are now determined automatically, to simplify support for future devices
2014.4.1:
* Version 8.2 (Rev. 4)
* Updated the IP to support the device package changes
2014.4:
* Version 8.2 (Rev. 3)
* Encrypted source files are concatenated together to reduce the number of files and to reduce simulator compile time
* Added support for 7-series Automotive (XA) and Defense Grade (XQ) devices
* Internal device family change, no functional changes
2014.3:
* Version 8.2 (Rev. 2)
* Fixed the Memory Resource Doubling issue in Simple Dual Port RAM when aspect ratio is used
* Fixed the GUI crash in Simple Dual Port RAM
* Added support of all write modes in Simple Dual Port RAM when ECC is not used
* Increased the supported depth to a maximum value of 256k
2014.2:
* Version 8.2 (Rev. 1)
* Updated the GUI tool tip for Byte write enable in the page-1 of block memory generator GUI
2014.1:
* Version 8.2
* Added support of the cascaded Primitives of widths 1 and 2 for ultra-scale devices
* Added support of the ECCPIPE register in the built-in ecc mode for ultra-scale devices
* Added support of the dynamic power saving for ultra-scale devices
* Improved timing efficiency in the IP Integrator by minimizing the use of output mux for the 7-series devices
* Internal device family name change, no functional changes
2013.4:
* Version 8.1
* The Primitive output registers are made "ON" by default in the stand alone mode
* Added cascaded support for ultrascale devices to construct 64Kx1 primitive by using two 32Kx1 primitives
* Added support for ultrascale devices
2013.3:
* Version 8.0 (Rev. 2)
* Added parameter "CTRL_ECC_ALGO" for supporting ECC in IP Integrator.
* Improved GUI speed and responsivness, no functional changes
* Reduced synthesis and simulation warnings
* Added support for Cadence IES and Synopsys VCS simulators
* Changed the default option of ENABLE PORT TYPE to "USE_ENA_PIN"
* Changed BRAM Interface DIN and DOUT to match bus interface directions.
2013.2:
* Version 8.0 (Rev. 1)
* No Changes
2013.1:
* Version 8.0
* Native Vivado Release
* There have been no functional or interface changes to this IP. The version number has changed to support unique versioning in Vivado starting with 2013.1.
(c) Copyright 2002 - 2019 Xilinx, Inc. All rights reserved.
This file contains confidential and proprietary information
of Xilinx, Inc. and is protected under U.S. and
international copyright and other intellectual property
laws.
DISCLAIMER
This disclaimer is not a license and does not grant any
rights to the materials distributed herewith. Except as
otherwise provided in a valid license issued to you by
Xilinx, and to the maximum extent permitted by applicable
law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
(2) Xilinx shall not be liable (whether in contract or tort,
including negligence, or under any other theory of
liability) for any loss or damage of any kind or nature
related to, arising under or in connection with these
materials, including for any direct, or any indirect,
special, incidental, or consequential loss or damage
(including loss of data, profits, goodwill, or any type of
loss or damage suffered as a result of any action brought
by a third party) even if such damage or loss was
reasonably foreseeable or Xilinx had been advised of the
possibility of the same.
CRITICAL APPLICATIONS
Xilinx products are not designed or intended to be fail-
safe, or for use in any application requiring fail-safe
performance, such as life-support or safety devices or
systems, Class III medical devices, nuclear facilities,
applications related to the deployment of airbags, or any
other applications that could lead to death, personal
injury, or severe property or environmental damage
(individually and collectively, "Critical
Applications"). Customer assumes the sole risk and
liability of any use of Xilinx products in Critical
Applications, subject only to applicable laws and
regulations governing limitations on product liability.
THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
PART OF THIS FILE AT ALL TIMES.

150
lacpu/rtl/xilinx_ip/data_sram_bank/misc/blk_mem_gen_v8_4.vhd Normal file
View File

@@ -0,0 +1,150 @@
library ieee;
use ieee.std_logic_1164.all;
entity blk_mem_gen_v8_4_4 is
generic (
C_FAMILY : string := "virtex7";
C_XDEVICEFAMILY : string := "virtex7";
C_ELABORATION_DIR : string := "";
C_INTERFACE_TYPE : integer := 0;
C_AXI_TYPE : integer := 1;
C_AXI_SLAVE_TYPE : integer := 0;
C_USE_BRAM_BLOCK : integer := 0;
C_ENABLE_32BIT_ADDRESS : integer := 0;
C_CTRL_ECC_ALGO : string := "ECCHSIAO32-7";
C_HAS_AXI_ID : integer := 0;
C_AXI_ID_WIDTH : integer := 4;
C_MEM_TYPE : integer := 2;
C_BYTE_SIZE : integer := 9;
C_ALGORITHM : integer := 0;
C_PRIM_TYPE : integer := 3;
C_LOAD_INIT_FILE : integer := 0;
C_INIT_FILE_NAME : string := "no_coe_file_loaded";
C_INIT_FILE : string := "no_mem_file_loaded";
C_USE_DEFAULT_DATA : integer := 0;
C_DEFAULT_DATA : string := "0";
C_HAS_RSTA : integer := 0;
C_RST_PRIORITY_A : string := "ce";
C_RSTRAM_A : integer := 0;
C_INITA_VAL : string := "0";
C_HAS_ENA : integer := 1;
C_HAS_REGCEA : integer := 0;
C_USE_BYTE_WEA : integer := 0;
C_WEA_WIDTH : integer := 1;
C_WRITE_MODE_A : string := "WRITE_FIRST";
C_WRITE_WIDTH_A : integer := 9;
C_READ_WIDTH_A : integer := 9;
C_WRITE_DEPTH_A : integer := 2048;
C_READ_DEPTH_A : integer := 2048;
C_ADDRA_WIDTH : integer := 11;
C_HAS_RSTB : integer := 0;
C_RST_PRIORITY_B : string := "ce";
C_RSTRAM_B : integer := 0;
C_INITB_VAL : string := "0";
C_HAS_ENB : integer := 1;
C_HAS_REGCEB : integer := 0;
C_USE_BYTE_WEB : integer := 0;
C_WEB_WIDTH : integer := 1;
C_WRITE_MODE_B : string := "WRITE_FIRST";
C_WRITE_WIDTH_B : integer := 9;
C_READ_WIDTH_B : integer := 9;
C_WRITE_DEPTH_B : integer := 2048;
C_READ_DEPTH_B : integer := 2048;
C_ADDRB_WIDTH : integer := 11;
C_HAS_MEM_OUTPUT_REGS_A : integer := 0;
C_HAS_MEM_OUTPUT_REGS_B : integer := 0;
C_HAS_MUX_OUTPUT_REGS_A : integer := 0;
C_HAS_MUX_OUTPUT_REGS_B : integer := 0;
C_MUX_PIPELINE_STAGES : integer := 0;
C_HAS_SOFTECC_INPUT_REGS_A : integer := 0;
C_HAS_SOFTECC_OUTPUT_REGS_B : integer := 0;
C_USE_SOFTECC : integer := 0;
C_USE_ECC : integer := 0;
C_EN_ECC_PIPE : integer := 0;
C_HAS_INJECTERR : integer := 0;
C_SIM_COLLISION_CHECK : string := "none";
C_COMMON_CLK : integer := 0;
C_DISABLE_WARN_BHV_COLL : integer := 0;
C_EN_SLEEP_PIN : integer := 0;
C_USE_URAM : integer := 0;
C_EN_RDADDRA_CHG : integer := 0;
C_EN_RDADDRB_CHG : integer := 0;
C_EN_DEEPSLEEP_PIN : integer := 0;
C_EN_SHUTDOWN_PIN : integer := 0;
C_EN_SAFETY_CKT : integer := 0;
C_DISABLE_WARN_BHV_RANGE : integer := 0;
C_COUNT_36K_BRAM : string := "";
C_COUNT_18K_BRAM : string := "";
C_EST_POWER_SUMMARY : string := ""
);
port (
clka : in std_logic := '0';
rsta : in std_logic := '0';
ena : in std_logic := '0';
regcea : in std_logic := '0';
wea : in std_logic_vector(c_wea_width - 1 downto 0) := (others => '0');
addra : in std_logic_vector(c_addra_width - 1 downto 0) := (others => '0');
dina : in std_logic_vector(c_write_width_a - 1 downto 0) := (others => '0');
douta : out std_logic_vector(c_read_width_a - 1 downto 0);
clkb : in std_logic := '0';
rstb : in std_logic := '0';
enb : in std_logic := '0';
regceb : in std_logic := '0';
web : in std_logic_vector(c_web_width - 1 downto 0) := (others => '0');
addrb : in std_logic_vector(c_addrb_width - 1 downto 0) := (others => '0');
dinb : in std_logic_vector(c_write_width_b - 1 downto 0) := (others => '0');
doutb : out std_logic_vector(c_read_width_b - 1 downto 0);
injectsbiterr : in std_logic := '0';
injectdbiterr : in std_logic := '0';
eccpipece : in std_logic := '0';
sbiterr : out std_logic;
dbiterr : out std_logic;
rdaddrecc : out std_logic_vector(c_addrb_width - 1 downto 0);
sleep : in std_logic := '0';
deepsleep : in std_logic := '0';
shutdown : in std_logic := '0';
rsta_busy : out std_logic;
rstb_busy : out std_logic;
s_aclk : in std_logic := '0';
s_aresetn : in std_logic := '0';
s_axi_awid : in std_logic_vector(c_axi_id_width - 1 downto 0) := (others => '0');
s_axi_awaddr : in std_logic_vector(31 downto 0) := (others => '0');
s_axi_awlen : in std_logic_vector(7 downto 0) := (others => '0');
s_axi_awsize : in std_logic_vector(2 downto 0) := (others => '0');
s_axi_awburst : in std_logic_vector(1 downto 0) := (others => '0');
s_axi_awvalid : in std_logic := '0';
s_axi_awready : out std_logic;
s_axi_wdata : in std_logic_vector(c_write_width_a - 1 downto 0) := (others => '0');
s_axi_wstrb : in std_logic_vector(c_wea_width - 1 downto 0) := (others => '0');
s_axi_wlast : in std_logic := '0';
s_axi_wvalid : in std_logic := '0';
s_axi_wready : out std_logic;
s_axi_bid : out std_logic_vector(c_axi_id_width - 1 downto 0);
s_axi_bresp : out std_logic_vector(1 downto 0);
s_axi_bvalid : out std_logic;
s_axi_bready : in std_logic := '0';
s_axi_arid : in std_logic_vector(c_axi_id_width - 1 downto 0) := (others => '0');
s_axi_araddr : in std_logic_vector(31 downto 0) := (others => '0');
s_axi_arlen : in std_logic_vector(8 - 1 downto 0) := (others => '0');
s_axi_arsize : in std_logic_vector(2 downto 0) := (others => '0');
s_axi_arburst : in std_logic_vector(1 downto 0) := (others => '0');
s_axi_arvalid : in std_logic := '0';
s_axi_arready : out std_logic;
s_axi_rid : out std_logic_vector(c_axi_id_width - 1 downto 0);
s_axi_rdata : out std_logic_vector(c_write_width_b - 1 downto 0);
s_axi_rresp : out std_logic_vector(2 - 1 downto 0);
s_axi_rlast : out std_logic;
s_axi_rvalid : out std_logic;
s_axi_rready : in std_logic := '0';
s_axi_injectsbiterr : in std_logic := '0';
s_axi_injectdbiterr : in std_logic := '0';
s_axi_sbiterr : out std_logic;
s_axi_dbiterr : out std_logic;
s_axi_rdaddrecc : out std_logic_vector(c_addrb_width - 1 downto 0)
);
end entity blk_mem_gen_v8_4_4;
architecture xilinx of blk_mem_gen_v8_4_4 is
begin
end
architecture xilinx;

220
lacpu/rtl/xilinx_ip/data_sram_bank/sim/data_bram_bank.v Normal file
View File

@@ -0,0 +1,220 @@
// (c) Copyright 1995-2023 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
// DO NOT MODIFY THIS FILE.
// IP VLNV: xilinx.com:ip:blk_mem_gen:8.4
// IP Revision: 4
`timescale 1ns/1ps
(* DowngradeIPIdentifiedWarnings = "yes" *)
module data_bram_bank (
clka,
ena,
wea,
addra,
dina,
douta
);
(* X_INTERFACE_INFO = "xilinx.com:interface:bram:1.0 BRAM_PORTA CLK" *)
input wire clka;
(* X_INTERFACE_INFO = "xilinx.com:interface:bram:1.0 BRAM_PORTA EN" *)
input wire ena;
(* X_INTERFACE_INFO = "xilinx.com:interface:bram:1.0 BRAM_PORTA WE" *)
input wire [3 : 0] wea;
(* X_INTERFACE_INFO = "xilinx.com:interface:bram:1.0 BRAM_PORTA ADDR" *)
input wire [5 : 0] addra;
(* X_INTERFACE_INFO = "xilinx.com:interface:bram:1.0 BRAM_PORTA DIN" *)
input wire [31 : 0] dina;
(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME BRAM_PORTA, MEM_SIZE 8192, MEM_WIDTH 32, MEM_ECC NONE, MASTER_TYPE OTHER, READ_LATENCY 1" *)
(* X_INTERFACE_INFO = "xilinx.com:interface:bram:1.0 BRAM_PORTA DOUT" *)
output wire [31 : 0] douta;
blk_mem_gen_v8_4_4 #(
.C_FAMILY("artix7"),
.C_XDEVICEFAMILY("artix7"),
.C_ELABORATION_DIR("./"),
.C_INTERFACE_TYPE(0),
.C_AXI_TYPE(1),
.C_AXI_SLAVE_TYPE(0),
.C_USE_BRAM_BLOCK(0),
.C_ENABLE_32BIT_ADDRESS(0),
.C_CTRL_ECC_ALGO("NONE"),
.C_HAS_AXI_ID(0),
.C_AXI_ID_WIDTH(4),
.C_MEM_TYPE(0),
.C_BYTE_SIZE(8),
.C_ALGORITHM(1),
.C_PRIM_TYPE(1),
.C_LOAD_INIT_FILE(0),
.C_INIT_FILE_NAME("no_coe_file_loaded"),
.C_INIT_FILE("data_bram_bank.mem"),
.C_USE_DEFAULT_DATA(0),
.C_DEFAULT_DATA("0"),
.C_HAS_RSTA(0),
.C_RST_PRIORITY_A("CE"),
.C_RSTRAM_A(0),
.C_INITA_VAL("0"),
.C_HAS_ENA(1),
.C_HAS_REGCEA(0),
.C_USE_BYTE_WEA(1),
.C_WEA_WIDTH(4),
.C_WRITE_MODE_A("WRITE_FIRST"),
.C_WRITE_WIDTH_A(32),
.C_READ_WIDTH_A(32),
.C_WRITE_DEPTH_A(64),
.C_READ_DEPTH_A(64),
.C_ADDRA_WIDTH(6),
.C_HAS_RSTB(0),
.C_RST_PRIORITY_B("CE"),
.C_RSTRAM_B(0),
.C_INITB_VAL("0"),
.C_HAS_ENB(0),
.C_HAS_REGCEB(0),
.C_USE_BYTE_WEB(1),
.C_WEB_WIDTH(4),
.C_WRITE_MODE_B("WRITE_FIRST"),
.C_WRITE_WIDTH_B(32),
.C_READ_WIDTH_B(32),
.C_WRITE_DEPTH_B(64),
.C_READ_DEPTH_B(64),
.C_ADDRB_WIDTH(6),
.C_HAS_MEM_OUTPUT_REGS_A(0),
.C_HAS_MEM_OUTPUT_REGS_B(0),
.C_HAS_MUX_OUTPUT_REGS_A(0),
.C_HAS_MUX_OUTPUT_REGS_B(0),
.C_MUX_PIPELINE_STAGES(0),
.C_HAS_SOFTECC_INPUT_REGS_A(0),
.C_HAS_SOFTECC_OUTPUT_REGS_B(0),
.C_USE_SOFTECC(0),
.C_USE_ECC(0),
.C_EN_ECC_PIPE(0),
.C_READ_LATENCY_A(1),
.C_READ_LATENCY_B(1),
.C_HAS_INJECTERR(0),
.C_SIM_COLLISION_CHECK("ALL"),
.C_COMMON_CLK(0),
.C_DISABLE_WARN_BHV_COLL(0),
.C_EN_SLEEP_PIN(0),
.C_USE_URAM(0),
.C_EN_RDADDRA_CHG(0),
.C_EN_RDADDRB_CHG(0),
.C_EN_DEEPSLEEP_PIN(0),
.C_EN_SHUTDOWN_PIN(0),
.C_EN_SAFETY_CKT(0),
.C_DISABLE_WARN_BHV_RANGE(0),
.C_COUNT_36K_BRAM("0"),
.C_COUNT_18K_BRAM("1"),
.C_EST_POWER_SUMMARY("Estimated Power for IP : 3.53845 mW")
) inst (
.clka(clka),
.rsta(1'D0),
.ena(ena),
.regcea(1'D0),
.wea(wea),
.addra(addra),
.dina(dina),
.douta(douta),
.clkb(1'D0),
.rstb(1'D0),
.enb(1'D0),
.regceb(1'D0),
.web(4'B0),
.addrb(6'B0),
.dinb(32'B0),
.doutb(),
.injectsbiterr(1'D0),
.injectdbiterr(1'D0),
.eccpipece(1'D0),
.sbiterr(),
.dbiterr(),
.rdaddrecc(),
.sleep(1'D0),
.deepsleep(1'D0),
.shutdown(1'D0),
.rsta_busy(),
.rstb_busy(),
.s_aclk(1'H0),
.s_aresetn(1'D0),
.s_axi_awid(4'B0),
.s_axi_awaddr(32'B0),
.s_axi_awlen(8'B0),
.s_axi_awsize(3'B0),
.s_axi_awburst(2'B0),
.s_axi_awvalid(1'D0),
.s_axi_awready(),
.s_axi_wdata(32'B0),
.s_axi_wstrb(4'B0),
.s_axi_wlast(1'D0),
.s_axi_wvalid(1'D0),
.s_axi_wready(),
.s_axi_bid(),
.s_axi_bresp(),
.s_axi_bvalid(),
.s_axi_bready(1'D0),
.s_axi_arid(4'B0),
.s_axi_araddr(32'B0),
.s_axi_arlen(8'B0),
.s_axi_arsize(3'B0),
.s_axi_arburst(2'B0),
.s_axi_arvalid(1'D0),
.s_axi_arready(),
.s_axi_rid(),
.s_axi_rdata(),
.s_axi_rresp(),
.s_axi_rlast(),
.s_axi_rvalid(),
.s_axi_rready(1'D0),
.s_axi_injectsbiterr(1'D0),
.s_axi_injectdbiterr(1'D0),
.s_axi_sbiterr(),
.s_axi_dbiterr(),
.s_axi_rdaddrecc()
);
endmodule

4522
lacpu/rtl/xilinx_ip/data_sram_bank/simulation/blk_mem_gen_v8_4.v Normal file
View File

File diff suppressed because it is too large Load Diff

20
lacpu/rtl/xilinx_ip/data_sram_bank/summary.log Normal file
View File

@@ -0,0 +1,20 @@
User Configuration
--------------------------------------------------------------------------------
Algorithm : Minimum_Area
Memory Type : Single_Port_RAM
Port A Read Width : [32]
Port A Write Width : [32]
Memory Depth : [64]
----------------------------------------------------------------------------------
Block RAM resource(s) (18K BRAMs) : [1]
Block RAM resource(s) (36K BRAMs) : [0]
----------------------------------------------------------------------------------
Clock A Frequency : [100]
Port A Enable Rate : [100]
Port A Write Rate : [50]
----------------------------------------------------------------------------------
Estimated Power for IP : 3.53845 mW
----------------------------------------------------------------------------------

26
lacpu/rtl/xilinx_ip/data_sram_bank/synth/data_bram_bank.vhd
View File

@@ -60,7 +60,7 @@ ENTITY data_bram_bank IS
PORT (
clka : IN STD_LOGIC;
ena : IN STD_LOGIC;
wea : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
wea : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
addra : IN STD_LOGIC_VECTOR(5 DOWNTO 0);
dina : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
douta : OUT STD_LOGIC_VECTOR(31 DOWNTO 0)
@@ -153,7 +153,7 @@ ARCHITECTURE data_bram_bank_arch OF data_bram_bank IS
rsta : IN STD_LOGIC;
ena : IN STD_LOGIC;
regcea : IN STD_LOGIC;
wea : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
wea : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
addra : IN STD_LOGIC_VECTOR(5 DOWNTO 0);
dina : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
douta : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
@@ -161,7 +161,7 @@ ARCHITECTURE data_bram_bank_arch OF data_bram_bank IS
rstb : IN STD_LOGIC;
enb : IN STD_LOGIC;
regceb : IN STD_LOGIC;
web : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
web : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
addrb : IN STD_LOGIC_VECTOR(5 DOWNTO 0);
dinb : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
doutb : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
@@ -186,7 +186,7 @@ ARCHITECTURE data_bram_bank_arch OF data_bram_bank IS
s_axi_awvalid : IN STD_LOGIC;
s_axi_awready : OUT STD_LOGIC;
s_axi_wdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_wstrb : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_wstrb : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_wlast : IN STD_LOGIC;
s_axi_wvalid : IN STD_LOGIC;
s_axi_wready : OUT STD_LOGIC;
@@ -219,8 +219,8 @@ ARCHITECTURE data_bram_bank_arch OF data_bram_bank IS
ATTRIBUTE CHECK_LICENSE_TYPE : STRING;
ATTRIBUTE CHECK_LICENSE_TYPE OF data_bram_bank_arch : ARCHITECTURE IS "data_bram_bank,blk_mem_gen_v8_4_4,{}";
ATTRIBUTE CORE_GENERATION_INFO : STRING;
ATTRIBUTE CORE_GENERATION_INFO OF data_bram_bank_arch: ARCHITECTURE IS "data_bram_bank,blk_mem_gen_v8_4_4,{x_ipProduct=Vivado 2019.2,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=blk_mem_gen,x_ipVersion=8.4,x_ipCoreRevision=4,x_ipLanguage=VERILOG,x_ipSimLanguage=MIXED,C_FAMILY=artix7,C_XDEVICEFAMILY=artix7,C_ELABORATION_DIR=./,C_INTERFACE_TYPE=0,C_AXI_TYPE=1,C_AXI_SLAVE_TYPE=0,C_USE_BRAM_BLOCK=0,C_ENABLE_32BIT_ADDRESS=0,C_CTRL_ECC_ALGO=NONE,C_HAS_AXI_ID=0,C_AXI_ID_WIDTH=4,C_MEM_TYPE=0,C_BYTE_SIZE=9,C_ALGORITHM=1,C_PRIM_TYPE=1,C_LOAD_INIT_FILE=0,C_INIT_FILE_NAME=no_c" &
"oe_file_loaded,C_INIT_FILE=data_bram_bank.mem,C_USE_DEFAULT_DATA=0,C_DEFAULT_DATA=0,C_HAS_RSTA=0,C_RST_PRIORITY_A=CE,C_RSTRAM_A=0,C_INITA_VAL=0,C_HAS_ENA=1,C_HAS_REGCEA=0,C_USE_BYTE_WEA=0,C_WEA_WIDTH=1,C_WRITE_MODE_A=WRITE_FIRST,C_WRITE_WIDTH_A=32,C_READ_WIDTH_A=32,C_WRITE_DEPTH_A=64,C_READ_DEPTH_A=64,C_ADDRA_WIDTH=6,C_HAS_RSTB=0,C_RST_PRIORITY_B=CE,C_RSTRAM_B=0,C_INITB_VAL=0,C_HAS_ENB=0,C_HAS_REGCEB=0,C_USE_BYTE_WEB=0,C_WEB_WIDTH=1,C_WRITE_MODE_B=WRITE_FIRST,C_WRITE_WIDTH_B=32,C_READ_WIDTH_B=32" &
ATTRIBUTE CORE_GENERATION_INFO OF data_bram_bank_arch: ARCHITECTURE IS "data_bram_bank,blk_mem_gen_v8_4_4,{x_ipProduct=Vivado 2019.2,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=blk_mem_gen,x_ipVersion=8.4,x_ipCoreRevision=4,x_ipLanguage=VERILOG,x_ipSimLanguage=MIXED,C_FAMILY=artix7,C_XDEVICEFAMILY=artix7,C_ELABORATION_DIR=./,C_INTERFACE_TYPE=0,C_AXI_TYPE=1,C_AXI_SLAVE_TYPE=0,C_USE_BRAM_BLOCK=0,C_ENABLE_32BIT_ADDRESS=0,C_CTRL_ECC_ALGO=NONE,C_HAS_AXI_ID=0,C_AXI_ID_WIDTH=4,C_MEM_TYPE=0,C_BYTE_SIZE=8,C_ALGORITHM=1,C_PRIM_TYPE=1,C_LOAD_INIT_FILE=0,C_INIT_FILE_NAME=no_c" &
"oe_file_loaded,C_INIT_FILE=data_bram_bank.mem,C_USE_DEFAULT_DATA=0,C_DEFAULT_DATA=0,C_HAS_RSTA=0,C_RST_PRIORITY_A=CE,C_RSTRAM_A=0,C_INITA_VAL=0,C_HAS_ENA=1,C_HAS_REGCEA=0,C_USE_BYTE_WEA=1,C_WEA_WIDTH=4,C_WRITE_MODE_A=WRITE_FIRST,C_WRITE_WIDTH_A=32,C_READ_WIDTH_A=32,C_WRITE_DEPTH_A=64,C_READ_DEPTH_A=64,C_ADDRA_WIDTH=6,C_HAS_RSTB=0,C_RST_PRIORITY_B=CE,C_RSTRAM_B=0,C_INITB_VAL=0,C_HAS_ENB=0,C_HAS_REGCEB=0,C_USE_BYTE_WEB=1,C_WEB_WIDTH=4,C_WRITE_MODE_B=WRITE_FIRST,C_WRITE_WIDTH_B=32,C_READ_WIDTH_B=32" &
",C_WRITE_DEPTH_B=64,C_READ_DEPTH_B=64,C_ADDRB_WIDTH=6,C_HAS_MEM_OUTPUT_REGS_A=0,C_HAS_MEM_OUTPUT_REGS_B=0,C_HAS_MUX_OUTPUT_REGS_A=0,C_HAS_MUX_OUTPUT_REGS_B=0,C_MUX_PIPELINE_STAGES=0,C_HAS_SOFTECC_INPUT_REGS_A=0,C_HAS_SOFTECC_OUTPUT_REGS_B=0,C_USE_SOFTECC=0,C_USE_ECC=0,C_EN_ECC_PIPE=0,C_READ_LATENCY_A=1,C_READ_LATENCY_B=1,C_HAS_INJECTERR=0,C_SIM_COLLISION_CHECK=ALL,C_COMMON_CLK=0,C_DISABLE_WARN_BHV_COLL=0,C_EN_SLEEP_PIN=0,C_USE_URAM=0,C_EN_RDADDRA_CHG=0,C_EN_RDADDRB_CHG=0,C_EN_DEEPSLEEP_PIN=0,C_E" &
"N_SHUTDOWN_PIN=0,C_EN_SAFETY_CKT=0,C_DISABLE_WARN_BHV_RANGE=0,C_COUNT_36K_BRAM=0,C_COUNT_18K_BRAM=1,C_EST_POWER_SUMMARY=Estimated Power for IP _ 3.53845 mW}";
ATTRIBUTE X_INTERFACE_INFO : STRING;
@@ -247,7 +247,7 @@ BEGIN
C_HAS_AXI_ID => 0,
C_AXI_ID_WIDTH => 4,
C_MEM_TYPE => 0,
C_BYTE_SIZE => 9,
C_BYTE_SIZE => 8,
C_ALGORITHM => 1,
C_PRIM_TYPE => 1,
C_LOAD_INIT_FILE => 0,
@@ -261,8 +261,8 @@ BEGIN
C_INITA_VAL => "0",
C_HAS_ENA => 1,
C_HAS_REGCEA => 0,
C_USE_BYTE_WEA => 0,
C_WEA_WIDTH => 1,
C_USE_BYTE_WEA => 1,
C_WEA_WIDTH => 4,
C_WRITE_MODE_A => "WRITE_FIRST",
C_WRITE_WIDTH_A => 32,
C_READ_WIDTH_A => 32,
@@ -275,8 +275,8 @@ BEGIN
C_INITB_VAL => "0",
C_HAS_ENB => 0,
C_HAS_REGCEB => 0,
C_USE_BYTE_WEB => 0,
C_WEB_WIDTH => 1,
C_USE_BYTE_WEB => 1,
C_WEB_WIDTH => 4,
C_WRITE_MODE_B => "WRITE_FIRST",
C_WRITE_WIDTH_B => 32,
C_READ_WIDTH_B => 32,
@@ -324,7 +324,7 @@ BEGIN
rstb => '0',
enb => '0',
regceb => '0',
web => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
web => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
addrb => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 6)),
dinb => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
injectsbiterr => '0',
@@ -342,7 +342,7 @@ BEGIN
s_axi_awburst => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)),
s_axi_awvalid => '0',
s_axi_wdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
s_axi_wstrb => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axi_wstrb => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
s_axi_wlast => '0',
s_axi_wvalid => '0',
s_axi_bready => '0',