[Modified] 8-stage v0.2. optimize mul stall, pass pref test but ail func test
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@@ -32,6 +32,16 @@ module mul_div_top(
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wire sign_flag_locked;
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wire rem_flag_locked;
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//-------------------------
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wire [63:0] unsigned_prod;
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wire [63:0] signed_prod;
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assign unsigned_prod = a * b;
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//assign signed_prod = $signed(a) * $signed(b);
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//-------------------------
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assign mul_en = mul_div_op[0] | mul_div_op[1];
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assign div_en = mul_div_op[2] | mul_div_op[3];
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@@ -64,19 +74,21 @@ module mul_div_top(
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.reset (reset ),
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.stallreq (stallreq_for_mul),
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.in_valid (mul_en_locked ),
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.out_valid (),
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.out_valid ( ),
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.a (a_locked ),
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.b (b_locked ),
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.result_h (result_h ),
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.result_l (result_l )
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);
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div u_div(
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.clk (clk ),
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.reset (reset ),
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.stallreq (stallreq_for_div),
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.in_valid (div_en_locked ),
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.out_valid (),
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.out_valid ( ),
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.a (a_locked ),
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.b (b_locked ),
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.quotient (quotient ),
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