[Modified] 8-stage v0.2. optimize mul stall, pass pref test but ail func test

lacpu/rtl/mycpu/mmu.v

@@ -3,19 +3,12 @@ module mmu (
     output [31:0] addr_o,
     output        cache_v
 );
-    wire [1:0] addr_head_i, addr_head_o;
-    assign addr_head_i = addr_i[31:30];
-
-    wire kseg0_l, kseg0_h, kseg1_l, kseg1_h;
-    assign kseg0_l = addr_head_i == 2'b00;
-    assign kseg0_h = addr_head_i == 2'b01;
-    assign kseg1_l = addr_head_i == 2'b10;
-    assign kseg1_h = addr_head_i == 2'b11;
     
-    wire other_seg;
-    assign other_seg = ~kseg0_l & ~kseg0_h & ~kseg1_l & ~kseg1_h;
-    assign addr_head_o = {2{kseg0_l}}&2'b00 | {2{kseg0_h}}&2'b01 | {2{kseg1_l}}&2'b10 | {2{kseg1_h}}&2'b11 | {2{other_seg}}&addr_head_i;
-    assign addr_o = {addr_head_o, addr_i[29:0]};
+    wire [31:0] dmw0;
+    assign dmw0 = 0;
 
-    assign cache_v = ~(kseg0_l|kseg1_l|kseg1_h);
+    assign cache_v = (dmw0[31:29] == addr_i[31:29]);
+
+    assign addr_o =  cache_v? {dmw0[27:25],addr_i[28:0]} : addr_i;
+    
 endmodule

lacpu/rtl/mycpu/mul.v

@@ -14,6 +14,9 @@ module mul(
     reg  [ 5:0] cnt;
     wire [31:0] add_result;
     wire        carry;
+
+    wire [63:0] mul_result;
+
     always @ (posedge clk) begin
         if (reset) begin
             cnt <= 0;
@@ -22,11 +25,11 @@ module mul(
             cnt <= cnt - 1;
         end
         else if (in_valid) begin
-            cnt <= 32;
+            cnt <= 1;//32;
         end
     end
 
-    assign {carry, add_result} = result_h + (result_l[0] ? a : 0);
+    assign mul_result = a * b;
 
     always @ (posedge clk) begin
         if (reset) begin
@@ -34,11 +37,13 @@ module mul(
             result_l <= 0;
         end 
         else if (cnt != 0) begin
-            {result_h, result_l} <= {carry, add_result, result_l[31:1]};
+            //{result_h, result_l} <= {carry, add_result, result_l[31:1]};
+            result_h <= mul_result[63:32];
+            result_l <= mul_result[31: 0];
         end
         else if (in_valid) begin
             result_h <= 0;
-            result_l <= b;
+            result_l <= 0;//b;
         end
     end 
 

lacpu/rtl/mycpu/mul_div_lock.v

@@ -67,7 +67,7 @@ module mul_div_lock (
 
             first_enable     <= 0;
         end
-        else if (!stallreq & (mul_en|div_en) & !first_enable & !stall[2]) begin
+        else if (!stallreq & (mul_en|div_en) & !first_enable & (!stall[2] | (stall[2] & (!stall[3])))) begin
             a_buffer         <= 0;
             b_buffer         <= 0;
             sign_flag_buffer <= 0;

lacpu/rtl/mycpu/mul_div_top.v

@@ -32,6 +32,16 @@ module mul_div_top(
     wire        sign_flag_locked;
     wire        rem_flag_locked;
 
+
+    //-------------------------  
+
+    wire [63:0] unsigned_prod;
+    wire [63:0] signed_prod;
+
+    assign unsigned_prod = a * b;
+    //assign signed_prod = $signed(a) * $signed(b);
+
+    //-------------------------
     assign mul_en = mul_div_op[0] | mul_div_op[1];
     assign div_en = mul_div_op[2] | mul_div_op[3];
 
@@ -64,19 +74,21 @@ module mul_div_top(
         .reset     (reset           ),
         .stallreq  (stallreq_for_mul),
         .in_valid  (mul_en_locked   ),
-        .out_valid (),
+        .out_valid (                ),
         .a         (a_locked        ),
         .b         (b_locked        ),
         .result_h  (result_h        ),
         .result_l  (result_l        )
     );
 
+
+
     div u_div(
         .clk       (clk             ),
         .reset     (reset           ),
         .stallreq  (stallreq_for_div),
         .in_valid  (div_en_locked   ),
-        .out_valid (),
+        .out_valid (                ),
         .a         (a_locked        ),
         .b         (b_locked        ),
         .quotient  (quotient        ),

lacpu/rtl/mycpu/pip_ctrl.v

@@ -34,7 +34,7 @@ module pip_ctrl(
             flush = 0;
             stall = `StallBus'b111111;
         end
-        //id段发生暂停，此时id及之前暂停
+        //id段å<EFBFBD>‘生暂å<EFBFBD>œï¼Œæ­¤æ—¶idå<EFBFBD>Šä¹‹å‰<EFBFBD>æš‚å<EFBFBD>?
         else if (stallreq_ds) begin
             flush = 0;
             stall = `StallBus'b000111;