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[Modified] Fix bugs & 46 Functional Test Point PASS

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包焕垲
2023-06-26 20:30:39 +08:00
parent 38f1ea7eda
commit 7a879edcb6
4 changed files with 39 additions and 57 deletions
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8
lacpu/rtl/cpu/bru.v
View File

@@ -36,10 +36,10 @@ module bru(
} = branch_op;
assign rj_eq_rd = (rj_value == rkd_value);
assign rj_lt_rd = (rj_value < rkd_value);
assign rj_ltu_rd = (rj_value[31] && ~rkd_value[31]) ? 1'b1 :
(~rj_value[31] && rkd_value[31]) ? 1'b0 :
rj_lt_rd;
assign rj_ltu_rd = (rj_value < rkd_value);
assign rj_lt_rd = (rj_value[31] && ~rkd_value[31]) ? 1'b1 :
(~rj_value[31] && rkd_value[31]) ? 1'b0 :
rj_ltu_rd;
assign br_taken = ( inst_beq && rj_eq_rd
|| inst_bne && !rj_eq_rd
|| inst_blt && rj_lt_rd

10
lacpu/rtl/cpu/exe_stage.v
View File

@@ -67,6 +67,7 @@ module exe_stage
wire br_taken;
wire [31:0] br_target;
wire br_flush;
wire data_sram_en_temp;
@@ -122,6 +123,8 @@ module exe_stage
inst //31 :0
};
assign br_flush = br_taken;
always @ (posedge clk) begin
if (reset) begin
ds_to_es_bus_r <= 0;
@@ -134,7 +137,7 @@ module exe_stage
ds_to_es_bus_r <= 0;
end
//nop, id not stall and br_bus[32]
else if (!stall[2]&br_bus[32]) begin
else if (!stall[2]&br_flush) begin
ds_to_es_bus_r <= 0;
end
// id not stall so can go on
@@ -210,8 +213,9 @@ module exe_stage
.mul_div_result(mul_div_result )
);
assign es_result = |mul_div_op ? mul_div_result :
alu_result;
assign es_result = (|mul_div_op ) ? mul_div_result :
(|load_op | |store_op) ? data_sram_addr :
alu_result;
assign csr_wdata = csr_wdata_sel ? imm : src1;
assign csr_bus = {csr_we,

26
lacpu/rtl/cpu/mem_stage.v
View File

@@ -135,19 +135,19 @@ module mem_stage
.out(byte_sel )
);
assign ms_result = (inst_ld_b & byte_sel[0]) ? {{24{data_temp[ 7]}}, data_temp[ 7: 0] } :
(inst_ld_b & byte_sel[1]) ? {{16{data_temp[15]}}, data_temp[15: 8], 8'b0} :
(inst_ld_b & byte_sel[2]) ? {{ 8{data_temp[23]}}, data_temp[23:16], 16'b0} :
(inst_ld_b & byte_sel[3]) ? { data_temp[31:24], 24'b0} :
(inst_ld_bu & byte_sel[0]) ? { 24'b0, data_temp[ 7: 0] } :
(inst_ld_bu & byte_sel[1]) ? { 16'b0, data_temp[15: 8], 8'b0} :
(inst_ld_bu & byte_sel[2]) ? { 8'b0, data_temp[23:16], 16'b0} :
(inst_ld_bu & byte_sel[3]) ? { data_temp[31:24], 24'b0} :
(inst_ld_h & byte_sel[0]) ? {{16{data_temp[15]}}, data_temp[15: 0] } :
(inst_ld_h & byte_sel[2]) ? { data_temp[15: 0], 16'b0} :
(inst_ld_hu & byte_sel[0]) ? { 16'b0, data_temp[15: 0] } :
(inst_ld_hu & byte_sel[2]) ? { data_temp[15: 0], 16'b0} :
(inst_ld_w & byte_sel[0]) ? data_temp :
assign ms_result = (inst_ld_b & byte_sel[0]) ? {{24{data_temp[ 7]}}, data_temp[ 7: 0]} :
(inst_ld_b & byte_sel[1]) ? {{24{data_temp[15]}}, data_temp[15: 8]} :
(inst_ld_b & byte_sel[2]) ? {{24{data_temp[23]}}, data_temp[23:16]} :
(inst_ld_b & byte_sel[3]) ? {{24{data_temp[31]}}, data_temp[31:24]} :
(inst_ld_bu & byte_sel[0]) ? { 24'b0, data_temp[ 7: 0]} :
(inst_ld_bu & byte_sel[1]) ? { 24'b0, data_temp[15: 8]} :
(inst_ld_bu & byte_sel[2]) ? { 24'b0, data_temp[23:16]} :
(inst_ld_bu & byte_sel[3]) ? { 24'b0, data_temp[31:24]} :
(inst_ld_h & byte_sel[0]) ? {{16{data_temp[15]}}, data_temp[15: 0]} :
(inst_ld_h & byte_sel[2]) ? {{16{data_temp[31]}}, data_temp[31:16]} :
(inst_ld_hu & byte_sel[0]) ? { 16'b0, data_temp[15: 0]} :
(inst_ld_hu & byte_sel[2]) ? { 16'b0, data_temp[31:16]} :
(inst_ld_w & byte_sel[0]) ? data_temp :
32'b0; // inst_ll ?
assign {csr_we,