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lacpu/README.md
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lacpu/README.md
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## 指令完成情况
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#### op6
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- [x] `0 1 0` 开头，`0 1 1` - `1 1 1`。共 5 项：**jirl, b, bl, beq, bne**
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- [x] `0 1 1` 开头，`0 0 0` - `0 1 1`。共 4 项：**blt, bge, bltu, bgeu**
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#### op7
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- [x] `0 0 0 1` 开头，`0 1 0`, `1 1 0`。共 2 项：**lu12i.w, pcaddu12i**
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#### op10
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- [x] `0 0 0 0 0 0 1` 开头， `0 0 0` - `1 1 1` 中间有缺项。 共 6 项：**slti, sltui, addi.w andi, ori, xori**
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- [x] `0 0 1 0 1 0 0` 开头，`0 0 0` - `1 1 0`。共 6 项：**ld.b, ld.h, ld.w, st.b, st.h, st.w**
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- [x] `0 0 1 0 1 0 1` 开头，`0 0 0` - `0 0 1`。共 3 项：**ld.bu, ld.hu**, preld
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#### op17
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- [x] `0 0 0 0 0 0 0 0 0 0 0 1` 开头，`0 0 0 0 0` - `1 0 0 0 0` 中间有缺项。共 11 项：**add.w, sub.w, slt, sltu, nor, and, or, xor, sll.w, srl.w, sra.w**
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- [ ] `0 0 0 0 0 0 0 0 0 0 0 1` 开头，`1 1 0 0 0` - `1 1 0 1 0` 。共 3 项：mul.w, mulh.w, mulh.wu
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- [ ] `0 0 0 0 0 0 0 0 0 0 1 0` 开头，`0 0 0 0 0` - `0 0 0 1 1`。共 4 项：div.w, mod.w, div.wu, mod.wu
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- [x] `0 0 0 0 0 0 0 0 0 1 0 0` 开头，`0 0` - `1 0` + `0 0 1`。共 3 项：**slli.w, srli.w, srai.w**
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- [ ] `0 0 1 1 1 0 0 0 0 1 1 1` 开头，`0 0 1 0 0` - `0 0 1 0 1` 。共 2 项：dbar, ibar
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#### op22
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- [ ] `0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0` 开头。共 3 项：rdcntid.w, rdcntvl.w, rdcntvh.w
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#### alu_op
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add.w, addi.w, pcaddu12i, ld.b, ld.h, ld.bu, ld.hu, ld.w, st.b, st.h, st.w, b, bl, jirl
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sub.w
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slt, sltu, stli, sltui
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and, andi
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nor
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or, ori
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xor, xori
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sll.w, slli.w
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srl.w, srli.w
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sra.w, srai.w
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lui12i.w
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## 简单整理
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### 算数运算类
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| √ | 指令 | 格式 | 说明 |
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| ---- | --------- | ------------------- | ------------------------------------------- |
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| √ | ADD.W | add.w rd, rj, rk | |
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| √ | SUB.W | sub.w rd, rj, rk | |
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| √ | ADDI.W | addi.w rd, rj, si12 | si12 符号扩展 32 位 |
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| √ | LU12I.W | lu12i.w rd, si20 | 将 si20 最低位连接 12'b0 符号扩展 |
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| √ | SLT | slt rd, rj, rk | 如果前者小于后者 GR[rd] 置 1 |
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| √ | SLTU | sltu rd, rj, rk | |
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| √ | SLTI | slt i rd, rj, si12 | |
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| √ | SLTUI | sltu i rd, rj, si12 | |
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| √ | PCADDU12I | pcaddu12i rd, si20 | 最低位连接 12'b0 |
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| √ | AND | and rd, rj, rk | |
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| √ | OR | or rd, rj, rk | |
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| √ | NOR | nor rd, rj, rk | |
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| √ | XOR | xor rd, rj, rk | |
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| √ | ANDI | and i rd, rj, ui12 | ui12 立即数零扩展 |
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| √ | ORI | ori rd, rj, ui 12 | |
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| √ | XORI | xori rd, rj, ui12 | |
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| - | NOP | andi r0, r0, 0 | |
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| | MUL.W | mul.w rd, rj, rk | 操作数视为有符号数，结果符号扩展 |
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| | MULH.W | mulh.w rd, rj, rk | 操作数视为有符号数，结果的 [63:32] 符号扩展 |
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| | MULH.WU | mulh.wu rd, rj, rk | 操作数视为无符号数 |
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| | DIV.W | div.w rd, rj, rk | 操作数视为有符号数，结果符号扩展 |
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| | MOD.W | mod.w rd, rj, rk | |
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| | DIV.WU | div.wu rd, rj, rk | 操作数视为无符号数 |
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| | MOD,WU | mod.wu rd, rj, rk | |
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### 移位运算类
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| √ | 指令 | 格式 | 说明 |
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| ------- | ------------------- | ----------------------------------- | ----------------------------------- |
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| √ | SLL.W | sll.w rd, rj, rk | 逻辑左移，结果符号扩展，GR\[rk][4:0] |
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| √ | SRL.W | srl.w r d, rj, rk | |
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| √ | SRA.W | sra.w rd, rj, rk | 算数右移，结果符号扩展 |
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| √ | SLLI.W | slli.w rd, rj, ui5 | |
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| √ | SRLI.W | srli.w rd, rj, ui5 | |
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| √ | SRAI.W | srai.w rd, rj, ui5 | |
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### 转移指令
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| √ | 指令 | 格式 | 说明 |
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| ---- | ---- | -------------------- | ------------------ |
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| - | BEQ | beq rj, rd, offs16 | |
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| - | BNE | bne rj, rd, offs16 | |
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| - | BLT | blt rj, rd, offs16 | 操作数视为有符号数 |
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| - | BGE | bge rj, rd, offs16 | 操作数视为有符号数 |
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| - | BLTU | bltu rj, rd, of fs16 | |
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| - | BGEU | bgeu rj, rd, offs16 | |
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| √ | B | | |
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| √ | BL | | |
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| √ | JIRL | | |
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### 访存指令
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| √ | 指令 | 格式 | 说明 |
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| ---------- | ---- | ---- | ---- |
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| √ | LD.B | | |
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| √ | LD.H | | |
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| √ | LD.W | | |
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| √ | LD.BU | | |
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| √ | LD.HU | | |
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| √ | ST.B | | |
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| √ | ST.H | | |
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| √ | ST.W | | |
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| | PRELD | | |
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### 原子访存指令
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| √ | 指令 | 格式 | 说明 |
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| ---------- | ---- | ---- | ---- |
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| | LL.W | | |
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| | SC.W | | |
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### 栅障指令
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| √ | 指令 | 格式 | 说明 |
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| ---------- | ---- | ---- | ---- |
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| | DBAR | | |
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| | IBAR | | |
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### 其他杂项指令
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| √ | 指令 | 格式 | 说明 |
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| ---------- | ---- | ---- | ---- |
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| | SYSCALL | | |
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| | BREAK | | |
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| | RDTIMEL.W | | |
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| | RDTIMEH.W | | |
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| | RDCNTID | | |
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lacpu/doc/pic/指令格式.png
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lacpu/doc/龙芯架构32位精简版参考手册.pdf
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