diff --git a/.gitignore b/.gitignore
index d163863..608b1d4 100644
--- a/.gitignore
+++ b/.gitignore
@@ -1 +1,2 @@
+.vscode/
 build/
\ No newline at end of file
diff --git a/CMakeLists.txt b/CMakeLists.txt
index e3ace04..db1f5d9 100644
--- a/CMakeLists.txt
+++ b/CMakeLists.txt
@@ -1,26 +1,72 @@
 cmake_minimum_required(VERSION 3.12)
 cmake_policy(SET CMP0074 NEW)
-project(lacpu)
+project(neula)
 
-# set environment variables for verilator
-# remove if already install one
-set(verilator_DIR "/home/blur/gits/verilator")
-set(ENV{VERILATOR_ROOT} ${verilator_DIR})
+# 为 Verilator 设置环境变量
+if(NOT DEFINED VERILATOR_ROOT)
+  set(ENV{VERILATOR_ROOT} "/home/blur/gits/verilator")
+endif()
 
-find_package(verilator)
+# 设置编译器参数
+if (${CMAKE_BUILD_TYPE} STREQUAL "Debug")
+  message("Turn On Debugger")
+  add_compile_options(-D DEBUG_MODE)
+endif()
+
+
+# ----- ----- 构建虚拟外设 ----- -----
+set(LABUS labus)
+set(LA_BUS_TARGET ${PROJECT_NAME}-bus)
+
+# 包含头文件，以可以利用尖括号获取，辅助队友开发
+include_directories(${CMAKE_SOURCE_DIR}/${LABUS}/include)
+
+# 获取所有的 CXX 源文件
+file(GLOB_RECURSE LABUS_SRC ${CMAKE_SOURCE_DIR}/${LABUS}/*.cc)
+
+add_library(${LA_BUS_TARGET} ${LABUS_SRC})
+link_libraries(${LA_BUS_TARGET})
+
+
+# ----- ----- 构建虚拟处理器 ----- -----
+set(LASIM lasim)
+set(LA_SIM_TARGET ${PROJECT_NAME}-sim)
+
+# 包含头文件，以可以利用尖括号获取，辅助队友开发
+include_directories(${CMAKE_SOURCE_DIR}/${LASIM}/include)
+
+# 获取所有的 CXX 源文件
+file(GLOB_RECURSE LASIM_SRC ${CMAKE_SOURCE_DIR}/${LASIM}/*.cc)
+
+add_executable(${LA_SIM_TARGET} ${LASIM_SRC})
+
+
+# ----- ----- 构建操作系统 ----- -----
+set(LAOS laos)
+add_subdirectory(${LAOS})
+
+
+# ----- ----- 构建 Verilator 项目 ----- -----
+set(LACPU lacpu)
+set(LAVSIM lavsim)
+set(LA_VSIM_TARGET ${PROJECT_NAME}-vsim)
+
+include_directories(${verilator_DIR}/include)
+
+find_package(verilator HINTS $ENV{VERILATOR_ROOT} ${VERILATOR_ROOT})
 
 if (NOT verilator_FOUND)
   message(FATAL_ERROR "Verilator was not found.")
 endif()
 
 # set default top module as top file
-set(VSRC ${CMAKE_SOURCE_DIR}/vsrc/top.v)
+set(VSRC ${CMAKE_SOURCE_DIR}/${LACPU}/top.v)
 
-# get all cxx source files from cxxsrc
-file(GLOB_RECURSE CXXSRC ${CMAKE_SOURCE_DIR}/cxxsrc/*.cc)
+# get all cxx source files from lavsim folder
+file(GLOB_RECURSE LAVSIM_SRC ${CMAKE_SOURCE_DIR}/${LAVSIM}/*.cc)
 
-add_executable(${CMAKE_PROJECT_NAME} ${CXXSRC})
+add_executable(${LA_VSIM_TARGET} ${LAVSIM_SRC})
 
-verilate(${CMAKE_PROJECT_NAME}
-  INCLUDE_DIRS ${CMAKE_SOURCE_DIR}/vsrc ${verilator_DIR}/include
+verilate(${LA_VSIM_TARGET}
+  INCLUDE_DIRS ${CMAKE_SOURCE_DIR}/${LACPU} ${VERILATOR_ROOT}/include
   SOURCES ${VSRC})
\ No newline at end of file
diff --git a/cxxsrc/spec.cc b/Makefile
similarity index 100%
rename from cxxsrc/spec.cc
rename to Makefile
diff --git a/README.md b/README.md
index 76ff027..a6d3b94 100644
--- a/README.md
+++ b/README.md
@@ -1,3 +1,33 @@
-# neulacpu
+# LoongArch CPU
 
-loongarch cpu development repo
+龙芯处理器设计
+
+## 文件组织建议
+
+|文件夹名称|文件夹用处|
+|-|-|
+|lacpu          | 龙芯处理器设计 Verilog |
+|lasim          | 龙芯模拟 软件模拟 C++ |
+|lavsim         | 龙芯模拟 Verilator 模拟 |
+|labus          | 龙芯虚拟外设 |
+|laos           | 龙芯操作系统 |
+
+除了 `lavsim` 和 `lacpu` 是在一起编译成一个文件，其余都会编译成单独的二进制文件
+
+### lacpu
+
+### lasim
+
+`lasim` 模拟龙芯行为，主要用于操作系统的软件模拟，通过软件角度对龙芯的基本硬件特性进行模拟，以辅助操作系统设计。
+
+### lavsim
+
+`lavsim` 主要用于测试 Verilog 设计的正确性。
+
+### labus
+
+`labus` 模拟外设行为，主要用于设计虚拟外设以软件模拟外设行为是否正确。
+
+### laos
+
+`laos` 自主设计操作系统，会参考其他项目进行设计。
\ No newline at end of file
diff --git a/labus/include/sysbus.hh b/labus/include/sysbus.hh
new file mode 100644
index 0000000..ed99f2c
--- /dev/null
+++ b/labus/include/sysbus.hh
@@ -0,0 +1 @@
+int fetch();
\ No newline at end of file
diff --git a/labus/sysbus.cc b/labus/sysbus.cc
new file mode 100644
index 0000000..16a81ef
--- /dev/null
+++ b/labus/sysbus.cc
@@ -0,0 +1,3 @@
+int fetch() {
+    return 0;
+}
\ No newline at end of file
diff --git a/lacpu/top.v b/lacpu/top.v
new file mode 100644
index 0000000..3deb48f
--- /dev/null
+++ b/lacpu/top.v
@@ -0,0 +1,14 @@
+// DESCRIPTION: Verilator: Verilog example module
+//
+// This file ONLY is placed under the Creative Commons Public Domain, for
+// any use, without warranty, 2017 by Wilson Snyder.
+// SPDX-License-Identifier: CC0-1.0
+
+// See also https://verilator.org/guide/latest/examples.html"
+
+module top;
+   initial begin
+      $display("Hello World!");
+      $finish;
+   end
+endmodule
diff --git a/laos/CMakeLists.txt b/laos/CMakeLists.txt
new file mode 100644
index 0000000..ad25ed3
--- /dev/null
+++ b/laos/CMakeLists.txt
@@ -0,0 +1,8 @@
+cmake_minimum_required(VERSION 3.12)
+
+set(LA_OS_TARGET ${PROJECT_NAME}-os)
+
+# get all cxx source files from lasim folder
+file(GLOB_RECURSE LAOS_SRC ${CMAKE_CURRENT_SOURCE_DIR}/*.c)
+
+add_executable(${LA_OS_TARGET} ${LAOS_SRC})
\ No newline at end of file
diff --git a/cxxsrc/main.cc b/laos/main.c
similarity index 100%
rename from cxxsrc/main.cc
rename to laos/main.c
diff --git a/cxxsrc/spec.hh b/lasim/include/spec.hh
similarity index 100%
rename from cxxsrc/spec.hh
rename to lasim/include/spec.hh
diff --git a/lasim/main.cc b/lasim/main.cc
new file mode 100644
index 0000000..2f427c9
--- /dev/null
+++ b/lasim/main.cc
@@ -0,0 +1,11 @@
+#include <sysbus.hh>
+
+#include <iostream>
+
+int main() {
+    fetch();
+#ifdef DEBUG_MODE
+    std::cout << "Hello" << std::endl;
+#endif
+    return 0;
+}
\ No newline at end of file
diff --git a/lasim/spec.cc b/lasim/spec.cc
new file mode 100644
index 0000000..e69de29
diff --git a/lavsim/main.cc b/lavsim/main.cc
new file mode 100644
index 0000000..f2df7b5
--- /dev/null
+++ b/lavsim/main.cc
@@ -0,0 +1,46 @@
+// DESCRIPTION: Verilator: Verilog example module
+//
+// This file ONLY is placed under the Creative Commons Public Domain, for
+// any use, without warranty, 2017 by Wilson Snyder.
+// SPDX-License-Identifier: CC0-1.0
+//======================================================================
+
+// Include common routines
+#include <verilated.h>
+
+// Include model header, generated from Verilating "top.v"
+#include "Vtop.h"
+
+int main(int argc, char** argv) {
+    // See a similar example walkthrough in the verilator manpage.
+
+    // This is intended to be a minimal example.  Before copying this to start a
+    // real project, it is better to start with a more complete example,
+    // e.g. examples/c_tracing.
+
+    // Construct a VerilatedContext to hold simulation time, etc.
+    VerilatedContext* contextp = new VerilatedContext;
+
+    // Pass arguments so Verilated code can see them, e.g. $value$plusargs
+    // This needs to be called before you create any model
+    contextp->commandArgs(argc, argv);
+
+    // Construct the Verilated model, from Vtop.h generated from Verilating "top.v"
+    Vtop* top = new Vtop{contextp};
+
+    // Simulate until $finish
+    while (!contextp->gotFinish()) {
+
+        // Evaluate model
+        top->eval();
+    }
+
+    // Final model cleanup
+    top->final();
+
+    // Destroy model
+    delete top;
+
+    // Return good completion status
+    return 0;
+}
diff --git a/vsrc/top.v b/vsrc/top.v
deleted file mode 100644
index c74fa1f..0000000
--- a/vsrc/top.v
+++ /dev/null
@@ -1,6 +0,0 @@
-module top (
-    input wire i_x,
-    output wire o_y
-);
-    assign o_y = i_x;
-endmodule
\ No newline at end of file