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[Modified] Debug & board test with cache & pass n58 with 40 MHz

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包焕垲
2023-07-22 14:56:53 +08:00
parent a755aae99e
commit 4c9c2ddd78
21 changed files with 6924 additions and 1336 deletions
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57
lacpu/run_vivado/soc_lite.xdc
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@@ -1,5 +1,5 @@
#set_property SEVERITY {Warning} [get_drc_checks RTSTAT-2]
#时钟信号连接
#ʱÖÓÐźÅÁ¬½Ó
set_property PACKAGE_PIN AC19 [get_ports clk]
set_property CLOCK_DEDICATED_ROUTE BACKBONE [get_nets clk]
create_clock -period 10.000 -name clk -waveform {0.000 5.000} [get_ports clk]
@@ -13,18 +13,18 @@ set_property PACKAGE_PIN K23 [get_ports {led[0]}]
set_property PACKAGE_PIN J21 [get_ports {led[1]}]
set_property PACKAGE_PIN H23 [get_ports {led[2]}]
set_property PACKAGE_PIN J19 [get_ports {led[3]}]
set_property PACKAGE_PIN G9 [get_ports {led[4]}]
set_property PACKAGE_PIN G9 [get_ports {led[4]}]
set_property PACKAGE_PIN J26 [get_ports {led[5]}]
set_property PACKAGE_PIN J23 [get_ports {led[6]}]
set_property PACKAGE_PIN J8 [get_ports {led[7]}]
set_property PACKAGE_PIN H8 [get_ports {led[8]}]
set_property PACKAGE_PIN G8 [get_ports {led[9]}]
set_property PACKAGE_PIN F7 [get_ports {led[10]}]
set_property PACKAGE_PIN A4 [get_ports {led[11]}]
set_property PACKAGE_PIN A5 [get_ports {led[12]}]
set_property PACKAGE_PIN A3 [get_ports {led[13]}]
set_property PACKAGE_PIN D5 [get_ports {led[14]}]
set_property PACKAGE_PIN H7 [get_ports {led[15]}]
set_property PACKAGE_PIN J8 [get_ports {led[7]}]
set_property PACKAGE_PIN H8 [get_ports {led[8]}]
set_property PACKAGE_PIN G8 [get_ports {led[9]}]
set_property PACKAGE_PIN F7 [get_ports {led[10]}]
set_property PACKAGE_PIN A4 [get_ports {led[11]}]
set_property PACKAGE_PIN A5 [get_ports {led[12]}]
set_property PACKAGE_PIN A3 [get_ports {led[13]}]
set_property PACKAGE_PIN D5 [get_ports {led[14]}]
set_property PACKAGE_PIN H7 [get_ports {led[15]}]
#led_rg 0/1
set_property PACKAGE_PIN G7 [get_ports {led_rg0[0]}]
@@ -51,6 +51,40 @@ set_property PACKAGE_PIN D4 [get_ports {num_a_g[5]}]
set_property PACKAGE_PIN A2 [get_ports {num_a_g[6]}]
#set_property PACKAGE_PIN C4 :DP
#num_data
set_property PACKAGE_PIN U24 [get_ports {num_data[0]}]
set_property PACKAGE_PIN U25 [get_ports {num_data[1]}]
set_property PACKAGE_PIN U26 [get_ports {num_data[2]}]
set_property PACKAGE_PIN V26 [get_ports {num_data[3]}]
set_property PACKAGE_PIN W26 [get_ports {num_data[4]}]
set_property PACKAGE_PIN AB26 [get_ports {num_data[5]}]
set_property PACKAGE_PIN AC26 [get_ports {num_data[6]}]
set_property PACKAGE_PIN W25 [get_ports {num_data[7]}]
set_property PACKAGE_PIN Y26 [get_ports {num_data[8]}]
set_property PACKAGE_PIN Y25 [get_ports {num_data[9]}]
set_property PACKAGE_PIN V24 [get_ports {num_data[10]}]
set_property PACKAGE_PIN AB25 [get_ports {num_data[11]}]
set_property PACKAGE_PIN AA23 [get_ports {num_data[12]}]
set_property PACKAGE_PIN V23 [get_ports {num_data[13]}]
set_property PACKAGE_PIN W23 [get_ports {num_data[14]}]
set_property PACKAGE_PIN Y22 [get_ports {num_data[15]}]
set_property PACKAGE_PIN Y23 [get_ports {num_data[16]}]
set_property PACKAGE_PIN U22 [get_ports {num_data[17]}]
set_property PACKAGE_PIN V22 [get_ports {num_data[18]}]
set_property PACKAGE_PIN U21 [get_ports {num_data[19]}]
set_property PACKAGE_PIN V21 [get_ports {num_data[20]}]
set_property PACKAGE_PIN T20 [get_ports {num_data[21]}]
set_property PACKAGE_PIN T19 [get_ports {num_data[22]}]
set_property PACKAGE_PIN U15 [get_ports {num_data[23]}]
set_property PACKAGE_PIN U16 [get_ports {num_data[24]}]
set_property PACKAGE_PIN U14 [get_ports {num_data[25]}]
set_property PACKAGE_PIN V14 [get_ports {num_data[26]}]
set_property PACKAGE_PIN V16 [get_ports {num_data[27]}]
set_property PACKAGE_PIN V17 [get_ports {num_data[28]}]
set_property PACKAGE_PIN U17 [get_ports {num_data[29]}]
set_property PACKAGE_PIN R7 [get_ports {num_data[30]}]
set_property PACKAGE_PIN R6 [get_ports {num_data[31]}]
#switch
set_property PACKAGE_PIN AC21 [get_ports {switch[7]}]
set_property PACKAGE_PIN AD24 [get_ports {switch[6]}]
@@ -86,6 +120,7 @@ set_property IOSTANDARD LVCMOS33 [get_ports {switch[*]}]
set_property IOSTANDARD LVCMOS33 [get_ports {btn_key_col[*]}]
set_property IOSTANDARD LVCMOS33 [get_ports {btn_key_row[*]}]
set_property IOSTANDARD LVCMOS33 [get_ports {btn_step[*]}]
set_property IOSTANDARD LVCMOS33 [get_ports {num_data[*]}]
set_false_path -from [get_clocks -of_objects [get_pins pll.clk_pll/inst/plle2_adv_inst/CLKOUT1]] -to [get_clocks -of_objects [get_pins pll.clk_pll/inst/plle2_adv_inst/CLKOUT0]]