[Modified] Debug & board test with cache & pass n58 with 40 MHz
This commit is contained in:
@@ -6,7 +6,7 @@
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<Project Version="7" Minor="44" Path="C:/Users/Unbal/Desktop/LoongArch/neulacpu/lacpu/run_vivado/la32r/la32r.xpr">
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<DefaultLaunch Dir="$PRUNDIR"/>
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<Configuration>
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<Option Name="Id" Val="b071601f1fd144c49e8a7855a3da572b"/>
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<Option Name="Id" Val="5374406f040d4ef0beb6257db957f456"/>
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||||
<Option Name="Part" Val="xc7a200tfbg676-1"/>
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<Option Name="CompiledLibDir" Val="$PCACHEDIR/compile_simlib"/>
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<Option Name="CompiledLibDirXSim" Val=""/>
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@@ -24,36 +24,47 @@
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<Option Name="IPOutputRepo" Val="$PCACHEDIR/ip"/>
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<Option Name="IPCachePermission" Val="read"/>
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<Option Name="IPCachePermission" Val="write"/>
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||||
<Option Name="EnableCoreContainer" Val="TRUE"/>
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||||
<Option Name="EnableCoreContainer" Val="FALSE"/>
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||||
<Option Name="CreateRefXciForCoreContainers" Val="FALSE"/>
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||||
<Option Name="IPUserFilesDir" Val="$PIPUSERFILESDIR"/>
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||||
<Option Name="IPStaticSourceDir" Val="$PIPUSERFILESDIR/ipstatic"/>
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||||
<Option Name="EnableBDX" Val="FALSE"/>
|
||||
<Option Name="WTXSimLaunchSim" Val="37"/>
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||||
<Option Name="WTXSimLaunchSim" Val="0"/>
|
||||
<Option Name="WTModelSimLaunchSim" Val="0"/>
|
||||
<Option Name="WTQuestaLaunchSim" Val="0"/>
|
||||
<Option Name="WTIesLaunchSim" Val="0"/>
|
||||
<Option Name="WTVcsLaunchSim" Val="0"/>
|
||||
<Option Name="WTRivieraLaunchSim" Val="0"/>
|
||||
<Option Name="WTActivehdlLaunchSim" Val="0"/>
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||||
<Option Name="WTXSimExportSim" Val="37"/>
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||||
<Option Name="WTModelSimExportSim" Val="37"/>
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||||
<Option Name="WTQuestaExportSim" Val="37"/>
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||||
<Option Name="WTIesExportSim" Val="37"/>
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||||
<Option Name="WTVcsExportSim" Val="37"/>
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||||
<Option Name="WTRivieraExportSim" Val="37"/>
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||||
<Option Name="WTActivehdlExportSim" Val="37"/>
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||||
<Option Name="WTXSimExportSim" Val="18"/>
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||||
<Option Name="WTModelSimExportSim" Val="18"/>
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||||
<Option Name="WTQuestaExportSim" Val="18"/>
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||||
<Option Name="WTIesExportSim" Val="18"/>
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||||
<Option Name="WTVcsExportSim" Val="18"/>
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||||
<Option Name="WTRivieraExportSim" Val="18"/>
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||||
<Option Name="WTActivehdlExportSim" Val="18"/>
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||||
<Option Name="GenerateIPUpgradeLog" Val="TRUE"/>
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||||
<Option Name="XSimRadix" Val="hex"/>
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||||
<Option Name="XSimTimeUnit" Val="ns"/>
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<Option Name="XSimArrayDisplayLimit" Val="1024"/>
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<Option Name="XSimTraceLimit" Val="65536"/>
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<Option Name="SimTypes" Val="rtl"/>
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<Option Name="SimTypes" Val="bfm"/>
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<Option Name="SimTypes" Val="tlm"/>
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<Option Name="SimTypes" Val="tlm_dpi"/>
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<Option Name="MEMEnableMemoryMapGeneration" Val="TRUE"/>
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<Option Name="DcpsUptoDate" Val="TRUE"/>
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</Configuration>
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||||
<FileSets Version="1" Minor="31">
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<FileSet Name="sources_1" Type="DesignSrcs" RelSrcDir="$PSRCDIR/sources_1">
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||||
<Filter Type="Srcs"/>
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<File Path="$PPRDIR/../../rtl/xilinx_ip/clk_pll/clk_pll.xci">
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<FileInfo>
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<Attr Name="UsedIn" Val="synthesis"/>
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<Attr Name="UsedIn" Val="implementation"/>
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<Attr Name="UsedIn" Val="simulation"/>
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</FileInfo>
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</File>
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<File Path="$PPRDIR/../../rtl/mycpu/alu.v">
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<FileInfo>
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<Attr Name="UsedIn" Val="synthesis"/>
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@@ -272,10 +283,15 @@
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<Attr Name="UsedIn" Val="simulation"/>
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</FileInfo>
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</File>
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<File Path="$PPRDIR/../../../../cdp_ede_local/mycpu_env/func/obj/inst_ram.coe">
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<FileInfo>
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<Attr Name="UsedIn" Val="synthesis"/>
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<Attr Name="UsedIn" Val="simulation"/>
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</FileInfo>
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</File>
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<Config>
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<Option Name="DesignMode" Val="RTL"/>
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<Option Name="TopModule" Val="soc_lite_top"/>
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<Option Name="TopAutoSet" Val="TRUE"/>
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</Config>
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</FileSet>
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<FileSet Name="constrs_1" Type="Constrs" RelSrcDir="$PSRCDIR/constrs_1">
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@@ -292,23 +308,14 @@
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</FileSet>
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<FileSet Name="sim_1" Type="SimulationSrcs" RelSrcDir="$PSRCDIR/sim_1">
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<Filter Type="Srcs"/>
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<File Path="$PPRDIR/sim/cpu_tb_behav.wcfg">
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<FileInfo>
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<Attr Name="UsedIn" Val="simulation"/>
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</FileInfo>
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</File>
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<Config>
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<Option Name="DesignMode" Val="RTL"/>
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<Option Name="TopModule" Val="cache_data_v6"/>
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<Option Name="TopModule" Val="soc_lite_top"/>
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<Option Name="TopLib" Val="xil_defaultlib"/>
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<Option Name="TopAutoSet" Val="TRUE"/>
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<Option Name="TransportPathDelay" Val="0"/>
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<Option Name="TransportIntDelay" Val="0"/>
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<Option Name="SelectedSimModel" Val="rtl"/>
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<Option Name="SrcSet" Val="sources_1"/>
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<Option Name="XSimWcfgFile" Val="$PPRDIR/sim/cpu_tb_behav.wcfg"/>
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<Option Name="xsim.simulate.log_all_signals" Val="true"/>
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<Option Name="xsim.simulate.saif_all_signals" Val="true"/>
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</Config>
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</FileSet>
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<FileSet Name="utils_1" Type="Utils" RelSrcDir="$PSRCDIR/utils_1">
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@@ -318,14 +325,7 @@
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</Config>
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</FileSet>
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<FileSet Name="data_bram_bank" Type="BlockSrcs" RelSrcDir="$PSRCDIR/data_bram_bank">
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<File Path="$PPRDIR/../../rtl/xilinx_ip/data_bram_bank.xcix">
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<FileInfo>
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<Attr Name="UsedIn" Val="synthesis"/>
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<Attr Name="UsedIn" Val="implementation"/>
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<Attr Name="UsedIn" Val="simulation"/>
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</FileInfo>
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</File>
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<File Path="$PPRDIR/../../rtl/xilinx_ip/data_bram_bank/data_bram_bank.xci">
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<File Path="$PPRDIR/../../rtl/xilinx_ip/data_sram_bank/data_bram_bank.xci">
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<FileInfo>
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<Attr Name="UsedIn" Val="synthesis"/>
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<Attr Name="UsedIn" Val="implementation"/>
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@@ -337,19 +337,6 @@
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<Option Name="UseBlackboxStub" Val="1"/>
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</Config>
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</FileSet>
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<FileSet Name="axi_ram" Type="BlockSrcs" RelSrcDir="$PSRCDIR/axi_ram">
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<File Path="$PPRDIR/../../rtl/xilinx_ip/axi_ram/axi_ram.xci">
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<FileInfo>
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<Attr Name="UsedIn" Val="synthesis"/>
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<Attr Name="UsedIn" Val="implementation"/>
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||||
<Attr Name="UsedIn" Val="simulation"/>
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</FileInfo>
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</File>
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<Config>
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<Option Name="TopModule" Val="axi_ram"/>
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<Option Name="UseBlackboxStub" Val="1"/>
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</Config>
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</FileSet>
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||||
<FileSet Name="axi_crossbar_1x2" Type="BlockSrcs" RelSrcDir="$PSRCDIR/axi_crossbar_1x2">
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<File Path="$PPRDIR/../../rtl/xilinx_ip/axi_crossbar_1x2/axi_crossbar_1x2.xci">
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<FileInfo>
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@@ -363,8 +350,8 @@
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<Option Name="UseBlackboxStub" Val="1"/>
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</Config>
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</FileSet>
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<FileSet Name="clk_pll" Type="BlockSrcs" RelSrcDir="$PSRCDIR/clk_pll">
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<File Path="$PPRDIR/../../rtl/xilinx_ip/clk_pll/clk_pll.xci">
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<FileSet Name="axi_ram" Type="BlockSrcs" RelSrcDir="$PSRCDIR/axi_ram">
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<File Path="$PPRDIR/../../rtl/xilinx_ip/axi_ram/axi_ram.xci">
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<FileInfo>
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||||
<Attr Name="UsedIn" Val="synthesis"/>
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<Attr Name="UsedIn" Val="implementation"/>
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@@ -372,7 +359,7 @@
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</FileInfo>
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</File>
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<Config>
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<Option Name="TopModule" Val="clk_pll"/>
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<Option Name="TopModule" Val="axi_ram"/>
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<Option Name="UseBlackboxStub" Val="1"/>
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</Config>
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</FileSet>
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@@ -398,7 +385,9 @@
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<Runs Version="1" Minor="11">
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<Run Id="synth_1" Type="Ft3:Synth" SrcSet="sources_1" Part="xc7a200tfbg676-1" ConstrsSet="constrs_1" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" State="current" Dir="$PRUNDIR/synth_1" IncludeInArchive="true">
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<Strategy Version="1" Minor="2">
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||||
<StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2019"/>
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<StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2019">
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||||
<Desc>Vivado Synthesis Defaults</Desc>
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</StratHandle>
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<Step Id="synth_design"/>
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</Strategy>
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<GeneratedRun Dir="$PRUNDIR" File="gen_run.xml"/>
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@@ -416,16 +405,6 @@
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<Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
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<RQSFiles/>
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</Run>
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<Run Id="axi_ram_synth_1" Type="Ft3:Synth" SrcSet="axi_ram" Part="xc7a200tfbg676-1" ConstrsSet="axi_ram" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" Dir="$PRUNDIR/axi_ram_synth_1" IncludeInArchive="true">
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<Strategy Version="1" Minor="2">
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<StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2019"/>
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<Step Id="synth_design"/>
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</Strategy>
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<GeneratedRun Dir="$PRUNDIR" File="gen_run.xml"/>
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||||
<ReportStrategy Name="Vivado Synthesis Default Reports" Flow="Vivado Synthesis 2019"/>
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||||
<Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
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<RQSFiles/>
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</Run>
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<Run Id="axi_crossbar_1x2_synth_1" Type="Ft3:Synth" SrcSet="axi_crossbar_1x2" Part="xc7a200tfbg676-1" ConstrsSet="axi_crossbar_1x2" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" Dir="$PRUNDIR/axi_crossbar_1x2_synth_1" IncludeInArchive="true">
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<Strategy Version="1" Minor="2">
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<StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2019"/>
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@@ -436,11 +415,9 @@
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<Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
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<RQSFiles/>
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</Run>
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<Run Id="clk_pll_synth_1" Type="Ft3:Synth" SrcSet="clk_pll" Part="xc7a200tfbg676-1" ConstrsSet="clk_pll" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" Dir="$PRUNDIR/clk_pll_synth_1" IncludeInArchive="true">
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<Run Id="axi_ram_synth_1" Type="Ft3:Synth" SrcSet="axi_ram" Part="xc7a200tfbg676-1" ConstrsSet="axi_ram" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" Dir="$PRUNDIR/axi_ram_synth_1" IncludeInArchive="true">
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<Strategy Version="1" Minor="2">
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||||
<StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2019">
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||||
<Desc>Vivado Synthesis Defaults</Desc>
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||||
</StratHandle>
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||||
<StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2019"/>
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<Step Id="synth_design"/>
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</Strategy>
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<GeneratedRun Dir="$PRUNDIR" File="gen_run.xml"/>
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@@ -450,7 +427,9 @@
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</Run>
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<Run Id="impl_1" Type="Ft2:EntireDesign" Part="xc7a200tfbg676-1" ConstrsSet="constrs_1" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" State="current" Dir="$PRUNDIR/impl_1" SynthRun="synth_1" IncludeInArchive="true" GenFullBitstream="true">
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||||
<Strategy Version="1" Minor="2">
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||||
<StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2019"/>
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||||
<StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2019">
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<Desc>Default settings for Implementation.</Desc>
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</StratHandle>
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<Step Id="init_design"/>
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<Step Id="opt_design"/>
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<Step Id="power_opt_design"/>
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@@ -483,23 +462,6 @@
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<Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
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<RQSFiles/>
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||||
</Run>
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||||
<Run Id="axi_ram_impl_1" Type="Ft2:EntireDesign" Part="xc7a200tfbg676-1" ConstrsSet="axi_ram" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" SynthRun="axi_ram_synth_1" IncludeInArchive="false" GenFullBitstream="true">
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<Strategy Version="1" Minor="2">
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||||
<StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2019"/>
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||||
<Step Id="init_design"/>
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<Step Id="opt_design"/>
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<Step Id="power_opt_design"/>
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<Step Id="place_design"/>
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<Step Id="post_place_power_opt_design"/>
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<Step Id="phys_opt_design" EnableStepBool="1"/>
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<Step Id="route_design"/>
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<Step Id="post_route_phys_opt_design"/>
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<Step Id="write_bitstream"/>
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</Strategy>
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||||
<ReportStrategy Name="Vivado Implementation Default Reports" Flow="Vivado Implementation 2019"/>
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||||
<Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
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<RQSFiles/>
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||||
</Run>
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||||
<Run Id="axi_crossbar_1x2_impl_1" Type="Ft2:EntireDesign" Part="xc7a200tfbg676-1" ConstrsSet="axi_crossbar_1x2" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" SynthRun="axi_crossbar_1x2_synth_1" IncludeInArchive="false" GenFullBitstream="true">
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<Strategy Version="1" Minor="2">
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<StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2019"/>
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@@ -517,11 +479,9 @@
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<Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
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<RQSFiles/>
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</Run>
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||||
<Run Id="clk_pll_impl_1" Type="Ft2:EntireDesign" Part="xc7a200tfbg676-1" ConstrsSet="clk_pll" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" SynthRun="clk_pll_synth_1" IncludeInArchive="false" GenFullBitstream="true">
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<Run Id="axi_ram_impl_1" Type="Ft2:EntireDesign" Part="xc7a200tfbg676-1" ConstrsSet="axi_ram" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" SynthRun="axi_ram_synth_1" IncludeInArchive="false" GenFullBitstream="true">
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||||
<Strategy Version="1" Minor="2">
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||||
<StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2019">
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||||
<Desc>Default settings for Implementation.</Desc>
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||||
</StratHandle>
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||||
<StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2019"/>
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||||
<Step Id="init_design"/>
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<Step Id="opt_design"/>
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<Step Id="power_opt_design"/>
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||||
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File diff suppressed because it is too large
Load Diff
@@ -1,43 +0,0 @@
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`timescale 1ns / 1ps
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module cpu_tb(
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);
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reg resetn;
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reg clk;
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wire [31:0] debug_wb_pc;
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wire [ 3:0] debug_wb_rf_wen;
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wire [ 4:0] debug_wb_rf_wnum;
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wire [31:0] debug_wb_rf_wdata;
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initial
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begin
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clk = 1'b0;
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resetn = 1'b0;
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#20;
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resetn = 1'b1;
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#2000;
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$finish;
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end
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always #5 clk=~clk;
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soc_lite_top u_soc_top(
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.resetn (resetn ),
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.clk (clk ),
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.pc ()
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);
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//debug signals
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assign debug_wb_pc = u_soc_top.debug_wb_pc;
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assign debug_wb_rf_wen = u_soc_top.debug_wb_rf_wen;
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assign debug_wb_rf_wnum = u_soc_top.debug_wb_rf_wnum;
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assign debug_wb_rf_wdata = u_soc_top.debug_wb_rf_wdata;
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always @(posedge clk) begin
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$display("PC = 0x%8h, wb_rf_wnum = 0x%2h, wb_rf_wdata = 0x%8h",
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debug_wb_pc, debug_wb_rf_wnum, debug_wb_rf_wdata);
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end
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endmodule
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