[Modified] Debug & board test with cache & pass n58 with 40 MHz
This commit is contained in:
@@ -6,7 +6,7 @@
|
||||
<Project Version="7" Minor="44" Path="C:/Users/Unbal/Desktop/LoongArch/neulacpu/lacpu/run_vivado/la32r/la32r.xpr">
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||||
<DefaultLaunch Dir="$PRUNDIR"/>
|
||||
<Configuration>
|
||||
<Option Name="Id" Val="b071601f1fd144c49e8a7855a3da572b"/>
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||||
<Option Name="Id" Val="5374406f040d4ef0beb6257db957f456"/>
|
||||
<Option Name="Part" Val="xc7a200tfbg676-1"/>
|
||||
<Option Name="CompiledLibDir" Val="$PCACHEDIR/compile_simlib"/>
|
||||
<Option Name="CompiledLibDirXSim" Val=""/>
|
||||
@@ -24,36 +24,47 @@
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<Option Name="IPOutputRepo" Val="$PCACHEDIR/ip"/>
|
||||
<Option Name="IPCachePermission" Val="read"/>
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||||
<Option Name="IPCachePermission" Val="write"/>
|
||||
<Option Name="EnableCoreContainer" Val="TRUE"/>
|
||||
<Option Name="EnableCoreContainer" Val="FALSE"/>
|
||||
<Option Name="CreateRefXciForCoreContainers" Val="FALSE"/>
|
||||
<Option Name="IPUserFilesDir" Val="$PIPUSERFILESDIR"/>
|
||||
<Option Name="IPStaticSourceDir" Val="$PIPUSERFILESDIR/ipstatic"/>
|
||||
<Option Name="EnableBDX" Val="FALSE"/>
|
||||
<Option Name="WTXSimLaunchSim" Val="37"/>
|
||||
<Option Name="WTXSimLaunchSim" Val="0"/>
|
||||
<Option Name="WTModelSimLaunchSim" Val="0"/>
|
||||
<Option Name="WTQuestaLaunchSim" Val="0"/>
|
||||
<Option Name="WTIesLaunchSim" Val="0"/>
|
||||
<Option Name="WTVcsLaunchSim" Val="0"/>
|
||||
<Option Name="WTRivieraLaunchSim" Val="0"/>
|
||||
<Option Name="WTActivehdlLaunchSim" Val="0"/>
|
||||
<Option Name="WTXSimExportSim" Val="37"/>
|
||||
<Option Name="WTModelSimExportSim" Val="37"/>
|
||||
<Option Name="WTQuestaExportSim" Val="37"/>
|
||||
<Option Name="WTIesExportSim" Val="37"/>
|
||||
<Option Name="WTVcsExportSim" Val="37"/>
|
||||
<Option Name="WTRivieraExportSim" Val="37"/>
|
||||
<Option Name="WTActivehdlExportSim" Val="37"/>
|
||||
<Option Name="WTXSimExportSim" Val="18"/>
|
||||
<Option Name="WTModelSimExportSim" Val="18"/>
|
||||
<Option Name="WTQuestaExportSim" Val="18"/>
|
||||
<Option Name="WTIesExportSim" Val="18"/>
|
||||
<Option Name="WTVcsExportSim" Val="18"/>
|
||||
<Option Name="WTRivieraExportSim" Val="18"/>
|
||||
<Option Name="WTActivehdlExportSim" Val="18"/>
|
||||
<Option Name="GenerateIPUpgradeLog" Val="TRUE"/>
|
||||
<Option Name="XSimRadix" Val="hex"/>
|
||||
<Option Name="XSimTimeUnit" Val="ns"/>
|
||||
<Option Name="XSimArrayDisplayLimit" Val="1024"/>
|
||||
<Option Name="XSimTraceLimit" Val="65536"/>
|
||||
<Option Name="SimTypes" Val="rtl"/>
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||||
<Option Name="SimTypes" Val="bfm"/>
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||||
<Option Name="SimTypes" Val="tlm"/>
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||||
<Option Name="SimTypes" Val="tlm_dpi"/>
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||||
<Option Name="MEMEnableMemoryMapGeneration" Val="TRUE"/>
|
||||
<Option Name="DcpsUptoDate" Val="TRUE"/>
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||||
</Configuration>
|
||||
<FileSets Version="1" Minor="31">
|
||||
<FileSet Name="sources_1" Type="DesignSrcs" RelSrcDir="$PSRCDIR/sources_1">
|
||||
<Filter Type="Srcs"/>
|
||||
<File Path="$PPRDIR/../../rtl/xilinx_ip/clk_pll/clk_pll.xci">
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||||
<FileInfo>
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||||
<Attr Name="UsedIn" Val="synthesis"/>
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||||
<Attr Name="UsedIn" Val="implementation"/>
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||||
<Attr Name="UsedIn" Val="simulation"/>
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||||
</FileInfo>
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||||
</File>
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||||
<File Path="$PPRDIR/../../rtl/mycpu/alu.v">
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||||
<FileInfo>
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||||
<Attr Name="UsedIn" Val="synthesis"/>
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@@ -272,10 +283,15 @@
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<Attr Name="UsedIn" Val="simulation"/>
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</FileInfo>
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||||
</File>
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||||
<File Path="$PPRDIR/../../../../cdp_ede_local/mycpu_env/func/obj/inst_ram.coe">
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||||
<FileInfo>
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||||
<Attr Name="UsedIn" Val="synthesis"/>
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||||
<Attr Name="UsedIn" Val="simulation"/>
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||||
</FileInfo>
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</File>
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||||
<Config>
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||||
<Option Name="DesignMode" Val="RTL"/>
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||||
<Option Name="TopModule" Val="soc_lite_top"/>
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||||
<Option Name="TopAutoSet" Val="TRUE"/>
|
||||
</Config>
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||||
</FileSet>
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||||
<FileSet Name="constrs_1" Type="Constrs" RelSrcDir="$PSRCDIR/constrs_1">
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||||
@@ -292,23 +308,14 @@
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</FileSet>
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||||
<FileSet Name="sim_1" Type="SimulationSrcs" RelSrcDir="$PSRCDIR/sim_1">
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||||
<Filter Type="Srcs"/>
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||||
<File Path="$PPRDIR/sim/cpu_tb_behav.wcfg">
|
||||
<FileInfo>
|
||||
<Attr Name="UsedIn" Val="simulation"/>
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||||
</FileInfo>
|
||||
</File>
|
||||
<Config>
|
||||
<Option Name="DesignMode" Val="RTL"/>
|
||||
<Option Name="TopModule" Val="cache_data_v6"/>
|
||||
<Option Name="TopModule" Val="soc_lite_top"/>
|
||||
<Option Name="TopLib" Val="xil_defaultlib"/>
|
||||
<Option Name="TopAutoSet" Val="TRUE"/>
|
||||
<Option Name="TransportPathDelay" Val="0"/>
|
||||
<Option Name="TransportIntDelay" Val="0"/>
|
||||
<Option Name="SelectedSimModel" Val="rtl"/>
|
||||
<Option Name="SrcSet" Val="sources_1"/>
|
||||
<Option Name="XSimWcfgFile" Val="$PPRDIR/sim/cpu_tb_behav.wcfg"/>
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||||
<Option Name="xsim.simulate.log_all_signals" Val="true"/>
|
||||
<Option Name="xsim.simulate.saif_all_signals" Val="true"/>
|
||||
</Config>
|
||||
</FileSet>
|
||||
<FileSet Name="utils_1" Type="Utils" RelSrcDir="$PSRCDIR/utils_1">
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||||
@@ -318,14 +325,7 @@
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</Config>
|
||||
</FileSet>
|
||||
<FileSet Name="data_bram_bank" Type="BlockSrcs" RelSrcDir="$PSRCDIR/data_bram_bank">
|
||||
<File Path="$PPRDIR/../../rtl/xilinx_ip/data_bram_bank.xcix">
|
||||
<FileInfo>
|
||||
<Attr Name="UsedIn" Val="synthesis"/>
|
||||
<Attr Name="UsedIn" Val="implementation"/>
|
||||
<Attr Name="UsedIn" Val="simulation"/>
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||||
</FileInfo>
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||||
</File>
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||||
<File Path="$PPRDIR/../../rtl/xilinx_ip/data_bram_bank/data_bram_bank.xci">
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||||
<File Path="$PPRDIR/../../rtl/xilinx_ip/data_sram_bank/data_bram_bank.xci">
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||||
<FileInfo>
|
||||
<Attr Name="UsedIn" Val="synthesis"/>
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||||
<Attr Name="UsedIn" Val="implementation"/>
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||||
@@ -337,19 +337,6 @@
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||||
<Option Name="UseBlackboxStub" Val="1"/>
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||||
</Config>
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||||
</FileSet>
|
||||
<FileSet Name="axi_ram" Type="BlockSrcs" RelSrcDir="$PSRCDIR/axi_ram">
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||||
<File Path="$PPRDIR/../../rtl/xilinx_ip/axi_ram/axi_ram.xci">
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||||
<FileInfo>
|
||||
<Attr Name="UsedIn" Val="synthesis"/>
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||||
<Attr Name="UsedIn" Val="implementation"/>
|
||||
<Attr Name="UsedIn" Val="simulation"/>
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||||
</FileInfo>
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||||
</File>
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||||
<Config>
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||||
<Option Name="TopModule" Val="axi_ram"/>
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||||
<Option Name="UseBlackboxStub" Val="1"/>
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||||
</Config>
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||||
</FileSet>
|
||||
<FileSet Name="axi_crossbar_1x2" Type="BlockSrcs" RelSrcDir="$PSRCDIR/axi_crossbar_1x2">
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||||
<File Path="$PPRDIR/../../rtl/xilinx_ip/axi_crossbar_1x2/axi_crossbar_1x2.xci">
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||||
<FileInfo>
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||||
@@ -363,8 +350,8 @@
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||||
<Option Name="UseBlackboxStub" Val="1"/>
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||||
</Config>
|
||||
</FileSet>
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||||
<FileSet Name="clk_pll" Type="BlockSrcs" RelSrcDir="$PSRCDIR/clk_pll">
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||||
<File Path="$PPRDIR/../../rtl/xilinx_ip/clk_pll/clk_pll.xci">
|
||||
<FileSet Name="axi_ram" Type="BlockSrcs" RelSrcDir="$PSRCDIR/axi_ram">
|
||||
<File Path="$PPRDIR/../../rtl/xilinx_ip/axi_ram/axi_ram.xci">
|
||||
<FileInfo>
|
||||
<Attr Name="UsedIn" Val="synthesis"/>
|
||||
<Attr Name="UsedIn" Val="implementation"/>
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||||
@@ -372,7 +359,7 @@
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||||
</FileInfo>
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||||
</File>
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||||
<Config>
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||||
<Option Name="TopModule" Val="clk_pll"/>
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||||
<Option Name="TopModule" Val="axi_ram"/>
|
||||
<Option Name="UseBlackboxStub" Val="1"/>
|
||||
</Config>
|
||||
</FileSet>
|
||||
@@ -398,7 +385,9 @@
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||||
<Runs Version="1" Minor="11">
|
||||
<Run Id="synth_1" Type="Ft3:Synth" SrcSet="sources_1" Part="xc7a200tfbg676-1" ConstrsSet="constrs_1" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" State="current" Dir="$PRUNDIR/synth_1" IncludeInArchive="true">
|
||||
<Strategy Version="1" Minor="2">
|
||||
<StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2019"/>
|
||||
<StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2019">
|
||||
<Desc>Vivado Synthesis Defaults</Desc>
|
||||
</StratHandle>
|
||||
<Step Id="synth_design"/>
|
||||
</Strategy>
|
||||
<GeneratedRun Dir="$PRUNDIR" File="gen_run.xml"/>
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||||
@@ -416,16 +405,6 @@
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||||
<Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
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||||
<RQSFiles/>
|
||||
</Run>
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||||
<Run Id="axi_ram_synth_1" Type="Ft3:Synth" SrcSet="axi_ram" Part="xc7a200tfbg676-1" ConstrsSet="axi_ram" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" Dir="$PRUNDIR/axi_ram_synth_1" IncludeInArchive="true">
|
||||
<Strategy Version="1" Minor="2">
|
||||
<StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2019"/>
|
||||
<Step Id="synth_design"/>
|
||||
</Strategy>
|
||||
<GeneratedRun Dir="$PRUNDIR" File="gen_run.xml"/>
|
||||
<ReportStrategy Name="Vivado Synthesis Default Reports" Flow="Vivado Synthesis 2019"/>
|
||||
<Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
|
||||
<RQSFiles/>
|
||||
</Run>
|
||||
<Run Id="axi_crossbar_1x2_synth_1" Type="Ft3:Synth" SrcSet="axi_crossbar_1x2" Part="xc7a200tfbg676-1" ConstrsSet="axi_crossbar_1x2" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" Dir="$PRUNDIR/axi_crossbar_1x2_synth_1" IncludeInArchive="true">
|
||||
<Strategy Version="1" Minor="2">
|
||||
<StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2019"/>
|
||||
@@ -436,11 +415,9 @@
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||||
<Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
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||||
<RQSFiles/>
|
||||
</Run>
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||||
<Run Id="clk_pll_synth_1" Type="Ft3:Synth" SrcSet="clk_pll" Part="xc7a200tfbg676-1" ConstrsSet="clk_pll" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" Dir="$PRUNDIR/clk_pll_synth_1" IncludeInArchive="true">
|
||||
<Run Id="axi_ram_synth_1" Type="Ft3:Synth" SrcSet="axi_ram" Part="xc7a200tfbg676-1" ConstrsSet="axi_ram" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" Dir="$PRUNDIR/axi_ram_synth_1" IncludeInArchive="true">
|
||||
<Strategy Version="1" Minor="2">
|
||||
<StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2019">
|
||||
<Desc>Vivado Synthesis Defaults</Desc>
|
||||
</StratHandle>
|
||||
<StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2019"/>
|
||||
<Step Id="synth_design"/>
|
||||
</Strategy>
|
||||
<GeneratedRun Dir="$PRUNDIR" File="gen_run.xml"/>
|
||||
@@ -450,7 +427,9 @@
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||||
</Run>
|
||||
<Run Id="impl_1" Type="Ft2:EntireDesign" Part="xc7a200tfbg676-1" ConstrsSet="constrs_1" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" State="current" Dir="$PRUNDIR/impl_1" SynthRun="synth_1" IncludeInArchive="true" GenFullBitstream="true">
|
||||
<Strategy Version="1" Minor="2">
|
||||
<StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2019"/>
|
||||
<StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2019">
|
||||
<Desc>Default settings for Implementation.</Desc>
|
||||
</StratHandle>
|
||||
<Step Id="init_design"/>
|
||||
<Step Id="opt_design"/>
|
||||
<Step Id="power_opt_design"/>
|
||||
@@ -483,23 +462,6 @@
|
||||
<Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
|
||||
<RQSFiles/>
|
||||
</Run>
|
||||
<Run Id="axi_ram_impl_1" Type="Ft2:EntireDesign" Part="xc7a200tfbg676-1" ConstrsSet="axi_ram" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" SynthRun="axi_ram_synth_1" IncludeInArchive="false" GenFullBitstream="true">
|
||||
<Strategy Version="1" Minor="2">
|
||||
<StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2019"/>
|
||||
<Step Id="init_design"/>
|
||||
<Step Id="opt_design"/>
|
||||
<Step Id="power_opt_design"/>
|
||||
<Step Id="place_design"/>
|
||||
<Step Id="post_place_power_opt_design"/>
|
||||
<Step Id="phys_opt_design" EnableStepBool="1"/>
|
||||
<Step Id="route_design"/>
|
||||
<Step Id="post_route_phys_opt_design"/>
|
||||
<Step Id="write_bitstream"/>
|
||||
</Strategy>
|
||||
<ReportStrategy Name="Vivado Implementation Default Reports" Flow="Vivado Implementation 2019"/>
|
||||
<Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
|
||||
<RQSFiles/>
|
||||
</Run>
|
||||
<Run Id="axi_crossbar_1x2_impl_1" Type="Ft2:EntireDesign" Part="xc7a200tfbg676-1" ConstrsSet="axi_crossbar_1x2" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" SynthRun="axi_crossbar_1x2_synth_1" IncludeInArchive="false" GenFullBitstream="true">
|
||||
<Strategy Version="1" Minor="2">
|
||||
<StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2019"/>
|
||||
@@ -517,11 +479,9 @@
|
||||
<Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
|
||||
<RQSFiles/>
|
||||
</Run>
|
||||
<Run Id="clk_pll_impl_1" Type="Ft2:EntireDesign" Part="xc7a200tfbg676-1" ConstrsSet="clk_pll" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" SynthRun="clk_pll_synth_1" IncludeInArchive="false" GenFullBitstream="true">
|
||||
<Run Id="axi_ram_impl_1" Type="Ft2:EntireDesign" Part="xc7a200tfbg676-1" ConstrsSet="axi_ram" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" SynthRun="axi_ram_synth_1" IncludeInArchive="false" GenFullBitstream="true">
|
||||
<Strategy Version="1" Minor="2">
|
||||
<StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2019">
|
||||
<Desc>Default settings for Implementation.</Desc>
|
||||
</StratHandle>
|
||||
<StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2019"/>
|
||||
<Step Id="init_design"/>
|
||||
<Step Id="opt_design"/>
|
||||
<Step Id="power_opt_design"/>
|
||||
|
||||
File diff suppressed because it is too large
Load Diff
@@ -1,43 +0,0 @@
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`timescale 1ns / 1ps
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module cpu_tb(
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|
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);
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reg resetn;
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reg clk;
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wire [31:0] debug_wb_pc;
|
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wire [ 3:0] debug_wb_rf_wen;
|
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wire [ 4:0] debug_wb_rf_wnum;
|
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wire [31:0] debug_wb_rf_wdata;
|
||||
|
||||
initial
|
||||
begin
|
||||
clk = 1'b0;
|
||||
resetn = 1'b0;
|
||||
#20;
|
||||
resetn = 1'b1;
|
||||
#2000;
|
||||
$finish;
|
||||
end
|
||||
always #5 clk=~clk;
|
||||
|
||||
soc_lite_top u_soc_top(
|
||||
.resetn (resetn ),
|
||||
.clk (clk ),
|
||||
|
||||
.pc ()
|
||||
);
|
||||
|
||||
//debug signals
|
||||
assign debug_wb_pc = u_soc_top.debug_wb_pc;
|
||||
assign debug_wb_rf_wen = u_soc_top.debug_wb_rf_wen;
|
||||
assign debug_wb_rf_wnum = u_soc_top.debug_wb_rf_wnum;
|
||||
assign debug_wb_rf_wdata = u_soc_top.debug_wb_rf_wdata;
|
||||
|
||||
always @(posedge clk) begin
|
||||
$display("PC = 0x%8h, wb_rf_wnum = 0x%2h, wb_rf_wdata = 0x%8h",
|
||||
debug_wb_pc, debug_wb_rf_wnum, debug_wb_rf_wdata);
|
||||
end
|
||||
|
||||
|
||||
endmodule
|
||||
@@ -1,5 +1,5 @@
|
||||
#set_property SEVERITY {Warning} [get_drc_checks RTSTAT-2]
|
||||
#时钟信号连接
|
||||
#ʱÖÓÐźÅÁ¬½Ó
|
||||
set_property PACKAGE_PIN AC19 [get_ports clk]
|
||||
set_property CLOCK_DEDICATED_ROUTE BACKBONE [get_nets clk]
|
||||
create_clock -period 10.000 -name clk -waveform {0.000 5.000} [get_ports clk]
|
||||
@@ -13,18 +13,18 @@ set_property PACKAGE_PIN K23 [get_ports {led[0]}]
|
||||
set_property PACKAGE_PIN J21 [get_ports {led[1]}]
|
||||
set_property PACKAGE_PIN H23 [get_ports {led[2]}]
|
||||
set_property PACKAGE_PIN J19 [get_ports {led[3]}]
|
||||
set_property PACKAGE_PIN G9 [get_ports {led[4]}]
|
||||
set_property PACKAGE_PIN G9 [get_ports {led[4]}]
|
||||
set_property PACKAGE_PIN J26 [get_ports {led[5]}]
|
||||
set_property PACKAGE_PIN J23 [get_ports {led[6]}]
|
||||
set_property PACKAGE_PIN J8 [get_ports {led[7]}]
|
||||
set_property PACKAGE_PIN H8 [get_ports {led[8]}]
|
||||
set_property PACKAGE_PIN G8 [get_ports {led[9]}]
|
||||
set_property PACKAGE_PIN F7 [get_ports {led[10]}]
|
||||
set_property PACKAGE_PIN A4 [get_ports {led[11]}]
|
||||
set_property PACKAGE_PIN A5 [get_ports {led[12]}]
|
||||
set_property PACKAGE_PIN A3 [get_ports {led[13]}]
|
||||
set_property PACKAGE_PIN D5 [get_ports {led[14]}]
|
||||
set_property PACKAGE_PIN H7 [get_ports {led[15]}]
|
||||
set_property PACKAGE_PIN J8 [get_ports {led[7]}]
|
||||
set_property PACKAGE_PIN H8 [get_ports {led[8]}]
|
||||
set_property PACKAGE_PIN G8 [get_ports {led[9]}]
|
||||
set_property PACKAGE_PIN F7 [get_ports {led[10]}]
|
||||
set_property PACKAGE_PIN A4 [get_ports {led[11]}]
|
||||
set_property PACKAGE_PIN A5 [get_ports {led[12]}]
|
||||
set_property PACKAGE_PIN A3 [get_ports {led[13]}]
|
||||
set_property PACKAGE_PIN D5 [get_ports {led[14]}]
|
||||
set_property PACKAGE_PIN H7 [get_ports {led[15]}]
|
||||
|
||||
#led_rg 0/1
|
||||
set_property PACKAGE_PIN G7 [get_ports {led_rg0[0]}]
|
||||
@@ -51,6 +51,40 @@ set_property PACKAGE_PIN D4 [get_ports {num_a_g[5]}]
|
||||
set_property PACKAGE_PIN A2 [get_ports {num_a_g[6]}]
|
||||
#set_property PACKAGE_PIN C4 :DP
|
||||
|
||||
#num_data
|
||||
set_property PACKAGE_PIN U24 [get_ports {num_data[0]}]
|
||||
set_property PACKAGE_PIN U25 [get_ports {num_data[1]}]
|
||||
set_property PACKAGE_PIN U26 [get_ports {num_data[2]}]
|
||||
set_property PACKAGE_PIN V26 [get_ports {num_data[3]}]
|
||||
set_property PACKAGE_PIN W26 [get_ports {num_data[4]}]
|
||||
set_property PACKAGE_PIN AB26 [get_ports {num_data[5]}]
|
||||
set_property PACKAGE_PIN AC26 [get_ports {num_data[6]}]
|
||||
set_property PACKAGE_PIN W25 [get_ports {num_data[7]}]
|
||||
set_property PACKAGE_PIN Y26 [get_ports {num_data[8]}]
|
||||
set_property PACKAGE_PIN Y25 [get_ports {num_data[9]}]
|
||||
set_property PACKAGE_PIN V24 [get_ports {num_data[10]}]
|
||||
set_property PACKAGE_PIN AB25 [get_ports {num_data[11]}]
|
||||
set_property PACKAGE_PIN AA23 [get_ports {num_data[12]}]
|
||||
set_property PACKAGE_PIN V23 [get_ports {num_data[13]}]
|
||||
set_property PACKAGE_PIN W23 [get_ports {num_data[14]}]
|
||||
set_property PACKAGE_PIN Y22 [get_ports {num_data[15]}]
|
||||
set_property PACKAGE_PIN Y23 [get_ports {num_data[16]}]
|
||||
set_property PACKAGE_PIN U22 [get_ports {num_data[17]}]
|
||||
set_property PACKAGE_PIN V22 [get_ports {num_data[18]}]
|
||||
set_property PACKAGE_PIN U21 [get_ports {num_data[19]}]
|
||||
set_property PACKAGE_PIN V21 [get_ports {num_data[20]}]
|
||||
set_property PACKAGE_PIN T20 [get_ports {num_data[21]}]
|
||||
set_property PACKAGE_PIN T19 [get_ports {num_data[22]}]
|
||||
set_property PACKAGE_PIN U15 [get_ports {num_data[23]}]
|
||||
set_property PACKAGE_PIN U16 [get_ports {num_data[24]}]
|
||||
set_property PACKAGE_PIN U14 [get_ports {num_data[25]}]
|
||||
set_property PACKAGE_PIN V14 [get_ports {num_data[26]}]
|
||||
set_property PACKAGE_PIN V16 [get_ports {num_data[27]}]
|
||||
set_property PACKAGE_PIN V17 [get_ports {num_data[28]}]
|
||||
set_property PACKAGE_PIN U17 [get_ports {num_data[29]}]
|
||||
set_property PACKAGE_PIN R7 [get_ports {num_data[30]}]
|
||||
set_property PACKAGE_PIN R6 [get_ports {num_data[31]}]
|
||||
|
||||
#switch
|
||||
set_property PACKAGE_PIN AC21 [get_ports {switch[7]}]
|
||||
set_property PACKAGE_PIN AD24 [get_ports {switch[6]}]
|
||||
@@ -86,6 +120,7 @@ set_property IOSTANDARD LVCMOS33 [get_ports {switch[*]}]
|
||||
set_property IOSTANDARD LVCMOS33 [get_ports {btn_key_col[*]}]
|
||||
set_property IOSTANDARD LVCMOS33 [get_ports {btn_key_row[*]}]
|
||||
set_property IOSTANDARD LVCMOS33 [get_ports {btn_step[*]}]
|
||||
set_property IOSTANDARD LVCMOS33 [get_ports {num_data[*]}]
|
||||
|
||||
|
||||
set_false_path -from [get_clocks -of_objects [get_pins pll.clk_pll/inst/plle2_adv_inst/CLKOUT1]] -to [get_clocks -of_objects [get_pins pll.clk_pll/inst/plle2_adv_inst/CLKOUT0]]
|
||||
|
||||
Reference in New Issue
Block a user