[Modified] Debug & board test with cache & pass n58 with 40 MHz
This commit is contained in:
BIN
lacpu/rtl/xilinx_ip/data_sram_bank/data_bram_bank.dcp
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lacpu/rtl/xilinx_ip/data_sram_bank/data_bram_bank.dcp
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lacpu/rtl/xilinx_ip/data_sram_bank/data_bram_bank.xci
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lacpu/rtl/xilinx_ip/data_sram_bank/data_bram_bank.xci
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@@ -0,0 +1,309 @@
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<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.AXI_Slave_Type">Memory_Slave</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.AXI_Type">AXI4_Full</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Additional_Inputs_for_Power_Estimation">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Algorithm">Minimum_Area</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Assume_Synchronous_Clk">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Byte_Size">9</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CTRL_ECC_ALGO">NONE</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Coe_File">no_coe_file_loaded</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Collision_Warnings">ALL</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Component_Name">data_bram_bank</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Disable_Collision_Warnings">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Disable_Out_of_Range_Warnings">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.ECC">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.EN_DEEPSLEEP_PIN">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.EN_ECC_PIPE">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.EN_SAFETY_CKT">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.EN_SHUTDOWN_PIN">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.EN_SLEEP_PIN">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Enable_32bit_Address">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Enable_A">Use_ENA_Pin</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Enable_B">Always_Enabled</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Error_Injection_Type">Single_Bit_Error_Injection</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Fill_Remaining_Memory_Locations">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Interface_Type">Native</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Load_Init_File">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MEM_FILE">no_mem_loaded</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Memory_Type">Single_Port_RAM</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Operating_Mode_A">WRITE_FIRST</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Operating_Mode_B">WRITE_FIRST</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Output_Reset_Value_A">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Output_Reset_Value_B">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.PRIM_type_to_Implement">BRAM</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Pipeline_Stages">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Port_A_Clock">100</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Port_A_Enable_Rate">100</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Port_A_Write_Rate">50</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Port_B_Clock">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Port_B_Enable_Rate">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Port_B_Write_Rate">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Primitive">8kx2</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.RD_ADDR_CHNG_A">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.RD_ADDR_CHNG_B">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.READ_LATENCY_A">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.READ_LATENCY_B">1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Read_Width_A">32</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Read_Width_B">32</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Register_PortA_Output_of_Memory_Core">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Register_PortA_Output_of_Memory_Primitives">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Register_PortB_Output_of_Memory_Core">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Register_PortB_Output_of_Memory_Primitives">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Remaining_Memory_Locations">0</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Reset_Memory_Latch_A">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Reset_Memory_Latch_B">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Reset_Priority_A">CE</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Reset_Priority_B">CE</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Reset_Type">SYNC</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Use_AXI_ID">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Use_Byte_Write_Enable">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Use_Error_Injection_Pins">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Use_REGCEA_Pin">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Use_REGCEB_Pin">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Use_RSTA_Pin">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Use_RSTB_Pin">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Write_Depth_A">64</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Write_Width_A">32</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.Write_Width_B">32</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.ecctype">No_ECC</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.register_porta_input_of_softecc">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.register_portb_output_of_softecc">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.softecc">false</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.use_bram_block">Stand_Alone</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.ARCHITECTURE">artix7</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.BASE_BOARD_PART"/>
|
||||
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.BOARD_CONNECTIONS"/>
|
||||
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.DEVICE">xc7a200t</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.PACKAGE">fbg676</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.PREFHDL">VERILOG</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.SILICON_REVISION"/>
|
||||
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.SIMULATOR_LANGUAGE">MIXED</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.SPEEDGRADE">-1</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.STATIC_POWER"/>
|
||||
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.TEMPERATURE_GRADE"/>
|
||||
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.USE_RDI_CUSTOMIZATION">TRUE</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.USE_RDI_GENERATION">TRUE</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.IPCONTEXT">IP_Flow</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.IPREVISION">4</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.MANAGED">TRUE</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.OUTPUTDIR">.</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SELECTEDSIMMODEL"/>
|
||||
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SHAREDDIR">.</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SWVERSION">2019.2</spirit:configurableElementValue>
|
||||
<spirit:configurableElementValue spirit:referenceId="RUNTIME_PARAM.SYNTHESISFLOW">OUT_OF_CONTEXT</spirit:configurableElementValue>
|
||||
</spirit:configurableElementValues>
|
||||
<spirit:vendorExtensions>
|
||||
<xilinx:componentInstanceExtensions>
|
||||
<xilinx:configElementInfos>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AXILITE_SLAVE_S_AXI.ADDR_WIDTH" xilinx:valueSource="auto"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AXILITE_SLAVE_S_AXI.ARUSER_WIDTH" xilinx:valueSource="constant"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AXILITE_SLAVE_S_AXI.AWUSER_WIDTH" xilinx:valueSource="constant"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AXILITE_SLAVE_S_AXI.BUSER_WIDTH" xilinx:valueSource="constant"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AXILITE_SLAVE_S_AXI.DATA_WIDTH" xilinx:valueSource="auto"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AXILITE_SLAVE_S_AXI.HAS_BRESP" xilinx:valueSource="auto"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AXILITE_SLAVE_S_AXI.HAS_BURST" xilinx:valueSource="auto"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AXILITE_SLAVE_S_AXI.HAS_CACHE" xilinx:valueSource="constant"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AXILITE_SLAVE_S_AXI.HAS_LOCK" xilinx:valueSource="constant"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AXILITE_SLAVE_S_AXI.HAS_PROT" xilinx:valueSource="constant"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AXILITE_SLAVE_S_AXI.HAS_QOS" xilinx:valueSource="constant"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AXILITE_SLAVE_S_AXI.HAS_REGION" xilinx:valueSource="constant"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AXILITE_SLAVE_S_AXI.HAS_RRESP" xilinx:valueSource="auto"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AXILITE_SLAVE_S_AXI.HAS_WSTRB" xilinx:valueSource="auto"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AXILITE_SLAVE_S_AXI.PROTOCOL" xilinx:valueSource="auto"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AXILITE_SLAVE_S_AXI.RUSER_WIDTH" xilinx:valueSource="constant"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AXILITE_SLAVE_S_AXI.WUSER_WIDTH" xilinx:valueSource="constant"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AXI_SLAVE_S_AXI.ADDR_WIDTH" xilinx:valueSource="auto"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AXI_SLAVE_S_AXI.ARUSER_WIDTH" xilinx:valueSource="constant"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AXI_SLAVE_S_AXI.AWUSER_WIDTH" xilinx:valueSource="constant"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AXI_SLAVE_S_AXI.BUSER_WIDTH" xilinx:valueSource="constant"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AXI_SLAVE_S_AXI.DATA_WIDTH" xilinx:valueSource="auto"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AXI_SLAVE_S_AXI.HAS_BRESP" xilinx:valueSource="auto"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AXI_SLAVE_S_AXI.HAS_BURST" xilinx:valueSource="auto"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AXI_SLAVE_S_AXI.HAS_CACHE" xilinx:valueSource="constant"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AXI_SLAVE_S_AXI.HAS_LOCK" xilinx:valueSource="constant"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AXI_SLAVE_S_AXI.HAS_PROT" xilinx:valueSource="constant"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AXI_SLAVE_S_AXI.HAS_QOS" xilinx:valueSource="constant"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AXI_SLAVE_S_AXI.HAS_REGION" xilinx:valueSource="constant"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AXI_SLAVE_S_AXI.HAS_RRESP" xilinx:valueSource="auto"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AXI_SLAVE_S_AXI.HAS_WSTRB" xilinx:valueSource="auto"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AXI_SLAVE_S_AXI.PROTOCOL" xilinx:valueSource="auto"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AXI_SLAVE_S_AXI.RUSER_WIDTH" xilinx:valueSource="constant"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="BUSIFPARAM_VALUE.AXI_SLAVE_S_AXI.WUSER_WIDTH" xilinx:valueSource="constant"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Read_Width_A" xilinx:valueSource="user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Read_Width_B" xilinx:valueSource="user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Register_PortA_Output_of_Memory_Primitives" xilinx:valueSource="user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Write_Depth_A" xilinx:valueSource="user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Write_Width_A" xilinx:valueSource="user"/>
|
||||
<xilinx:configElementInfo xilinx:referenceId="PARAM_VALUE.Write_Width_B" xilinx:valueSource="user"/>
|
||||
</xilinx:configElementInfos>
|
||||
</xilinx:componentInstanceExtensions>
|
||||
</spirit:vendorExtensions>
|
||||
</spirit:componentInstance>
|
||||
</spirit:componentInstances>
|
||||
</spirit:design>
|
||||
4303
lacpu/rtl/xilinx_ip/data_sram_bank/data_bram_bank.xml
Normal file
4303
lacpu/rtl/xilinx_ip/data_sram_bank/data_bram_bank.xml
Normal file
File diff suppressed because it is too large
Load Diff
55
lacpu/rtl/xilinx_ip/data_sram_bank/data_bram_bank_ooc.xdc
Normal file
55
lacpu/rtl/xilinx_ip/data_sram_bank/data_bram_bank_ooc.xdc
Normal file
@@ -0,0 +1,55 @@
|
||||
################################################################################
|
||||
#
|
||||
# (c) Copyright 2002 - 2013 Xilinx, Inc. All rights reserved.
|
||||
#
|
||||
# This file contains confidential and proprietary information
|
||||
# of Xilinx, Inc. and is protected under U.S. and
|
||||
# international copyright and other intellectual property
|
||||
# laws.
|
||||
#
|
||||
# DISCLAIMER
|
||||
# This disclaimer is not a license and does not grant any
|
||||
# rights to the materials distributed herewith. Except as
|
||||
# otherwise provided in a valid license issued to you by
|
||||
# Xilinx, and to the maximum extent permitted by applicable
|
||||
# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
|
||||
# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
|
||||
# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
|
||||
# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
|
||||
# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
|
||||
# (2) Xilinx shall not be liable (whether in contract or tort,
|
||||
# including negligence, or under any other theory of
|
||||
# liability) for any loss or damage of any kind or nature
|
||||
# related to, arising under or in connection with these
|
||||
# materials, including for any direct, or any indirect,
|
||||
# special, incidental, or consequential loss or damage
|
||||
# (including loss of data, profits, goodwill, or any type of
|
||||
# loss or damage suffered as a result of any action brought
|
||||
# by a third party) even if such damage or loss was
|
||||
# reasonably foreseeable or Xilinx had been advised of the
|
||||
# possibility of the same.
|
||||
#
|
||||
# CRITICAL APPLICATIONS
|
||||
# Xilinx products are not designed or intended to be fail-
|
||||
# safe, or for use in any application requiring fail-safe
|
||||
# performance, such as life-support or safety devices or
|
||||
# systems, Class III medical devices, nuclear facilities,
|
||||
# applications related to the deployment of airbags, or any
|
||||
# other applications that could lead to death, personal
|
||||
# injury, or severe property or environmental damage
|
||||
# (individually and collectively, "Critical
|
||||
# Applications"). Customer assumes the sole risk and
|
||||
# liability of any use of Xilinx products in Critical
|
||||
# Applications, subject only to applicable laws and
|
||||
# regulations governing limitations on product liability.
|
||||
#
|
||||
# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
|
||||
# PART OF THIS FILE AT ALL TIMES.
|
||||
#
|
||||
################################################################################
|
||||
|
||||
# Core Period Constraint. This constraint can be modified, and is
|
||||
# valid as long as it is met after place and route.
|
||||
create_clock -name "TS_CLKA" -period 20.0 [ get_ports clka ]
|
||||
set_property HD.CLK_SRC BUFGCTRL_X0Y0 [ get_ports clka ]
|
||||
################################################################################
|
||||
817
lacpu/rtl/xilinx_ip/data_sram_bank/data_bram_bank_sim_netlist.v
Normal file
817
lacpu/rtl/xilinx_ip/data_sram_bank/data_bram_bank_sim_netlist.v
Normal file
@@ -0,0 +1,817 @@
|
||||
// Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
|
||||
// --------------------------------------------------------------------------------
|
||||
// Tool Version: Vivado v.2019.2 (win64) Build 2708876 Wed Nov 6 21:40:23 MST 2019
|
||||
// Date : Fri Jul 21 18:49:49 2023
|
||||
// Host : BHKLaptop running 64-bit major release (build 9200)
|
||||
// Command : write_verilog -force -mode funcsim
|
||||
// C:/Users/Unbal/Desktop/LoongArch/neulacpu/lacpu/rtl/xilinx_ip/data_sram_bank/data_bram_bank_sim_netlist.v
|
||||
// Design : data_bram_bank
|
||||
// Purpose : This verilog netlist is a functional simulation representation of the design and should not be modified
|
||||
// or synthesized. This netlist cannot be used for SDF annotated simulation.
|
||||
// Device : xc7a200tfbg676-1
|
||||
// --------------------------------------------------------------------------------
|
||||
`timescale 1 ps / 1 ps
|
||||
|
||||
(* CHECK_LICENSE_TYPE = "data_bram_bank,blk_mem_gen_v8_4_4,{}" *) (* downgradeipidentifiedwarnings = "yes" *) (* x_core_info = "blk_mem_gen_v8_4_4,Vivado 2019.2" *)
|
||||
(* NotValidForBitStream *)
|
||||
module data_bram_bank
|
||||
(clka,
|
||||
ena,
|
||||
wea,
|
||||
addra,
|
||||
dina,
|
||||
douta);
|
||||
(* x_interface_info = "xilinx.com:interface:bram:1.0 BRAM_PORTA CLK" *) (* x_interface_parameter = "XIL_INTERFACENAME BRAM_PORTA, MEM_SIZE 8192, MEM_WIDTH 32, MEM_ECC NONE, MASTER_TYPE OTHER, READ_LATENCY 1" *) input clka;
|
||||
(* x_interface_info = "xilinx.com:interface:bram:1.0 BRAM_PORTA EN" *) input ena;
|
||||
(* x_interface_info = "xilinx.com:interface:bram:1.0 BRAM_PORTA WE" *) input [0:0]wea;
|
||||
(* x_interface_info = "xilinx.com:interface:bram:1.0 BRAM_PORTA ADDR" *) input [5:0]addra;
|
||||
(* x_interface_info = "xilinx.com:interface:bram:1.0 BRAM_PORTA DIN" *) input [31:0]dina;
|
||||
(* x_interface_info = "xilinx.com:interface:bram:1.0 BRAM_PORTA DOUT" *) output [31:0]douta;
|
||||
|
||||
wire [5:0]addra;
|
||||
wire clka;
|
||||
wire [31:0]dina;
|
||||
wire [31:0]douta;
|
||||
wire ena;
|
||||
wire [0:0]wea;
|
||||
wire NLW_U0_dbiterr_UNCONNECTED;
|
||||
wire NLW_U0_rsta_busy_UNCONNECTED;
|
||||
wire NLW_U0_rstb_busy_UNCONNECTED;
|
||||
wire NLW_U0_s_axi_arready_UNCONNECTED;
|
||||
wire NLW_U0_s_axi_awready_UNCONNECTED;
|
||||
wire NLW_U0_s_axi_bvalid_UNCONNECTED;
|
||||
wire NLW_U0_s_axi_dbiterr_UNCONNECTED;
|
||||
wire NLW_U0_s_axi_rlast_UNCONNECTED;
|
||||
wire NLW_U0_s_axi_rvalid_UNCONNECTED;
|
||||
wire NLW_U0_s_axi_sbiterr_UNCONNECTED;
|
||||
wire NLW_U0_s_axi_wready_UNCONNECTED;
|
||||
wire NLW_U0_sbiterr_UNCONNECTED;
|
||||
wire [31:0]NLW_U0_doutb_UNCONNECTED;
|
||||
wire [5:0]NLW_U0_rdaddrecc_UNCONNECTED;
|
||||
wire [3:0]NLW_U0_s_axi_bid_UNCONNECTED;
|
||||
wire [1:0]NLW_U0_s_axi_bresp_UNCONNECTED;
|
||||
wire [5:0]NLW_U0_s_axi_rdaddrecc_UNCONNECTED;
|
||||
wire [31:0]NLW_U0_s_axi_rdata_UNCONNECTED;
|
||||
wire [3:0]NLW_U0_s_axi_rid_UNCONNECTED;
|
||||
wire [1:0]NLW_U0_s_axi_rresp_UNCONNECTED;
|
||||
|
||||
(* C_ADDRA_WIDTH = "6" *)
|
||||
(* C_ADDRB_WIDTH = "6" *)
|
||||
(* C_ALGORITHM = "1" *)
|
||||
(* C_AXI_ID_WIDTH = "4" *)
|
||||
(* C_AXI_SLAVE_TYPE = "0" *)
|
||||
(* C_AXI_TYPE = "1" *)
|
||||
(* C_BYTE_SIZE = "9" *)
|
||||
(* C_COMMON_CLK = "0" *)
|
||||
(* C_COUNT_18K_BRAM = "1" *)
|
||||
(* C_COUNT_36K_BRAM = "0" *)
|
||||
(* C_CTRL_ECC_ALGO = "NONE" *)
|
||||
(* C_DEFAULT_DATA = "0" *)
|
||||
(* C_DISABLE_WARN_BHV_COLL = "0" *)
|
||||
(* C_DISABLE_WARN_BHV_RANGE = "0" *)
|
||||
(* C_ELABORATION_DIR = "./" *)
|
||||
(* C_ENABLE_32BIT_ADDRESS = "0" *)
|
||||
(* C_EN_DEEPSLEEP_PIN = "0" *)
|
||||
(* C_EN_ECC_PIPE = "0" *)
|
||||
(* C_EN_RDADDRA_CHG = "0" *)
|
||||
(* C_EN_RDADDRB_CHG = "0" *)
|
||||
(* C_EN_SAFETY_CKT = "0" *)
|
||||
(* C_EN_SHUTDOWN_PIN = "0" *)
|
||||
(* C_EN_SLEEP_PIN = "0" *)
|
||||
(* C_EST_POWER_SUMMARY = "Estimated Power for IP : 3.53845 mW" *)
|
||||
(* C_FAMILY = "artix7" *)
|
||||
(* C_HAS_AXI_ID = "0" *)
|
||||
(* C_HAS_ENA = "1" *)
|
||||
(* C_HAS_ENB = "0" *)
|
||||
(* C_HAS_INJECTERR = "0" *)
|
||||
(* C_HAS_MEM_OUTPUT_REGS_A = "0" *)
|
||||
(* C_HAS_MEM_OUTPUT_REGS_B = "0" *)
|
||||
(* C_HAS_MUX_OUTPUT_REGS_A = "0" *)
|
||||
(* C_HAS_MUX_OUTPUT_REGS_B = "0" *)
|
||||
(* C_HAS_REGCEA = "0" *)
|
||||
(* C_HAS_REGCEB = "0" *)
|
||||
(* C_HAS_RSTA = "0" *)
|
||||
(* C_HAS_RSTB = "0" *)
|
||||
(* C_HAS_SOFTECC_INPUT_REGS_A = "0" *)
|
||||
(* C_HAS_SOFTECC_OUTPUT_REGS_B = "0" *)
|
||||
(* C_INITA_VAL = "0" *)
|
||||
(* C_INITB_VAL = "0" *)
|
||||
(* C_INIT_FILE = "data_bram_bank.mem" *)
|
||||
(* C_INIT_FILE_NAME = "no_coe_file_loaded" *)
|
||||
(* C_INTERFACE_TYPE = "0" *)
|
||||
(* C_LOAD_INIT_FILE = "0" *)
|
||||
(* C_MEM_TYPE = "0" *)
|
||||
(* C_MUX_PIPELINE_STAGES = "0" *)
|
||||
(* C_PRIM_TYPE = "1" *)
|
||||
(* C_READ_DEPTH_A = "64" *)
|
||||
(* C_READ_DEPTH_B = "64" *)
|
||||
(* C_READ_LATENCY_A = "1" *)
|
||||
(* C_READ_LATENCY_B = "1" *)
|
||||
(* C_READ_WIDTH_A = "32" *)
|
||||
(* C_READ_WIDTH_B = "32" *)
|
||||
(* C_RSTRAM_A = "0" *)
|
||||
(* C_RSTRAM_B = "0" *)
|
||||
(* C_RST_PRIORITY_A = "CE" *)
|
||||
(* C_RST_PRIORITY_B = "CE" *)
|
||||
(* C_SIM_COLLISION_CHECK = "ALL" *)
|
||||
(* C_USE_BRAM_BLOCK = "0" *)
|
||||
(* C_USE_BYTE_WEA = "0" *)
|
||||
(* C_USE_BYTE_WEB = "0" *)
|
||||
(* C_USE_DEFAULT_DATA = "0" *)
|
||||
(* C_USE_ECC = "0" *)
|
||||
(* C_USE_SOFTECC = "0" *)
|
||||
(* C_USE_URAM = "0" *)
|
||||
(* C_WEA_WIDTH = "1" *)
|
||||
(* C_WEB_WIDTH = "1" *)
|
||||
(* C_WRITE_DEPTH_A = "64" *)
|
||||
(* C_WRITE_DEPTH_B = "64" *)
|
||||
(* C_WRITE_MODE_A = "WRITE_FIRST" *)
|
||||
(* C_WRITE_MODE_B = "WRITE_FIRST" *)
|
||||
(* C_WRITE_WIDTH_A = "32" *)
|
||||
(* C_WRITE_WIDTH_B = "32" *)
|
||||
(* C_XDEVICEFAMILY = "artix7" *)
|
||||
(* downgradeipidentifiedwarnings = "yes" *)
|
||||
data_bram_bank_blk_mem_gen_v8_4_4 U0
|
||||
(.addra(addra),
|
||||
.addrb({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
|
||||
.clka(clka),
|
||||
.clkb(1'b0),
|
||||
.dbiterr(NLW_U0_dbiterr_UNCONNECTED),
|
||||
.deepsleep(1'b0),
|
||||
.dina(dina),
|
||||
.dinb({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
|
||||
.douta(douta),
|
||||
.doutb(NLW_U0_doutb_UNCONNECTED[31:0]),
|
||||
.eccpipece(1'b0),
|
||||
.ena(ena),
|
||||
.enb(1'b0),
|
||||
.injectdbiterr(1'b0),
|
||||
.injectsbiterr(1'b0),
|
||||
.rdaddrecc(NLW_U0_rdaddrecc_UNCONNECTED[5:0]),
|
||||
.regcea(1'b0),
|
||||
.regceb(1'b0),
|
||||
.rsta(1'b0),
|
||||
.rsta_busy(NLW_U0_rsta_busy_UNCONNECTED),
|
||||
.rstb(1'b0),
|
||||
.rstb_busy(NLW_U0_rstb_busy_UNCONNECTED),
|
||||
.s_aclk(1'b0),
|
||||
.s_aresetn(1'b0),
|
||||
.s_axi_araddr({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
|
||||
.s_axi_arburst({1'b0,1'b0}),
|
||||
.s_axi_arid({1'b0,1'b0,1'b0,1'b0}),
|
||||
.s_axi_arlen({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
|
||||
.s_axi_arready(NLW_U0_s_axi_arready_UNCONNECTED),
|
||||
.s_axi_arsize({1'b0,1'b0,1'b0}),
|
||||
.s_axi_arvalid(1'b0),
|
||||
.s_axi_awaddr({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
|
||||
.s_axi_awburst({1'b0,1'b0}),
|
||||
.s_axi_awid({1'b0,1'b0,1'b0,1'b0}),
|
||||
.s_axi_awlen({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
|
||||
.s_axi_awready(NLW_U0_s_axi_awready_UNCONNECTED),
|
||||
.s_axi_awsize({1'b0,1'b0,1'b0}),
|
||||
.s_axi_awvalid(1'b0),
|
||||
.s_axi_bid(NLW_U0_s_axi_bid_UNCONNECTED[3:0]),
|
||||
.s_axi_bready(1'b0),
|
||||
.s_axi_bresp(NLW_U0_s_axi_bresp_UNCONNECTED[1:0]),
|
||||
.s_axi_bvalid(NLW_U0_s_axi_bvalid_UNCONNECTED),
|
||||
.s_axi_dbiterr(NLW_U0_s_axi_dbiterr_UNCONNECTED),
|
||||
.s_axi_injectdbiterr(1'b0),
|
||||
.s_axi_injectsbiterr(1'b0),
|
||||
.s_axi_rdaddrecc(NLW_U0_s_axi_rdaddrecc_UNCONNECTED[5:0]),
|
||||
.s_axi_rdata(NLW_U0_s_axi_rdata_UNCONNECTED[31:0]),
|
||||
.s_axi_rid(NLW_U0_s_axi_rid_UNCONNECTED[3:0]),
|
||||
.s_axi_rlast(NLW_U0_s_axi_rlast_UNCONNECTED),
|
||||
.s_axi_rready(1'b0),
|
||||
.s_axi_rresp(NLW_U0_s_axi_rresp_UNCONNECTED[1:0]),
|
||||
.s_axi_rvalid(NLW_U0_s_axi_rvalid_UNCONNECTED),
|
||||
.s_axi_sbiterr(NLW_U0_s_axi_sbiterr_UNCONNECTED),
|
||||
.s_axi_wdata({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}),
|
||||
.s_axi_wlast(1'b0),
|
||||
.s_axi_wready(NLW_U0_s_axi_wready_UNCONNECTED),
|
||||
.s_axi_wstrb(1'b0),
|
||||
.s_axi_wvalid(1'b0),
|
||||
.sbiterr(NLW_U0_sbiterr_UNCONNECTED),
|
||||
.shutdown(1'b0),
|
||||
.sleep(1'b0),
|
||||
.wea(wea),
|
||||
.web(1'b0));
|
||||
endmodule
|
||||
|
||||
(* ORIG_REF_NAME = "blk_mem_gen_generic_cstr" *)
|
||||
module data_bram_bank_blk_mem_gen_generic_cstr
|
||||
(douta,
|
||||
clka,
|
||||
ena,
|
||||
addra,
|
||||
dina,
|
||||
wea);
|
||||
output [31:0]douta;
|
||||
input clka;
|
||||
input ena;
|
||||
input [5:0]addra;
|
||||
input [31:0]dina;
|
||||
input [0:0]wea;
|
||||
|
||||
wire [5:0]addra;
|
||||
wire clka;
|
||||
wire [31:0]dina;
|
||||
wire [31:0]douta;
|
||||
wire ena;
|
||||
wire [0:0]wea;
|
||||
|
||||
data_bram_bank_blk_mem_gen_prim_width \ramloop[0].ram.r
|
||||
(.addra(addra),
|
||||
.clka(clka),
|
||||
.dina(dina),
|
||||
.douta(douta),
|
||||
.ena(ena),
|
||||
.wea(wea));
|
||||
endmodule
|
||||
|
||||
(* ORIG_REF_NAME = "blk_mem_gen_prim_width" *)
|
||||
module data_bram_bank_blk_mem_gen_prim_width
|
||||
(douta,
|
||||
clka,
|
||||
ena,
|
||||
addra,
|
||||
dina,
|
||||
wea);
|
||||
output [31:0]douta;
|
||||
input clka;
|
||||
input ena;
|
||||
input [5:0]addra;
|
||||
input [31:0]dina;
|
||||
input [0:0]wea;
|
||||
|
||||
wire [5:0]addra;
|
||||
wire clka;
|
||||
wire [31:0]dina;
|
||||
wire [31:0]douta;
|
||||
wire ena;
|
||||
wire [0:0]wea;
|
||||
|
||||
data_bram_bank_blk_mem_gen_prim_wrapper \prim_noinit.ram
|
||||
(.addra(addra),
|
||||
.clka(clka),
|
||||
.dina(dina),
|
||||
.douta(douta),
|
||||
.ena(ena),
|
||||
.wea(wea));
|
||||
endmodule
|
||||
|
||||
(* ORIG_REF_NAME = "blk_mem_gen_prim_wrapper" *)
|
||||
module data_bram_bank_blk_mem_gen_prim_wrapper
|
||||
(douta,
|
||||
clka,
|
||||
ena,
|
||||
addra,
|
||||
dina,
|
||||
wea);
|
||||
output [31:0]douta;
|
||||
input clka;
|
||||
input ena;
|
||||
input [5:0]addra;
|
||||
input [31:0]dina;
|
||||
input [0:0]wea;
|
||||
|
||||
wire \DEVICE_7SERIES.NO_BMM_INFO.SP.WIDE_PRIM18.ram_n_32 ;
|
||||
wire \DEVICE_7SERIES.NO_BMM_INFO.SP.WIDE_PRIM18.ram_n_33 ;
|
||||
wire \DEVICE_7SERIES.NO_BMM_INFO.SP.WIDE_PRIM18.ram_n_34 ;
|
||||
wire \DEVICE_7SERIES.NO_BMM_INFO.SP.WIDE_PRIM18.ram_n_35 ;
|
||||
wire [5:0]addra;
|
||||
wire clka;
|
||||
wire [31:0]dina;
|
||||
wire [31:0]douta;
|
||||
wire ena;
|
||||
wire [0:0]wea;
|
||||
|
||||
(* box_type = "PRIMITIVE" *)
|
||||
RAMB18E1 #(
|
||||
.DOA_REG(0),
|
||||
.DOB_REG(0),
|
||||
.INITP_00(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
||||
.INITP_01(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
||||
.INITP_02(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
||||
.INITP_03(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
||||
.INITP_04(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
||||
.INITP_05(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
||||
.INITP_06(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
||||
.INITP_07(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
||||
.INIT_00(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
||||
.INIT_01(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
||||
.INIT_02(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
||||
.INIT_03(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
||||
.INIT_04(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
||||
.INIT_05(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
||||
.INIT_06(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
||||
.INIT_07(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
||||
.INIT_08(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
||||
.INIT_09(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
||||
.INIT_0A(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
||||
.INIT_0B(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
||||
.INIT_0C(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
||||
.INIT_0D(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
||||
.INIT_0E(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
||||
.INIT_0F(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
||||
.INIT_10(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
||||
.INIT_11(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
||||
.INIT_12(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
||||
.INIT_13(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
||||
.INIT_14(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
||||
.INIT_15(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
||||
.INIT_16(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
||||
.INIT_17(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
||||
.INIT_18(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
||||
.INIT_19(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
||||
.INIT_1A(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
||||
.INIT_1B(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
||||
.INIT_1C(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
||||
.INIT_1D(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
||||
.INIT_1E(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
||||
.INIT_1F(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
||||
.INIT_20(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
||||
.INIT_21(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
||||
.INIT_22(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
||||
.INIT_23(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
||||
.INIT_24(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
||||
.INIT_25(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
||||
.INIT_26(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
||||
.INIT_27(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
||||
.INIT_28(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
||||
.INIT_29(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
||||
.INIT_2A(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
||||
.INIT_2B(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
||||
.INIT_2C(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
||||
.INIT_2D(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
||||
.INIT_2E(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
||||
.INIT_2F(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
||||
.INIT_30(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
||||
.INIT_31(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
||||
.INIT_32(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
||||
.INIT_33(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
||||
.INIT_34(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
||||
.INIT_35(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
||||
.INIT_36(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
||||
.INIT_37(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
||||
.INIT_38(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
||||
.INIT_39(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
||||
.INIT_3A(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
||||
.INIT_3B(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
||||
.INIT_3C(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
||||
.INIT_3D(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
||||
.INIT_3E(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
||||
.INIT_3F(256'h0000000000000000000000000000000000000000000000000000000000000000),
|
||||
.INIT_A(18'h00000),
|
||||
.INIT_B(18'h00000),
|
||||
.INIT_FILE("NONE"),
|
||||
.IS_CLKARDCLK_INVERTED(1'b0),
|
||||
.IS_CLKBWRCLK_INVERTED(1'b0),
|
||||
.IS_ENARDEN_INVERTED(1'b0),
|
||||
.IS_ENBWREN_INVERTED(1'b0),
|
||||
.IS_RSTRAMARSTRAM_INVERTED(1'b0),
|
||||
.IS_RSTRAMB_INVERTED(1'b0),
|
||||
.IS_RSTREGARSTREG_INVERTED(1'b0),
|
||||
.IS_RSTREGB_INVERTED(1'b0),
|
||||
.RAM_MODE("TDP"),
|
||||
.RDADDR_COLLISION_HWCONFIG("DELAYED_WRITE"),
|
||||
.READ_WIDTH_A(18),
|
||||
.READ_WIDTH_B(18),
|
||||
.RSTREG_PRIORITY_A("REGCE"),
|
||||
.RSTREG_PRIORITY_B("REGCE"),
|
||||
.SIM_COLLISION_CHECK("ALL"),
|
||||
.SIM_DEVICE("7SERIES"),
|
||||
.SRVAL_A(18'h00000),
|
||||
.SRVAL_B(18'h00000),
|
||||
.WRITE_MODE_A("WRITE_FIRST"),
|
||||
.WRITE_MODE_B("WRITE_FIRST"),
|
||||
.WRITE_WIDTH_A(18),
|
||||
.WRITE_WIDTH_B(18))
|
||||
\DEVICE_7SERIES.NO_BMM_INFO.SP.WIDE_PRIM18.ram
|
||||
(.ADDRARDADDR({1'b0,1'b0,1'b0,addra,1'b0,1'b0,1'b0,1'b0,1'b0}),
|
||||
.ADDRBWRADDR({1'b0,1'b0,1'b0,addra,1'b1,1'b0,1'b0,1'b0,1'b0}),
|
||||
.CLKARDCLK(clka),
|
||||
.CLKBWRCLK(clka),
|
||||
.DIADI(dina[15:0]),
|
||||
.DIBDI(dina[31:16]),
|
||||
.DIPADIP({1'b0,1'b0}),
|
||||
.DIPBDIP({1'b0,1'b0}),
|
||||
.DOADO(douta[15:0]),
|
||||
.DOBDO(douta[31:16]),
|
||||
.DOPADOP({\DEVICE_7SERIES.NO_BMM_INFO.SP.WIDE_PRIM18.ram_n_32 ,\DEVICE_7SERIES.NO_BMM_INFO.SP.WIDE_PRIM18.ram_n_33 }),
|
||||
.DOPBDOP({\DEVICE_7SERIES.NO_BMM_INFO.SP.WIDE_PRIM18.ram_n_34 ,\DEVICE_7SERIES.NO_BMM_INFO.SP.WIDE_PRIM18.ram_n_35 }),
|
||||
.ENARDEN(ena),
|
||||
.ENBWREN(ena),
|
||||
.REGCEAREGCE(1'b0),
|
||||
.REGCEB(1'b0),
|
||||
.RSTRAMARSTRAM(1'b0),
|
||||
.RSTRAMB(1'b0),
|
||||
.RSTREGARSTREG(1'b0),
|
||||
.RSTREGB(1'b0),
|
||||
.WEA({wea,wea}),
|
||||
.WEBWE({1'b0,1'b0,wea,wea}));
|
||||
endmodule
|
||||
|
||||
(* ORIG_REF_NAME = "blk_mem_gen_top" *)
|
||||
module data_bram_bank_blk_mem_gen_top
|
||||
(douta,
|
||||
clka,
|
||||
ena,
|
||||
addra,
|
||||
dina,
|
||||
wea);
|
||||
output [31:0]douta;
|
||||
input clka;
|
||||
input ena;
|
||||
input [5:0]addra;
|
||||
input [31:0]dina;
|
||||
input [0:0]wea;
|
||||
|
||||
wire [5:0]addra;
|
||||
wire clka;
|
||||
wire [31:0]dina;
|
||||
wire [31:0]douta;
|
||||
wire ena;
|
||||
wire [0:0]wea;
|
||||
|
||||
data_bram_bank_blk_mem_gen_generic_cstr \valid.cstr
|
||||
(.addra(addra),
|
||||
.clka(clka),
|
||||
.dina(dina),
|
||||
.douta(douta),
|
||||
.ena(ena),
|
||||
.wea(wea));
|
||||
endmodule
|
||||
|
||||
(* C_ADDRA_WIDTH = "6" *) (* C_ADDRB_WIDTH = "6" *) (* C_ALGORITHM = "1" *)
|
||||
(* C_AXI_ID_WIDTH = "4" *) (* C_AXI_SLAVE_TYPE = "0" *) (* C_AXI_TYPE = "1" *)
|
||||
(* C_BYTE_SIZE = "9" *) (* C_COMMON_CLK = "0" *) (* C_COUNT_18K_BRAM = "1" *)
|
||||
(* C_COUNT_36K_BRAM = "0" *) (* C_CTRL_ECC_ALGO = "NONE" *) (* C_DEFAULT_DATA = "0" *)
|
||||
(* C_DISABLE_WARN_BHV_COLL = "0" *) (* C_DISABLE_WARN_BHV_RANGE = "0" *) (* C_ELABORATION_DIR = "./" *)
|
||||
(* C_ENABLE_32BIT_ADDRESS = "0" *) (* C_EN_DEEPSLEEP_PIN = "0" *) (* C_EN_ECC_PIPE = "0" *)
|
||||
(* C_EN_RDADDRA_CHG = "0" *) (* C_EN_RDADDRB_CHG = "0" *) (* C_EN_SAFETY_CKT = "0" *)
|
||||
(* C_EN_SHUTDOWN_PIN = "0" *) (* C_EN_SLEEP_PIN = "0" *) (* C_EST_POWER_SUMMARY = "Estimated Power for IP : 3.53845 mW" *)
|
||||
(* C_FAMILY = "artix7" *) (* C_HAS_AXI_ID = "0" *) (* C_HAS_ENA = "1" *)
|
||||
(* C_HAS_ENB = "0" *) (* C_HAS_INJECTERR = "0" *) (* C_HAS_MEM_OUTPUT_REGS_A = "0" *)
|
||||
(* C_HAS_MEM_OUTPUT_REGS_B = "0" *) (* C_HAS_MUX_OUTPUT_REGS_A = "0" *) (* C_HAS_MUX_OUTPUT_REGS_B = "0" *)
|
||||
(* C_HAS_REGCEA = "0" *) (* C_HAS_REGCEB = "0" *) (* C_HAS_RSTA = "0" *)
|
||||
(* C_HAS_RSTB = "0" *) (* C_HAS_SOFTECC_INPUT_REGS_A = "0" *) (* C_HAS_SOFTECC_OUTPUT_REGS_B = "0" *)
|
||||
(* C_INITA_VAL = "0" *) (* C_INITB_VAL = "0" *) (* C_INIT_FILE = "data_bram_bank.mem" *)
|
||||
(* C_INIT_FILE_NAME = "no_coe_file_loaded" *) (* C_INTERFACE_TYPE = "0" *) (* C_LOAD_INIT_FILE = "0" *)
|
||||
(* C_MEM_TYPE = "0" *) (* C_MUX_PIPELINE_STAGES = "0" *) (* C_PRIM_TYPE = "1" *)
|
||||
(* C_READ_DEPTH_A = "64" *) (* C_READ_DEPTH_B = "64" *) (* C_READ_LATENCY_A = "1" *)
|
||||
(* C_READ_LATENCY_B = "1" *) (* C_READ_WIDTH_A = "32" *) (* C_READ_WIDTH_B = "32" *)
|
||||
(* C_RSTRAM_A = "0" *) (* C_RSTRAM_B = "0" *) (* C_RST_PRIORITY_A = "CE" *)
|
||||
(* C_RST_PRIORITY_B = "CE" *) (* C_SIM_COLLISION_CHECK = "ALL" *) (* C_USE_BRAM_BLOCK = "0" *)
|
||||
(* C_USE_BYTE_WEA = "0" *) (* C_USE_BYTE_WEB = "0" *) (* C_USE_DEFAULT_DATA = "0" *)
|
||||
(* C_USE_ECC = "0" *) (* C_USE_SOFTECC = "0" *) (* C_USE_URAM = "0" *)
|
||||
(* C_WEA_WIDTH = "1" *) (* C_WEB_WIDTH = "1" *) (* C_WRITE_DEPTH_A = "64" *)
|
||||
(* C_WRITE_DEPTH_B = "64" *) (* C_WRITE_MODE_A = "WRITE_FIRST" *) (* C_WRITE_MODE_B = "WRITE_FIRST" *)
|
||||
(* C_WRITE_WIDTH_A = "32" *) (* C_WRITE_WIDTH_B = "32" *) (* C_XDEVICEFAMILY = "artix7" *)
|
||||
(* ORIG_REF_NAME = "blk_mem_gen_v8_4_4" *) (* downgradeipidentifiedwarnings = "yes" *)
|
||||
module data_bram_bank_blk_mem_gen_v8_4_4
|
||||
(clka,
|
||||
rsta,
|
||||
ena,
|
||||
regcea,
|
||||
wea,
|
||||
addra,
|
||||
dina,
|
||||
douta,
|
||||
clkb,
|
||||
rstb,
|
||||
enb,
|
||||
regceb,
|
||||
web,
|
||||
addrb,
|
||||
dinb,
|
||||
doutb,
|
||||
injectsbiterr,
|
||||
injectdbiterr,
|
||||
eccpipece,
|
||||
sbiterr,
|
||||
dbiterr,
|
||||
rdaddrecc,
|
||||
sleep,
|
||||
deepsleep,
|
||||
shutdown,
|
||||
rsta_busy,
|
||||
rstb_busy,
|
||||
s_aclk,
|
||||
s_aresetn,
|
||||
s_axi_awid,
|
||||
s_axi_awaddr,
|
||||
s_axi_awlen,
|
||||
s_axi_awsize,
|
||||
s_axi_awburst,
|
||||
s_axi_awvalid,
|
||||
s_axi_awready,
|
||||
s_axi_wdata,
|
||||
s_axi_wstrb,
|
||||
s_axi_wlast,
|
||||
s_axi_wvalid,
|
||||
s_axi_wready,
|
||||
s_axi_bid,
|
||||
s_axi_bresp,
|
||||
s_axi_bvalid,
|
||||
s_axi_bready,
|
||||
s_axi_arid,
|
||||
s_axi_araddr,
|
||||
s_axi_arlen,
|
||||
s_axi_arsize,
|
||||
s_axi_arburst,
|
||||
s_axi_arvalid,
|
||||
s_axi_arready,
|
||||
s_axi_rid,
|
||||
s_axi_rdata,
|
||||
s_axi_rresp,
|
||||
s_axi_rlast,
|
||||
s_axi_rvalid,
|
||||
s_axi_rready,
|
||||
s_axi_injectsbiterr,
|
||||
s_axi_injectdbiterr,
|
||||
s_axi_sbiterr,
|
||||
s_axi_dbiterr,
|
||||
s_axi_rdaddrecc);
|
||||
input clka;
|
||||
input rsta;
|
||||
input ena;
|
||||
input regcea;
|
||||
input [0:0]wea;
|
||||
input [5:0]addra;
|
||||
input [31:0]dina;
|
||||
output [31:0]douta;
|
||||
input clkb;
|
||||
input rstb;
|
||||
input enb;
|
||||
input regceb;
|
||||
input [0:0]web;
|
||||
input [5:0]addrb;
|
||||
input [31:0]dinb;
|
||||
output [31:0]doutb;
|
||||
input injectsbiterr;
|
||||
input injectdbiterr;
|
||||
input eccpipece;
|
||||
output sbiterr;
|
||||
output dbiterr;
|
||||
output [5:0]rdaddrecc;
|
||||
input sleep;
|
||||
input deepsleep;
|
||||
input shutdown;
|
||||
output rsta_busy;
|
||||
output rstb_busy;
|
||||
input s_aclk;
|
||||
input s_aresetn;
|
||||
input [3:0]s_axi_awid;
|
||||
input [31:0]s_axi_awaddr;
|
||||
input [7:0]s_axi_awlen;
|
||||
input [2:0]s_axi_awsize;
|
||||
input [1:0]s_axi_awburst;
|
||||
input s_axi_awvalid;
|
||||
output s_axi_awready;
|
||||
input [31:0]s_axi_wdata;
|
||||
input [0:0]s_axi_wstrb;
|
||||
input s_axi_wlast;
|
||||
input s_axi_wvalid;
|
||||
output s_axi_wready;
|
||||
output [3:0]s_axi_bid;
|
||||
output [1:0]s_axi_bresp;
|
||||
output s_axi_bvalid;
|
||||
input s_axi_bready;
|
||||
input [3:0]s_axi_arid;
|
||||
input [31:0]s_axi_araddr;
|
||||
input [7:0]s_axi_arlen;
|
||||
input [2:0]s_axi_arsize;
|
||||
input [1:0]s_axi_arburst;
|
||||
input s_axi_arvalid;
|
||||
output s_axi_arready;
|
||||
output [3:0]s_axi_rid;
|
||||
output [31:0]s_axi_rdata;
|
||||
output [1:0]s_axi_rresp;
|
||||
output s_axi_rlast;
|
||||
output s_axi_rvalid;
|
||||
input s_axi_rready;
|
||||
input s_axi_injectsbiterr;
|
||||
input s_axi_injectdbiterr;
|
||||
output s_axi_sbiterr;
|
||||
output s_axi_dbiterr;
|
||||
output [5:0]s_axi_rdaddrecc;
|
||||
|
||||
wire \<const0> ;
|
||||
wire [5:0]addra;
|
||||
wire clka;
|
||||
wire [31:0]dina;
|
||||
wire [31:0]douta;
|
||||
wire ena;
|
||||
wire [0:0]wea;
|
||||
|
||||
assign dbiterr = \<const0> ;
|
||||
assign doutb[31] = \<const0> ;
|
||||
assign doutb[30] = \<const0> ;
|
||||
assign doutb[29] = \<const0> ;
|
||||
assign doutb[28] = \<const0> ;
|
||||
assign doutb[27] = \<const0> ;
|
||||
assign doutb[26] = \<const0> ;
|
||||
assign doutb[25] = \<const0> ;
|
||||
assign doutb[24] = \<const0> ;
|
||||
assign doutb[23] = \<const0> ;
|
||||
assign doutb[22] = \<const0> ;
|
||||
assign doutb[21] = \<const0> ;
|
||||
assign doutb[20] = \<const0> ;
|
||||
assign doutb[19] = \<const0> ;
|
||||
assign doutb[18] = \<const0> ;
|
||||
assign doutb[17] = \<const0> ;
|
||||
assign doutb[16] = \<const0> ;
|
||||
assign doutb[15] = \<const0> ;
|
||||
assign doutb[14] = \<const0> ;
|
||||
assign doutb[13] = \<const0> ;
|
||||
assign doutb[12] = \<const0> ;
|
||||
assign doutb[11] = \<const0> ;
|
||||
assign doutb[10] = \<const0> ;
|
||||
assign doutb[9] = \<const0> ;
|
||||
assign doutb[8] = \<const0> ;
|
||||
assign doutb[7] = \<const0> ;
|
||||
assign doutb[6] = \<const0> ;
|
||||
assign doutb[5] = \<const0> ;
|
||||
assign doutb[4] = \<const0> ;
|
||||
assign doutb[3] = \<const0> ;
|
||||
assign doutb[2] = \<const0> ;
|
||||
assign doutb[1] = \<const0> ;
|
||||
assign doutb[0] = \<const0> ;
|
||||
assign rdaddrecc[5] = \<const0> ;
|
||||
assign rdaddrecc[4] = \<const0> ;
|
||||
assign rdaddrecc[3] = \<const0> ;
|
||||
assign rdaddrecc[2] = \<const0> ;
|
||||
assign rdaddrecc[1] = \<const0> ;
|
||||
assign rdaddrecc[0] = \<const0> ;
|
||||
assign rsta_busy = \<const0> ;
|
||||
assign rstb_busy = \<const0> ;
|
||||
assign s_axi_arready = \<const0> ;
|
||||
assign s_axi_awready = \<const0> ;
|
||||
assign s_axi_bid[3] = \<const0> ;
|
||||
assign s_axi_bid[2] = \<const0> ;
|
||||
assign s_axi_bid[1] = \<const0> ;
|
||||
assign s_axi_bid[0] = \<const0> ;
|
||||
assign s_axi_bresp[1] = \<const0> ;
|
||||
assign s_axi_bresp[0] = \<const0> ;
|
||||
assign s_axi_bvalid = \<const0> ;
|
||||
assign s_axi_dbiterr = \<const0> ;
|
||||
assign s_axi_rdaddrecc[5] = \<const0> ;
|
||||
assign s_axi_rdaddrecc[4] = \<const0> ;
|
||||
assign s_axi_rdaddrecc[3] = \<const0> ;
|
||||
assign s_axi_rdaddrecc[2] = \<const0> ;
|
||||
assign s_axi_rdaddrecc[1] = \<const0> ;
|
||||
assign s_axi_rdaddrecc[0] = \<const0> ;
|
||||
assign s_axi_rdata[31] = \<const0> ;
|
||||
assign s_axi_rdata[30] = \<const0> ;
|
||||
assign s_axi_rdata[29] = \<const0> ;
|
||||
assign s_axi_rdata[28] = \<const0> ;
|
||||
assign s_axi_rdata[27] = \<const0> ;
|
||||
assign s_axi_rdata[26] = \<const0> ;
|
||||
assign s_axi_rdata[25] = \<const0> ;
|
||||
assign s_axi_rdata[24] = \<const0> ;
|
||||
assign s_axi_rdata[23] = \<const0> ;
|
||||
assign s_axi_rdata[22] = \<const0> ;
|
||||
assign s_axi_rdata[21] = \<const0> ;
|
||||
assign s_axi_rdata[20] = \<const0> ;
|
||||
assign s_axi_rdata[19] = \<const0> ;
|
||||
assign s_axi_rdata[18] = \<const0> ;
|
||||
assign s_axi_rdata[17] = \<const0> ;
|
||||
assign s_axi_rdata[16] = \<const0> ;
|
||||
assign s_axi_rdata[15] = \<const0> ;
|
||||
assign s_axi_rdata[14] = \<const0> ;
|
||||
assign s_axi_rdata[13] = \<const0> ;
|
||||
assign s_axi_rdata[12] = \<const0> ;
|
||||
assign s_axi_rdata[11] = \<const0> ;
|
||||
assign s_axi_rdata[10] = \<const0> ;
|
||||
assign s_axi_rdata[9] = \<const0> ;
|
||||
assign s_axi_rdata[8] = \<const0> ;
|
||||
assign s_axi_rdata[7] = \<const0> ;
|
||||
assign s_axi_rdata[6] = \<const0> ;
|
||||
assign s_axi_rdata[5] = \<const0> ;
|
||||
assign s_axi_rdata[4] = \<const0> ;
|
||||
assign s_axi_rdata[3] = \<const0> ;
|
||||
assign s_axi_rdata[2] = \<const0> ;
|
||||
assign s_axi_rdata[1] = \<const0> ;
|
||||
assign s_axi_rdata[0] = \<const0> ;
|
||||
assign s_axi_rid[3] = \<const0> ;
|
||||
assign s_axi_rid[2] = \<const0> ;
|
||||
assign s_axi_rid[1] = \<const0> ;
|
||||
assign s_axi_rid[0] = \<const0> ;
|
||||
assign s_axi_rlast = \<const0> ;
|
||||
assign s_axi_rresp[1] = \<const0> ;
|
||||
assign s_axi_rresp[0] = \<const0> ;
|
||||
assign s_axi_rvalid = \<const0> ;
|
||||
assign s_axi_sbiterr = \<const0> ;
|
||||
assign s_axi_wready = \<const0> ;
|
||||
assign sbiterr = \<const0> ;
|
||||
GND GND
|
||||
(.G(\<const0> ));
|
||||
data_bram_bank_blk_mem_gen_v8_4_4_synth inst_blk_mem_gen
|
||||
(.addra(addra),
|
||||
.clka(clka),
|
||||
.dina(dina),
|
||||
.douta(douta),
|
||||
.ena(ena),
|
||||
.wea(wea));
|
||||
endmodule
|
||||
|
||||
(* ORIG_REF_NAME = "blk_mem_gen_v8_4_4_synth" *)
|
||||
module data_bram_bank_blk_mem_gen_v8_4_4_synth
|
||||
(douta,
|
||||
clka,
|
||||
ena,
|
||||
addra,
|
||||
dina,
|
||||
wea);
|
||||
output [31:0]douta;
|
||||
input clka;
|
||||
input ena;
|
||||
input [5:0]addra;
|
||||
input [31:0]dina;
|
||||
input [0:0]wea;
|
||||
|
||||
wire [5:0]addra;
|
||||
wire clka;
|
||||
wire [31:0]dina;
|
||||
wire [31:0]douta;
|
||||
wire ena;
|
||||
wire [0:0]wea;
|
||||
|
||||
data_bram_bank_blk_mem_gen_top \gnbram.gnativebmg.native_blk_mem_gen
|
||||
(.addra(addra),
|
||||
.clka(clka),
|
||||
.dina(dina),
|
||||
.douta(douta),
|
||||
.ena(ena),
|
||||
.wea(wea));
|
||||
endmodule
|
||||
`ifndef GLBL
|
||||
`define GLBL
|
||||
`timescale 1 ps / 1 ps
|
||||
|
||||
module glbl ();
|
||||
|
||||
parameter ROC_WIDTH = 100000;
|
||||
parameter TOC_WIDTH = 0;
|
||||
|
||||
//-------- STARTUP Globals --------------
|
||||
wire GSR;
|
||||
wire GTS;
|
||||
wire GWE;
|
||||
wire PRLD;
|
||||
tri1 p_up_tmp;
|
||||
tri (weak1, strong0) PLL_LOCKG = p_up_tmp;
|
||||
|
||||
wire PROGB_GLBL;
|
||||
wire CCLKO_GLBL;
|
||||
wire FCSBO_GLBL;
|
||||
wire [3:0] DO_GLBL;
|
||||
wire [3:0] DI_GLBL;
|
||||
|
||||
reg GSR_int;
|
||||
reg GTS_int;
|
||||
reg PRLD_int;
|
||||
|
||||
//-------- JTAG Globals --------------
|
||||
wire JTAG_TDO_GLBL;
|
||||
wire JTAG_TCK_GLBL;
|
||||
wire JTAG_TDI_GLBL;
|
||||
wire JTAG_TMS_GLBL;
|
||||
wire JTAG_TRST_GLBL;
|
||||
|
||||
reg JTAG_CAPTURE_GLBL;
|
||||
reg JTAG_RESET_GLBL;
|
||||
reg JTAG_SHIFT_GLBL;
|
||||
reg JTAG_UPDATE_GLBL;
|
||||
reg JTAG_RUNTEST_GLBL;
|
||||
|
||||
reg JTAG_SEL1_GLBL = 0;
|
||||
reg JTAG_SEL2_GLBL = 0 ;
|
||||
reg JTAG_SEL3_GLBL = 0;
|
||||
reg JTAG_SEL4_GLBL = 0;
|
||||
|
||||
reg JTAG_USER_TDO1_GLBL = 1'bz;
|
||||
reg JTAG_USER_TDO2_GLBL = 1'bz;
|
||||
reg JTAG_USER_TDO3_GLBL = 1'bz;
|
||||
reg JTAG_USER_TDO4_GLBL = 1'bz;
|
||||
|
||||
assign (strong1, weak0) GSR = GSR_int;
|
||||
assign (strong1, weak0) GTS = GTS_int;
|
||||
assign (weak1, weak0) PRLD = PRLD_int;
|
||||
|
||||
initial begin
|
||||
GSR_int = 1'b1;
|
||||
PRLD_int = 1'b1;
|
||||
#(ROC_WIDTH)
|
||||
GSR_int = 1'b0;
|
||||
PRLD_int = 1'b0;
|
||||
end
|
||||
|
||||
initial begin
|
||||
GTS_int = 1'b1;
|
||||
#(TOC_WIDTH)
|
||||
GTS_int = 1'b0;
|
||||
end
|
||||
|
||||
endmodule
|
||||
`endif
|
||||
@@ -0,0 +1,904 @@
|
||||
-- Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
|
||||
-- --------------------------------------------------------------------------------
|
||||
-- Tool Version: Vivado v.2019.2 (win64) Build 2708876 Wed Nov 6 21:40:23 MST 2019
|
||||
-- Date : Fri Jul 21 18:49:49 2023
|
||||
-- Host : BHKLaptop running 64-bit major release (build 9200)
|
||||
-- Command : write_vhdl -force -mode funcsim
|
||||
-- C:/Users/Unbal/Desktop/LoongArch/neulacpu/lacpu/rtl/xilinx_ip/data_sram_bank/data_bram_bank_sim_netlist.vhdl
|
||||
-- Design : data_bram_bank
|
||||
-- Purpose : This VHDL netlist is a functional simulation representation of the design and should not be modified or
|
||||
-- synthesized. This netlist cannot be used for SDF annotated simulation.
|
||||
-- Device : xc7a200tfbg676-1
|
||||
-- --------------------------------------------------------------------------------
|
||||
library IEEE;
|
||||
use IEEE.STD_LOGIC_1164.ALL;
|
||||
library UNISIM;
|
||||
use UNISIM.VCOMPONENTS.ALL;
|
||||
entity data_bram_bank_blk_mem_gen_prim_wrapper is
|
||||
port (
|
||||
douta : out STD_LOGIC_VECTOR ( 31 downto 0 );
|
||||
clka : in STD_LOGIC;
|
||||
ena : in STD_LOGIC;
|
||||
addra : in STD_LOGIC_VECTOR ( 5 downto 0 );
|
||||
dina : in STD_LOGIC_VECTOR ( 31 downto 0 );
|
||||
wea : in STD_LOGIC_VECTOR ( 0 to 0 )
|
||||
);
|
||||
attribute ORIG_REF_NAME : string;
|
||||
attribute ORIG_REF_NAME of data_bram_bank_blk_mem_gen_prim_wrapper : entity is "blk_mem_gen_prim_wrapper";
|
||||
end data_bram_bank_blk_mem_gen_prim_wrapper;
|
||||
|
||||
architecture STRUCTURE of data_bram_bank_blk_mem_gen_prim_wrapper is
|
||||
signal \DEVICE_7SERIES.NO_BMM_INFO.SP.WIDE_PRIM18.ram_n_32\ : STD_LOGIC;
|
||||
signal \DEVICE_7SERIES.NO_BMM_INFO.SP.WIDE_PRIM18.ram_n_33\ : STD_LOGIC;
|
||||
signal \DEVICE_7SERIES.NO_BMM_INFO.SP.WIDE_PRIM18.ram_n_34\ : STD_LOGIC;
|
||||
signal \DEVICE_7SERIES.NO_BMM_INFO.SP.WIDE_PRIM18.ram_n_35\ : STD_LOGIC;
|
||||
attribute box_type : string;
|
||||
attribute box_type of \DEVICE_7SERIES.NO_BMM_INFO.SP.WIDE_PRIM18.ram\ : label is "PRIMITIVE";
|
||||
begin
|
||||
\DEVICE_7SERIES.NO_BMM_INFO.SP.WIDE_PRIM18.ram\: unisim.vcomponents.RAMB18E1
|
||||
generic map(
|
||||
DOA_REG => 0,
|
||||
DOB_REG => 0,
|
||||
INITP_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
|
||||
INITP_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
|
||||
INITP_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
|
||||
INITP_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
|
||||
INITP_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
|
||||
INITP_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
|
||||
INITP_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
|
||||
INITP_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
|
||||
INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
|
||||
INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
|
||||
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
|
||||
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
|
||||
INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
|
||||
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
|
||||
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
|
||||
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
|
||||
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
|
||||
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
|
||||
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
|
||||
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
|
||||
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
|
||||
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
|
||||
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
|
||||
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
|
||||
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
|
||||
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
|
||||
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
|
||||
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
|
||||
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
|
||||
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
|
||||
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
|
||||
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
|
||||
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
|
||||
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
|
||||
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
|
||||
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
|
||||
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
|
||||
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
|
||||
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
|
||||
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
|
||||
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
|
||||
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
|
||||
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
|
||||
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
|
||||
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
|
||||
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
|
||||
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
|
||||
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
|
||||
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
|
||||
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
|
||||
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
|
||||
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
|
||||
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
|
||||
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
|
||||
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
|
||||
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
|
||||
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
|
||||
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
|
||||
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
|
||||
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
|
||||
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
|
||||
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
|
||||
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
|
||||
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
|
||||
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
|
||||
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
|
||||
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
|
||||
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
|
||||
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
|
||||
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
|
||||
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
|
||||
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000",
|
||||
INIT_A => X"00000",
|
||||
INIT_B => X"00000",
|
||||
INIT_FILE => "NONE",
|
||||
IS_CLKARDCLK_INVERTED => '0',
|
||||
IS_CLKBWRCLK_INVERTED => '0',
|
||||
IS_ENARDEN_INVERTED => '0',
|
||||
IS_ENBWREN_INVERTED => '0',
|
||||
IS_RSTRAMARSTRAM_INVERTED => '0',
|
||||
IS_RSTRAMB_INVERTED => '0',
|
||||
IS_RSTREGARSTREG_INVERTED => '0',
|
||||
IS_RSTREGB_INVERTED => '0',
|
||||
RAM_MODE => "TDP",
|
||||
RDADDR_COLLISION_HWCONFIG => "DELAYED_WRITE",
|
||||
READ_WIDTH_A => 18,
|
||||
READ_WIDTH_B => 18,
|
||||
RSTREG_PRIORITY_A => "REGCE",
|
||||
RSTREG_PRIORITY_B => "REGCE",
|
||||
SIM_COLLISION_CHECK => "ALL",
|
||||
SIM_DEVICE => "7SERIES",
|
||||
SRVAL_A => X"00000",
|
||||
SRVAL_B => X"00000",
|
||||
WRITE_MODE_A => "WRITE_FIRST",
|
||||
WRITE_MODE_B => "WRITE_FIRST",
|
||||
WRITE_WIDTH_A => 18,
|
||||
WRITE_WIDTH_B => 18
|
||||
)
|
||||
port map (
|
||||
ADDRARDADDR(13 downto 11) => B"000",
|
||||
ADDRARDADDR(10 downto 5) => addra(5 downto 0),
|
||||
ADDRARDADDR(4 downto 0) => B"00000",
|
||||
ADDRBWRADDR(13 downto 11) => B"000",
|
||||
ADDRBWRADDR(10 downto 5) => addra(5 downto 0),
|
||||
ADDRBWRADDR(4 downto 0) => B"10000",
|
||||
CLKARDCLK => clka,
|
||||
CLKBWRCLK => clka,
|
||||
DIADI(15 downto 0) => dina(15 downto 0),
|
||||
DIBDI(15 downto 0) => dina(31 downto 16),
|
||||
DIPADIP(1 downto 0) => B"00",
|
||||
DIPBDIP(1 downto 0) => B"00",
|
||||
DOADO(15 downto 0) => douta(15 downto 0),
|
||||
DOBDO(15 downto 0) => douta(31 downto 16),
|
||||
DOPADOP(1) => \DEVICE_7SERIES.NO_BMM_INFO.SP.WIDE_PRIM18.ram_n_32\,
|
||||
DOPADOP(0) => \DEVICE_7SERIES.NO_BMM_INFO.SP.WIDE_PRIM18.ram_n_33\,
|
||||
DOPBDOP(1) => \DEVICE_7SERIES.NO_BMM_INFO.SP.WIDE_PRIM18.ram_n_34\,
|
||||
DOPBDOP(0) => \DEVICE_7SERIES.NO_BMM_INFO.SP.WIDE_PRIM18.ram_n_35\,
|
||||
ENARDEN => ena,
|
||||
ENBWREN => ena,
|
||||
REGCEAREGCE => '0',
|
||||
REGCEB => '0',
|
||||
RSTRAMARSTRAM => '0',
|
||||
RSTRAMB => '0',
|
||||
RSTREGARSTREG => '0',
|
||||
RSTREGB => '0',
|
||||
WEA(1) => wea(0),
|
||||
WEA(0) => wea(0),
|
||||
WEBWE(3 downto 2) => B"00",
|
||||
WEBWE(1) => wea(0),
|
||||
WEBWE(0) => wea(0)
|
||||
);
|
||||
end STRUCTURE;
|
||||
library IEEE;
|
||||
use IEEE.STD_LOGIC_1164.ALL;
|
||||
library UNISIM;
|
||||
use UNISIM.VCOMPONENTS.ALL;
|
||||
entity data_bram_bank_blk_mem_gen_prim_width is
|
||||
port (
|
||||
douta : out STD_LOGIC_VECTOR ( 31 downto 0 );
|
||||
clka : in STD_LOGIC;
|
||||
ena : in STD_LOGIC;
|
||||
addra : in STD_LOGIC_VECTOR ( 5 downto 0 );
|
||||
dina : in STD_LOGIC_VECTOR ( 31 downto 0 );
|
||||
wea : in STD_LOGIC_VECTOR ( 0 to 0 )
|
||||
);
|
||||
attribute ORIG_REF_NAME : string;
|
||||
attribute ORIG_REF_NAME of data_bram_bank_blk_mem_gen_prim_width : entity is "blk_mem_gen_prim_width";
|
||||
end data_bram_bank_blk_mem_gen_prim_width;
|
||||
|
||||
architecture STRUCTURE of data_bram_bank_blk_mem_gen_prim_width is
|
||||
begin
|
||||
\prim_noinit.ram\: entity work.data_bram_bank_blk_mem_gen_prim_wrapper
|
||||
port map (
|
||||
addra(5 downto 0) => addra(5 downto 0),
|
||||
clka => clka,
|
||||
dina(31 downto 0) => dina(31 downto 0),
|
||||
douta(31 downto 0) => douta(31 downto 0),
|
||||
ena => ena,
|
||||
wea(0) => wea(0)
|
||||
);
|
||||
end STRUCTURE;
|
||||
library IEEE;
|
||||
use IEEE.STD_LOGIC_1164.ALL;
|
||||
library UNISIM;
|
||||
use UNISIM.VCOMPONENTS.ALL;
|
||||
entity data_bram_bank_blk_mem_gen_generic_cstr is
|
||||
port (
|
||||
douta : out STD_LOGIC_VECTOR ( 31 downto 0 );
|
||||
clka : in STD_LOGIC;
|
||||
ena : in STD_LOGIC;
|
||||
addra : in STD_LOGIC_VECTOR ( 5 downto 0 );
|
||||
dina : in STD_LOGIC_VECTOR ( 31 downto 0 );
|
||||
wea : in STD_LOGIC_VECTOR ( 0 to 0 )
|
||||
);
|
||||
attribute ORIG_REF_NAME : string;
|
||||
attribute ORIG_REF_NAME of data_bram_bank_blk_mem_gen_generic_cstr : entity is "blk_mem_gen_generic_cstr";
|
||||
end data_bram_bank_blk_mem_gen_generic_cstr;
|
||||
|
||||
architecture STRUCTURE of data_bram_bank_blk_mem_gen_generic_cstr is
|
||||
begin
|
||||
\ramloop[0].ram.r\: entity work.data_bram_bank_blk_mem_gen_prim_width
|
||||
port map (
|
||||
addra(5 downto 0) => addra(5 downto 0),
|
||||
clka => clka,
|
||||
dina(31 downto 0) => dina(31 downto 0),
|
||||
douta(31 downto 0) => douta(31 downto 0),
|
||||
ena => ena,
|
||||
wea(0) => wea(0)
|
||||
);
|
||||
end STRUCTURE;
|
||||
library IEEE;
|
||||
use IEEE.STD_LOGIC_1164.ALL;
|
||||
library UNISIM;
|
||||
use UNISIM.VCOMPONENTS.ALL;
|
||||
entity data_bram_bank_blk_mem_gen_top is
|
||||
port (
|
||||
douta : out STD_LOGIC_VECTOR ( 31 downto 0 );
|
||||
clka : in STD_LOGIC;
|
||||
ena : in STD_LOGIC;
|
||||
addra : in STD_LOGIC_VECTOR ( 5 downto 0 );
|
||||
dina : in STD_LOGIC_VECTOR ( 31 downto 0 );
|
||||
wea : in STD_LOGIC_VECTOR ( 0 to 0 )
|
||||
);
|
||||
attribute ORIG_REF_NAME : string;
|
||||
attribute ORIG_REF_NAME of data_bram_bank_blk_mem_gen_top : entity is "blk_mem_gen_top";
|
||||
end data_bram_bank_blk_mem_gen_top;
|
||||
|
||||
architecture STRUCTURE of data_bram_bank_blk_mem_gen_top is
|
||||
begin
|
||||
\valid.cstr\: entity work.data_bram_bank_blk_mem_gen_generic_cstr
|
||||
port map (
|
||||
addra(5 downto 0) => addra(5 downto 0),
|
||||
clka => clka,
|
||||
dina(31 downto 0) => dina(31 downto 0),
|
||||
douta(31 downto 0) => douta(31 downto 0),
|
||||
ena => ena,
|
||||
wea(0) => wea(0)
|
||||
);
|
||||
end STRUCTURE;
|
||||
library IEEE;
|
||||
use IEEE.STD_LOGIC_1164.ALL;
|
||||
library UNISIM;
|
||||
use UNISIM.VCOMPONENTS.ALL;
|
||||
entity data_bram_bank_blk_mem_gen_v8_4_4_synth is
|
||||
port (
|
||||
douta : out STD_LOGIC_VECTOR ( 31 downto 0 );
|
||||
clka : in STD_LOGIC;
|
||||
ena : in STD_LOGIC;
|
||||
addra : in STD_LOGIC_VECTOR ( 5 downto 0 );
|
||||
dina : in STD_LOGIC_VECTOR ( 31 downto 0 );
|
||||
wea : in STD_LOGIC_VECTOR ( 0 to 0 )
|
||||
);
|
||||
attribute ORIG_REF_NAME : string;
|
||||
attribute ORIG_REF_NAME of data_bram_bank_blk_mem_gen_v8_4_4_synth : entity is "blk_mem_gen_v8_4_4_synth";
|
||||
end data_bram_bank_blk_mem_gen_v8_4_4_synth;
|
||||
|
||||
architecture STRUCTURE of data_bram_bank_blk_mem_gen_v8_4_4_synth is
|
||||
begin
|
||||
\gnbram.gnativebmg.native_blk_mem_gen\: entity work.data_bram_bank_blk_mem_gen_top
|
||||
port map (
|
||||
addra(5 downto 0) => addra(5 downto 0),
|
||||
clka => clka,
|
||||
dina(31 downto 0) => dina(31 downto 0),
|
||||
douta(31 downto 0) => douta(31 downto 0),
|
||||
ena => ena,
|
||||
wea(0) => wea(0)
|
||||
);
|
||||
end STRUCTURE;
|
||||
library IEEE;
|
||||
use IEEE.STD_LOGIC_1164.ALL;
|
||||
library UNISIM;
|
||||
use UNISIM.VCOMPONENTS.ALL;
|
||||
entity data_bram_bank_blk_mem_gen_v8_4_4 is
|
||||
port (
|
||||
clka : in STD_LOGIC;
|
||||
rsta : in STD_LOGIC;
|
||||
ena : in STD_LOGIC;
|
||||
regcea : in STD_LOGIC;
|
||||
wea : in STD_LOGIC_VECTOR ( 0 to 0 );
|
||||
addra : in STD_LOGIC_VECTOR ( 5 downto 0 );
|
||||
dina : in STD_LOGIC_VECTOR ( 31 downto 0 );
|
||||
douta : out STD_LOGIC_VECTOR ( 31 downto 0 );
|
||||
clkb : in STD_LOGIC;
|
||||
rstb : in STD_LOGIC;
|
||||
enb : in STD_LOGIC;
|
||||
regceb : in STD_LOGIC;
|
||||
web : in STD_LOGIC_VECTOR ( 0 to 0 );
|
||||
addrb : in STD_LOGIC_VECTOR ( 5 downto 0 );
|
||||
dinb : in STD_LOGIC_VECTOR ( 31 downto 0 );
|
||||
doutb : out STD_LOGIC_VECTOR ( 31 downto 0 );
|
||||
injectsbiterr : in STD_LOGIC;
|
||||
injectdbiterr : in STD_LOGIC;
|
||||
eccpipece : in STD_LOGIC;
|
||||
sbiterr : out STD_LOGIC;
|
||||
dbiterr : out STD_LOGIC;
|
||||
rdaddrecc : out STD_LOGIC_VECTOR ( 5 downto 0 );
|
||||
sleep : in STD_LOGIC;
|
||||
deepsleep : in STD_LOGIC;
|
||||
shutdown : in STD_LOGIC;
|
||||
rsta_busy : out STD_LOGIC;
|
||||
rstb_busy : out STD_LOGIC;
|
||||
s_aclk : in STD_LOGIC;
|
||||
s_aresetn : in STD_LOGIC;
|
||||
s_axi_awid : in STD_LOGIC_VECTOR ( 3 downto 0 );
|
||||
s_axi_awaddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
|
||||
s_axi_awlen : in STD_LOGIC_VECTOR ( 7 downto 0 );
|
||||
s_axi_awsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
|
||||
s_axi_awburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
|
||||
s_axi_awvalid : in STD_LOGIC;
|
||||
s_axi_awready : out STD_LOGIC;
|
||||
s_axi_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
|
||||
s_axi_wstrb : in STD_LOGIC_VECTOR ( 0 to 0 );
|
||||
s_axi_wlast : in STD_LOGIC;
|
||||
s_axi_wvalid : in STD_LOGIC;
|
||||
s_axi_wready : out STD_LOGIC;
|
||||
s_axi_bid : out STD_LOGIC_VECTOR ( 3 downto 0 );
|
||||
s_axi_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
|
||||
s_axi_bvalid : out STD_LOGIC;
|
||||
s_axi_bready : in STD_LOGIC;
|
||||
s_axi_arid : in STD_LOGIC_VECTOR ( 3 downto 0 );
|
||||
s_axi_araddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
|
||||
s_axi_arlen : in STD_LOGIC_VECTOR ( 7 downto 0 );
|
||||
s_axi_arsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
|
||||
s_axi_arburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
|
||||
s_axi_arvalid : in STD_LOGIC;
|
||||
s_axi_arready : out STD_LOGIC;
|
||||
s_axi_rid : out STD_LOGIC_VECTOR ( 3 downto 0 );
|
||||
s_axi_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
|
||||
s_axi_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
|
||||
s_axi_rlast : out STD_LOGIC;
|
||||
s_axi_rvalid : out STD_LOGIC;
|
||||
s_axi_rready : in STD_LOGIC;
|
||||
s_axi_injectsbiterr : in STD_LOGIC;
|
||||
s_axi_injectdbiterr : in STD_LOGIC;
|
||||
s_axi_sbiterr : out STD_LOGIC;
|
||||
s_axi_dbiterr : out STD_LOGIC;
|
||||
s_axi_rdaddrecc : out STD_LOGIC_VECTOR ( 5 downto 0 )
|
||||
);
|
||||
attribute C_ADDRA_WIDTH : integer;
|
||||
attribute C_ADDRA_WIDTH of data_bram_bank_blk_mem_gen_v8_4_4 : entity is 6;
|
||||
attribute C_ADDRB_WIDTH : integer;
|
||||
attribute C_ADDRB_WIDTH of data_bram_bank_blk_mem_gen_v8_4_4 : entity is 6;
|
||||
attribute C_ALGORITHM : integer;
|
||||
attribute C_ALGORITHM of data_bram_bank_blk_mem_gen_v8_4_4 : entity is 1;
|
||||
attribute C_AXI_ID_WIDTH : integer;
|
||||
attribute C_AXI_ID_WIDTH of data_bram_bank_blk_mem_gen_v8_4_4 : entity is 4;
|
||||
attribute C_AXI_SLAVE_TYPE : integer;
|
||||
attribute C_AXI_SLAVE_TYPE of data_bram_bank_blk_mem_gen_v8_4_4 : entity is 0;
|
||||
attribute C_AXI_TYPE : integer;
|
||||
attribute C_AXI_TYPE of data_bram_bank_blk_mem_gen_v8_4_4 : entity is 1;
|
||||
attribute C_BYTE_SIZE : integer;
|
||||
attribute C_BYTE_SIZE of data_bram_bank_blk_mem_gen_v8_4_4 : entity is 9;
|
||||
attribute C_COMMON_CLK : integer;
|
||||
attribute C_COMMON_CLK of data_bram_bank_blk_mem_gen_v8_4_4 : entity is 0;
|
||||
attribute C_COUNT_18K_BRAM : string;
|
||||
attribute C_COUNT_18K_BRAM of data_bram_bank_blk_mem_gen_v8_4_4 : entity is "1";
|
||||
attribute C_COUNT_36K_BRAM : string;
|
||||
attribute C_COUNT_36K_BRAM of data_bram_bank_blk_mem_gen_v8_4_4 : entity is "0";
|
||||
attribute C_CTRL_ECC_ALGO : string;
|
||||
attribute C_CTRL_ECC_ALGO of data_bram_bank_blk_mem_gen_v8_4_4 : entity is "NONE";
|
||||
attribute C_DEFAULT_DATA : string;
|
||||
attribute C_DEFAULT_DATA of data_bram_bank_blk_mem_gen_v8_4_4 : entity is "0";
|
||||
attribute C_DISABLE_WARN_BHV_COLL : integer;
|
||||
attribute C_DISABLE_WARN_BHV_COLL of data_bram_bank_blk_mem_gen_v8_4_4 : entity is 0;
|
||||
attribute C_DISABLE_WARN_BHV_RANGE : integer;
|
||||
attribute C_DISABLE_WARN_BHV_RANGE of data_bram_bank_blk_mem_gen_v8_4_4 : entity is 0;
|
||||
attribute C_ELABORATION_DIR : string;
|
||||
attribute C_ELABORATION_DIR of data_bram_bank_blk_mem_gen_v8_4_4 : entity is "./";
|
||||
attribute C_ENABLE_32BIT_ADDRESS : integer;
|
||||
attribute C_ENABLE_32BIT_ADDRESS of data_bram_bank_blk_mem_gen_v8_4_4 : entity is 0;
|
||||
attribute C_EN_DEEPSLEEP_PIN : integer;
|
||||
attribute C_EN_DEEPSLEEP_PIN of data_bram_bank_blk_mem_gen_v8_4_4 : entity is 0;
|
||||
attribute C_EN_ECC_PIPE : integer;
|
||||
attribute C_EN_ECC_PIPE of data_bram_bank_blk_mem_gen_v8_4_4 : entity is 0;
|
||||
attribute C_EN_RDADDRA_CHG : integer;
|
||||
attribute C_EN_RDADDRA_CHG of data_bram_bank_blk_mem_gen_v8_4_4 : entity is 0;
|
||||
attribute C_EN_RDADDRB_CHG : integer;
|
||||
attribute C_EN_RDADDRB_CHG of data_bram_bank_blk_mem_gen_v8_4_4 : entity is 0;
|
||||
attribute C_EN_SAFETY_CKT : integer;
|
||||
attribute C_EN_SAFETY_CKT of data_bram_bank_blk_mem_gen_v8_4_4 : entity is 0;
|
||||
attribute C_EN_SHUTDOWN_PIN : integer;
|
||||
attribute C_EN_SHUTDOWN_PIN of data_bram_bank_blk_mem_gen_v8_4_4 : entity is 0;
|
||||
attribute C_EN_SLEEP_PIN : integer;
|
||||
attribute C_EN_SLEEP_PIN of data_bram_bank_blk_mem_gen_v8_4_4 : entity is 0;
|
||||
attribute C_EST_POWER_SUMMARY : string;
|
||||
attribute C_EST_POWER_SUMMARY of data_bram_bank_blk_mem_gen_v8_4_4 : entity is "Estimated Power for IP : 3.53845 mW";
|
||||
attribute C_FAMILY : string;
|
||||
attribute C_FAMILY of data_bram_bank_blk_mem_gen_v8_4_4 : entity is "artix7";
|
||||
attribute C_HAS_AXI_ID : integer;
|
||||
attribute C_HAS_AXI_ID of data_bram_bank_blk_mem_gen_v8_4_4 : entity is 0;
|
||||
attribute C_HAS_ENA : integer;
|
||||
attribute C_HAS_ENA of data_bram_bank_blk_mem_gen_v8_4_4 : entity is 1;
|
||||
attribute C_HAS_ENB : integer;
|
||||
attribute C_HAS_ENB of data_bram_bank_blk_mem_gen_v8_4_4 : entity is 0;
|
||||
attribute C_HAS_INJECTERR : integer;
|
||||
attribute C_HAS_INJECTERR of data_bram_bank_blk_mem_gen_v8_4_4 : entity is 0;
|
||||
attribute C_HAS_MEM_OUTPUT_REGS_A : integer;
|
||||
attribute C_HAS_MEM_OUTPUT_REGS_A of data_bram_bank_blk_mem_gen_v8_4_4 : entity is 0;
|
||||
attribute C_HAS_MEM_OUTPUT_REGS_B : integer;
|
||||
attribute C_HAS_MEM_OUTPUT_REGS_B of data_bram_bank_blk_mem_gen_v8_4_4 : entity is 0;
|
||||
attribute C_HAS_MUX_OUTPUT_REGS_A : integer;
|
||||
attribute C_HAS_MUX_OUTPUT_REGS_A of data_bram_bank_blk_mem_gen_v8_4_4 : entity is 0;
|
||||
attribute C_HAS_MUX_OUTPUT_REGS_B : integer;
|
||||
attribute C_HAS_MUX_OUTPUT_REGS_B of data_bram_bank_blk_mem_gen_v8_4_4 : entity is 0;
|
||||
attribute C_HAS_REGCEA : integer;
|
||||
attribute C_HAS_REGCEA of data_bram_bank_blk_mem_gen_v8_4_4 : entity is 0;
|
||||
attribute C_HAS_REGCEB : integer;
|
||||
attribute C_HAS_REGCEB of data_bram_bank_blk_mem_gen_v8_4_4 : entity is 0;
|
||||
attribute C_HAS_RSTA : integer;
|
||||
attribute C_HAS_RSTA of data_bram_bank_blk_mem_gen_v8_4_4 : entity is 0;
|
||||
attribute C_HAS_RSTB : integer;
|
||||
attribute C_HAS_RSTB of data_bram_bank_blk_mem_gen_v8_4_4 : entity is 0;
|
||||
attribute C_HAS_SOFTECC_INPUT_REGS_A : integer;
|
||||
attribute C_HAS_SOFTECC_INPUT_REGS_A of data_bram_bank_blk_mem_gen_v8_4_4 : entity is 0;
|
||||
attribute C_HAS_SOFTECC_OUTPUT_REGS_B : integer;
|
||||
attribute C_HAS_SOFTECC_OUTPUT_REGS_B of data_bram_bank_blk_mem_gen_v8_4_4 : entity is 0;
|
||||
attribute C_INITA_VAL : string;
|
||||
attribute C_INITA_VAL of data_bram_bank_blk_mem_gen_v8_4_4 : entity is "0";
|
||||
attribute C_INITB_VAL : string;
|
||||
attribute C_INITB_VAL of data_bram_bank_blk_mem_gen_v8_4_4 : entity is "0";
|
||||
attribute C_INIT_FILE : string;
|
||||
attribute C_INIT_FILE of data_bram_bank_blk_mem_gen_v8_4_4 : entity is "data_bram_bank.mem";
|
||||
attribute C_INIT_FILE_NAME : string;
|
||||
attribute C_INIT_FILE_NAME of data_bram_bank_blk_mem_gen_v8_4_4 : entity is "no_coe_file_loaded";
|
||||
attribute C_INTERFACE_TYPE : integer;
|
||||
attribute C_INTERFACE_TYPE of data_bram_bank_blk_mem_gen_v8_4_4 : entity is 0;
|
||||
attribute C_LOAD_INIT_FILE : integer;
|
||||
attribute C_LOAD_INIT_FILE of data_bram_bank_blk_mem_gen_v8_4_4 : entity is 0;
|
||||
attribute C_MEM_TYPE : integer;
|
||||
attribute C_MEM_TYPE of data_bram_bank_blk_mem_gen_v8_4_4 : entity is 0;
|
||||
attribute C_MUX_PIPELINE_STAGES : integer;
|
||||
attribute C_MUX_PIPELINE_STAGES of data_bram_bank_blk_mem_gen_v8_4_4 : entity is 0;
|
||||
attribute C_PRIM_TYPE : integer;
|
||||
attribute C_PRIM_TYPE of data_bram_bank_blk_mem_gen_v8_4_4 : entity is 1;
|
||||
attribute C_READ_DEPTH_A : integer;
|
||||
attribute C_READ_DEPTH_A of data_bram_bank_blk_mem_gen_v8_4_4 : entity is 64;
|
||||
attribute C_READ_DEPTH_B : integer;
|
||||
attribute C_READ_DEPTH_B of data_bram_bank_blk_mem_gen_v8_4_4 : entity is 64;
|
||||
attribute C_READ_LATENCY_A : integer;
|
||||
attribute C_READ_LATENCY_A of data_bram_bank_blk_mem_gen_v8_4_4 : entity is 1;
|
||||
attribute C_READ_LATENCY_B : integer;
|
||||
attribute C_READ_LATENCY_B of data_bram_bank_blk_mem_gen_v8_4_4 : entity is 1;
|
||||
attribute C_READ_WIDTH_A : integer;
|
||||
attribute C_READ_WIDTH_A of data_bram_bank_blk_mem_gen_v8_4_4 : entity is 32;
|
||||
attribute C_READ_WIDTH_B : integer;
|
||||
attribute C_READ_WIDTH_B of data_bram_bank_blk_mem_gen_v8_4_4 : entity is 32;
|
||||
attribute C_RSTRAM_A : integer;
|
||||
attribute C_RSTRAM_A of data_bram_bank_blk_mem_gen_v8_4_4 : entity is 0;
|
||||
attribute C_RSTRAM_B : integer;
|
||||
attribute C_RSTRAM_B of data_bram_bank_blk_mem_gen_v8_4_4 : entity is 0;
|
||||
attribute C_RST_PRIORITY_A : string;
|
||||
attribute C_RST_PRIORITY_A of data_bram_bank_blk_mem_gen_v8_4_4 : entity is "CE";
|
||||
attribute C_RST_PRIORITY_B : string;
|
||||
attribute C_RST_PRIORITY_B of data_bram_bank_blk_mem_gen_v8_4_4 : entity is "CE";
|
||||
attribute C_SIM_COLLISION_CHECK : string;
|
||||
attribute C_SIM_COLLISION_CHECK of data_bram_bank_blk_mem_gen_v8_4_4 : entity is "ALL";
|
||||
attribute C_USE_BRAM_BLOCK : integer;
|
||||
attribute C_USE_BRAM_BLOCK of data_bram_bank_blk_mem_gen_v8_4_4 : entity is 0;
|
||||
attribute C_USE_BYTE_WEA : integer;
|
||||
attribute C_USE_BYTE_WEA of data_bram_bank_blk_mem_gen_v8_4_4 : entity is 0;
|
||||
attribute C_USE_BYTE_WEB : integer;
|
||||
attribute C_USE_BYTE_WEB of data_bram_bank_blk_mem_gen_v8_4_4 : entity is 0;
|
||||
attribute C_USE_DEFAULT_DATA : integer;
|
||||
attribute C_USE_DEFAULT_DATA of data_bram_bank_blk_mem_gen_v8_4_4 : entity is 0;
|
||||
attribute C_USE_ECC : integer;
|
||||
attribute C_USE_ECC of data_bram_bank_blk_mem_gen_v8_4_4 : entity is 0;
|
||||
attribute C_USE_SOFTECC : integer;
|
||||
attribute C_USE_SOFTECC of data_bram_bank_blk_mem_gen_v8_4_4 : entity is 0;
|
||||
attribute C_USE_URAM : integer;
|
||||
attribute C_USE_URAM of data_bram_bank_blk_mem_gen_v8_4_4 : entity is 0;
|
||||
attribute C_WEA_WIDTH : integer;
|
||||
attribute C_WEA_WIDTH of data_bram_bank_blk_mem_gen_v8_4_4 : entity is 1;
|
||||
attribute C_WEB_WIDTH : integer;
|
||||
attribute C_WEB_WIDTH of data_bram_bank_blk_mem_gen_v8_4_4 : entity is 1;
|
||||
attribute C_WRITE_DEPTH_A : integer;
|
||||
attribute C_WRITE_DEPTH_A of data_bram_bank_blk_mem_gen_v8_4_4 : entity is 64;
|
||||
attribute C_WRITE_DEPTH_B : integer;
|
||||
attribute C_WRITE_DEPTH_B of data_bram_bank_blk_mem_gen_v8_4_4 : entity is 64;
|
||||
attribute C_WRITE_MODE_A : string;
|
||||
attribute C_WRITE_MODE_A of data_bram_bank_blk_mem_gen_v8_4_4 : entity is "WRITE_FIRST";
|
||||
attribute C_WRITE_MODE_B : string;
|
||||
attribute C_WRITE_MODE_B of data_bram_bank_blk_mem_gen_v8_4_4 : entity is "WRITE_FIRST";
|
||||
attribute C_WRITE_WIDTH_A : integer;
|
||||
attribute C_WRITE_WIDTH_A of data_bram_bank_blk_mem_gen_v8_4_4 : entity is 32;
|
||||
attribute C_WRITE_WIDTH_B : integer;
|
||||
attribute C_WRITE_WIDTH_B of data_bram_bank_blk_mem_gen_v8_4_4 : entity is 32;
|
||||
attribute C_XDEVICEFAMILY : string;
|
||||
attribute C_XDEVICEFAMILY of data_bram_bank_blk_mem_gen_v8_4_4 : entity is "artix7";
|
||||
attribute ORIG_REF_NAME : string;
|
||||
attribute ORIG_REF_NAME of data_bram_bank_blk_mem_gen_v8_4_4 : entity is "blk_mem_gen_v8_4_4";
|
||||
attribute downgradeipidentifiedwarnings : string;
|
||||
attribute downgradeipidentifiedwarnings of data_bram_bank_blk_mem_gen_v8_4_4 : entity is "yes";
|
||||
end data_bram_bank_blk_mem_gen_v8_4_4;
|
||||
|
||||
architecture STRUCTURE of data_bram_bank_blk_mem_gen_v8_4_4 is
|
||||
signal \<const0>\ : STD_LOGIC;
|
||||
begin
|
||||
dbiterr <= \<const0>\;
|
||||
doutb(31) <= \<const0>\;
|
||||
doutb(30) <= \<const0>\;
|
||||
doutb(29) <= \<const0>\;
|
||||
doutb(28) <= \<const0>\;
|
||||
doutb(27) <= \<const0>\;
|
||||
doutb(26) <= \<const0>\;
|
||||
doutb(25) <= \<const0>\;
|
||||
doutb(24) <= \<const0>\;
|
||||
doutb(23) <= \<const0>\;
|
||||
doutb(22) <= \<const0>\;
|
||||
doutb(21) <= \<const0>\;
|
||||
doutb(20) <= \<const0>\;
|
||||
doutb(19) <= \<const0>\;
|
||||
doutb(18) <= \<const0>\;
|
||||
doutb(17) <= \<const0>\;
|
||||
doutb(16) <= \<const0>\;
|
||||
doutb(15) <= \<const0>\;
|
||||
doutb(14) <= \<const0>\;
|
||||
doutb(13) <= \<const0>\;
|
||||
doutb(12) <= \<const0>\;
|
||||
doutb(11) <= \<const0>\;
|
||||
doutb(10) <= \<const0>\;
|
||||
doutb(9) <= \<const0>\;
|
||||
doutb(8) <= \<const0>\;
|
||||
doutb(7) <= \<const0>\;
|
||||
doutb(6) <= \<const0>\;
|
||||
doutb(5) <= \<const0>\;
|
||||
doutb(4) <= \<const0>\;
|
||||
doutb(3) <= \<const0>\;
|
||||
doutb(2) <= \<const0>\;
|
||||
doutb(1) <= \<const0>\;
|
||||
doutb(0) <= \<const0>\;
|
||||
rdaddrecc(5) <= \<const0>\;
|
||||
rdaddrecc(4) <= \<const0>\;
|
||||
rdaddrecc(3) <= \<const0>\;
|
||||
rdaddrecc(2) <= \<const0>\;
|
||||
rdaddrecc(1) <= \<const0>\;
|
||||
rdaddrecc(0) <= \<const0>\;
|
||||
rsta_busy <= \<const0>\;
|
||||
rstb_busy <= \<const0>\;
|
||||
s_axi_arready <= \<const0>\;
|
||||
s_axi_awready <= \<const0>\;
|
||||
s_axi_bid(3) <= \<const0>\;
|
||||
s_axi_bid(2) <= \<const0>\;
|
||||
s_axi_bid(1) <= \<const0>\;
|
||||
s_axi_bid(0) <= \<const0>\;
|
||||
s_axi_bresp(1) <= \<const0>\;
|
||||
s_axi_bresp(0) <= \<const0>\;
|
||||
s_axi_bvalid <= \<const0>\;
|
||||
s_axi_dbiterr <= \<const0>\;
|
||||
s_axi_rdaddrecc(5) <= \<const0>\;
|
||||
s_axi_rdaddrecc(4) <= \<const0>\;
|
||||
s_axi_rdaddrecc(3) <= \<const0>\;
|
||||
s_axi_rdaddrecc(2) <= \<const0>\;
|
||||
s_axi_rdaddrecc(1) <= \<const0>\;
|
||||
s_axi_rdaddrecc(0) <= \<const0>\;
|
||||
s_axi_rdata(31) <= \<const0>\;
|
||||
s_axi_rdata(30) <= \<const0>\;
|
||||
s_axi_rdata(29) <= \<const0>\;
|
||||
s_axi_rdata(28) <= \<const0>\;
|
||||
s_axi_rdata(27) <= \<const0>\;
|
||||
s_axi_rdata(26) <= \<const0>\;
|
||||
s_axi_rdata(25) <= \<const0>\;
|
||||
s_axi_rdata(24) <= \<const0>\;
|
||||
s_axi_rdata(23) <= \<const0>\;
|
||||
s_axi_rdata(22) <= \<const0>\;
|
||||
s_axi_rdata(21) <= \<const0>\;
|
||||
s_axi_rdata(20) <= \<const0>\;
|
||||
s_axi_rdata(19) <= \<const0>\;
|
||||
s_axi_rdata(18) <= \<const0>\;
|
||||
s_axi_rdata(17) <= \<const0>\;
|
||||
s_axi_rdata(16) <= \<const0>\;
|
||||
s_axi_rdata(15) <= \<const0>\;
|
||||
s_axi_rdata(14) <= \<const0>\;
|
||||
s_axi_rdata(13) <= \<const0>\;
|
||||
s_axi_rdata(12) <= \<const0>\;
|
||||
s_axi_rdata(11) <= \<const0>\;
|
||||
s_axi_rdata(10) <= \<const0>\;
|
||||
s_axi_rdata(9) <= \<const0>\;
|
||||
s_axi_rdata(8) <= \<const0>\;
|
||||
s_axi_rdata(7) <= \<const0>\;
|
||||
s_axi_rdata(6) <= \<const0>\;
|
||||
s_axi_rdata(5) <= \<const0>\;
|
||||
s_axi_rdata(4) <= \<const0>\;
|
||||
s_axi_rdata(3) <= \<const0>\;
|
||||
s_axi_rdata(2) <= \<const0>\;
|
||||
s_axi_rdata(1) <= \<const0>\;
|
||||
s_axi_rdata(0) <= \<const0>\;
|
||||
s_axi_rid(3) <= \<const0>\;
|
||||
s_axi_rid(2) <= \<const0>\;
|
||||
s_axi_rid(1) <= \<const0>\;
|
||||
s_axi_rid(0) <= \<const0>\;
|
||||
s_axi_rlast <= \<const0>\;
|
||||
s_axi_rresp(1) <= \<const0>\;
|
||||
s_axi_rresp(0) <= \<const0>\;
|
||||
s_axi_rvalid <= \<const0>\;
|
||||
s_axi_sbiterr <= \<const0>\;
|
||||
s_axi_wready <= \<const0>\;
|
||||
sbiterr <= \<const0>\;
|
||||
GND: unisim.vcomponents.GND
|
||||
port map (
|
||||
G => \<const0>\
|
||||
);
|
||||
inst_blk_mem_gen: entity work.data_bram_bank_blk_mem_gen_v8_4_4_synth
|
||||
port map (
|
||||
addra(5 downto 0) => addra(5 downto 0),
|
||||
clka => clka,
|
||||
dina(31 downto 0) => dina(31 downto 0),
|
||||
douta(31 downto 0) => douta(31 downto 0),
|
||||
ena => ena,
|
||||
wea(0) => wea(0)
|
||||
);
|
||||
end STRUCTURE;
|
||||
library IEEE;
|
||||
use IEEE.STD_LOGIC_1164.ALL;
|
||||
library UNISIM;
|
||||
use UNISIM.VCOMPONENTS.ALL;
|
||||
entity data_bram_bank is
|
||||
port (
|
||||
clka : in STD_LOGIC;
|
||||
ena : in STD_LOGIC;
|
||||
wea : in STD_LOGIC_VECTOR ( 0 to 0 );
|
||||
addra : in STD_LOGIC_VECTOR ( 5 downto 0 );
|
||||
dina : in STD_LOGIC_VECTOR ( 31 downto 0 );
|
||||
douta : out STD_LOGIC_VECTOR ( 31 downto 0 )
|
||||
);
|
||||
attribute NotValidForBitStream : boolean;
|
||||
attribute NotValidForBitStream of data_bram_bank : entity is true;
|
||||
attribute CHECK_LICENSE_TYPE : string;
|
||||
attribute CHECK_LICENSE_TYPE of data_bram_bank : entity is "data_bram_bank,blk_mem_gen_v8_4_4,{}";
|
||||
attribute downgradeipidentifiedwarnings : string;
|
||||
attribute downgradeipidentifiedwarnings of data_bram_bank : entity is "yes";
|
||||
attribute x_core_info : string;
|
||||
attribute x_core_info of data_bram_bank : entity is "blk_mem_gen_v8_4_4,Vivado 2019.2";
|
||||
end data_bram_bank;
|
||||
|
||||
architecture STRUCTURE of data_bram_bank is
|
||||
signal NLW_U0_dbiterr_UNCONNECTED : STD_LOGIC;
|
||||
signal NLW_U0_rsta_busy_UNCONNECTED : STD_LOGIC;
|
||||
signal NLW_U0_rstb_busy_UNCONNECTED : STD_LOGIC;
|
||||
signal NLW_U0_s_axi_arready_UNCONNECTED : STD_LOGIC;
|
||||
signal NLW_U0_s_axi_awready_UNCONNECTED : STD_LOGIC;
|
||||
signal NLW_U0_s_axi_bvalid_UNCONNECTED : STD_LOGIC;
|
||||
signal NLW_U0_s_axi_dbiterr_UNCONNECTED : STD_LOGIC;
|
||||
signal NLW_U0_s_axi_rlast_UNCONNECTED : STD_LOGIC;
|
||||
signal NLW_U0_s_axi_rvalid_UNCONNECTED : STD_LOGIC;
|
||||
signal NLW_U0_s_axi_sbiterr_UNCONNECTED : STD_LOGIC;
|
||||
signal NLW_U0_s_axi_wready_UNCONNECTED : STD_LOGIC;
|
||||
signal NLW_U0_sbiterr_UNCONNECTED : STD_LOGIC;
|
||||
signal NLW_U0_doutb_UNCONNECTED : STD_LOGIC_VECTOR ( 31 downto 0 );
|
||||
signal NLW_U0_rdaddrecc_UNCONNECTED : STD_LOGIC_VECTOR ( 5 downto 0 );
|
||||
signal NLW_U0_s_axi_bid_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
|
||||
signal NLW_U0_s_axi_bresp_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
|
||||
signal NLW_U0_s_axi_rdaddrecc_UNCONNECTED : STD_LOGIC_VECTOR ( 5 downto 0 );
|
||||
signal NLW_U0_s_axi_rdata_UNCONNECTED : STD_LOGIC_VECTOR ( 31 downto 0 );
|
||||
signal NLW_U0_s_axi_rid_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
|
||||
signal NLW_U0_s_axi_rresp_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
|
||||
attribute C_ADDRA_WIDTH : integer;
|
||||
attribute C_ADDRA_WIDTH of U0 : label is 6;
|
||||
attribute C_ADDRB_WIDTH : integer;
|
||||
attribute C_ADDRB_WIDTH of U0 : label is 6;
|
||||
attribute C_ALGORITHM : integer;
|
||||
attribute C_ALGORITHM of U0 : label is 1;
|
||||
attribute C_AXI_ID_WIDTH : integer;
|
||||
attribute C_AXI_ID_WIDTH of U0 : label is 4;
|
||||
attribute C_AXI_SLAVE_TYPE : integer;
|
||||
attribute C_AXI_SLAVE_TYPE of U0 : label is 0;
|
||||
attribute C_AXI_TYPE : integer;
|
||||
attribute C_AXI_TYPE of U0 : label is 1;
|
||||
attribute C_BYTE_SIZE : integer;
|
||||
attribute C_BYTE_SIZE of U0 : label is 9;
|
||||
attribute C_COMMON_CLK : integer;
|
||||
attribute C_COMMON_CLK of U0 : label is 0;
|
||||
attribute C_COUNT_18K_BRAM : string;
|
||||
attribute C_COUNT_18K_BRAM of U0 : label is "1";
|
||||
attribute C_COUNT_36K_BRAM : string;
|
||||
attribute C_COUNT_36K_BRAM of U0 : label is "0";
|
||||
attribute C_CTRL_ECC_ALGO : string;
|
||||
attribute C_CTRL_ECC_ALGO of U0 : label is "NONE";
|
||||
attribute C_DEFAULT_DATA : string;
|
||||
attribute C_DEFAULT_DATA of U0 : label is "0";
|
||||
attribute C_DISABLE_WARN_BHV_COLL : integer;
|
||||
attribute C_DISABLE_WARN_BHV_COLL of U0 : label is 0;
|
||||
attribute C_DISABLE_WARN_BHV_RANGE : integer;
|
||||
attribute C_DISABLE_WARN_BHV_RANGE of U0 : label is 0;
|
||||
attribute C_ELABORATION_DIR : string;
|
||||
attribute C_ELABORATION_DIR of U0 : label is "./";
|
||||
attribute C_ENABLE_32BIT_ADDRESS : integer;
|
||||
attribute C_ENABLE_32BIT_ADDRESS of U0 : label is 0;
|
||||
attribute C_EN_DEEPSLEEP_PIN : integer;
|
||||
attribute C_EN_DEEPSLEEP_PIN of U0 : label is 0;
|
||||
attribute C_EN_ECC_PIPE : integer;
|
||||
attribute C_EN_ECC_PIPE of U0 : label is 0;
|
||||
attribute C_EN_RDADDRA_CHG : integer;
|
||||
attribute C_EN_RDADDRA_CHG of U0 : label is 0;
|
||||
attribute C_EN_RDADDRB_CHG : integer;
|
||||
attribute C_EN_RDADDRB_CHG of U0 : label is 0;
|
||||
attribute C_EN_SAFETY_CKT : integer;
|
||||
attribute C_EN_SAFETY_CKT of U0 : label is 0;
|
||||
attribute C_EN_SHUTDOWN_PIN : integer;
|
||||
attribute C_EN_SHUTDOWN_PIN of U0 : label is 0;
|
||||
attribute C_EN_SLEEP_PIN : integer;
|
||||
attribute C_EN_SLEEP_PIN of U0 : label is 0;
|
||||
attribute C_EST_POWER_SUMMARY : string;
|
||||
attribute C_EST_POWER_SUMMARY of U0 : label is "Estimated Power for IP : 3.53845 mW";
|
||||
attribute C_FAMILY : string;
|
||||
attribute C_FAMILY of U0 : label is "artix7";
|
||||
attribute C_HAS_AXI_ID : integer;
|
||||
attribute C_HAS_AXI_ID of U0 : label is 0;
|
||||
attribute C_HAS_ENA : integer;
|
||||
attribute C_HAS_ENA of U0 : label is 1;
|
||||
attribute C_HAS_ENB : integer;
|
||||
attribute C_HAS_ENB of U0 : label is 0;
|
||||
attribute C_HAS_INJECTERR : integer;
|
||||
attribute C_HAS_INJECTERR of U0 : label is 0;
|
||||
attribute C_HAS_MEM_OUTPUT_REGS_A : integer;
|
||||
attribute C_HAS_MEM_OUTPUT_REGS_A of U0 : label is 0;
|
||||
attribute C_HAS_MEM_OUTPUT_REGS_B : integer;
|
||||
attribute C_HAS_MEM_OUTPUT_REGS_B of U0 : label is 0;
|
||||
attribute C_HAS_MUX_OUTPUT_REGS_A : integer;
|
||||
attribute C_HAS_MUX_OUTPUT_REGS_A of U0 : label is 0;
|
||||
attribute C_HAS_MUX_OUTPUT_REGS_B : integer;
|
||||
attribute C_HAS_MUX_OUTPUT_REGS_B of U0 : label is 0;
|
||||
attribute C_HAS_REGCEA : integer;
|
||||
attribute C_HAS_REGCEA of U0 : label is 0;
|
||||
attribute C_HAS_REGCEB : integer;
|
||||
attribute C_HAS_REGCEB of U0 : label is 0;
|
||||
attribute C_HAS_RSTA : integer;
|
||||
attribute C_HAS_RSTA of U0 : label is 0;
|
||||
attribute C_HAS_RSTB : integer;
|
||||
attribute C_HAS_RSTB of U0 : label is 0;
|
||||
attribute C_HAS_SOFTECC_INPUT_REGS_A : integer;
|
||||
attribute C_HAS_SOFTECC_INPUT_REGS_A of U0 : label is 0;
|
||||
attribute C_HAS_SOFTECC_OUTPUT_REGS_B : integer;
|
||||
attribute C_HAS_SOFTECC_OUTPUT_REGS_B of U0 : label is 0;
|
||||
attribute C_INITA_VAL : string;
|
||||
attribute C_INITA_VAL of U0 : label is "0";
|
||||
attribute C_INITB_VAL : string;
|
||||
attribute C_INITB_VAL of U0 : label is "0";
|
||||
attribute C_INIT_FILE : string;
|
||||
attribute C_INIT_FILE of U0 : label is "data_bram_bank.mem";
|
||||
attribute C_INIT_FILE_NAME : string;
|
||||
attribute C_INIT_FILE_NAME of U0 : label is "no_coe_file_loaded";
|
||||
attribute C_INTERFACE_TYPE : integer;
|
||||
attribute C_INTERFACE_TYPE of U0 : label is 0;
|
||||
attribute C_LOAD_INIT_FILE : integer;
|
||||
attribute C_LOAD_INIT_FILE of U0 : label is 0;
|
||||
attribute C_MEM_TYPE : integer;
|
||||
attribute C_MEM_TYPE of U0 : label is 0;
|
||||
attribute C_MUX_PIPELINE_STAGES : integer;
|
||||
attribute C_MUX_PIPELINE_STAGES of U0 : label is 0;
|
||||
attribute C_PRIM_TYPE : integer;
|
||||
attribute C_PRIM_TYPE of U0 : label is 1;
|
||||
attribute C_READ_DEPTH_A : integer;
|
||||
attribute C_READ_DEPTH_A of U0 : label is 64;
|
||||
attribute C_READ_DEPTH_B : integer;
|
||||
attribute C_READ_DEPTH_B of U0 : label is 64;
|
||||
attribute C_READ_LATENCY_A : integer;
|
||||
attribute C_READ_LATENCY_A of U0 : label is 1;
|
||||
attribute C_READ_LATENCY_B : integer;
|
||||
attribute C_READ_LATENCY_B of U0 : label is 1;
|
||||
attribute C_READ_WIDTH_A : integer;
|
||||
attribute C_READ_WIDTH_A of U0 : label is 32;
|
||||
attribute C_READ_WIDTH_B : integer;
|
||||
attribute C_READ_WIDTH_B of U0 : label is 32;
|
||||
attribute C_RSTRAM_A : integer;
|
||||
attribute C_RSTRAM_A of U0 : label is 0;
|
||||
attribute C_RSTRAM_B : integer;
|
||||
attribute C_RSTRAM_B of U0 : label is 0;
|
||||
attribute C_RST_PRIORITY_A : string;
|
||||
attribute C_RST_PRIORITY_A of U0 : label is "CE";
|
||||
attribute C_RST_PRIORITY_B : string;
|
||||
attribute C_RST_PRIORITY_B of U0 : label is "CE";
|
||||
attribute C_SIM_COLLISION_CHECK : string;
|
||||
attribute C_SIM_COLLISION_CHECK of U0 : label is "ALL";
|
||||
attribute C_USE_BRAM_BLOCK : integer;
|
||||
attribute C_USE_BRAM_BLOCK of U0 : label is 0;
|
||||
attribute C_USE_BYTE_WEA : integer;
|
||||
attribute C_USE_BYTE_WEA of U0 : label is 0;
|
||||
attribute C_USE_BYTE_WEB : integer;
|
||||
attribute C_USE_BYTE_WEB of U0 : label is 0;
|
||||
attribute C_USE_DEFAULT_DATA : integer;
|
||||
attribute C_USE_DEFAULT_DATA of U0 : label is 0;
|
||||
attribute C_USE_ECC : integer;
|
||||
attribute C_USE_ECC of U0 : label is 0;
|
||||
attribute C_USE_SOFTECC : integer;
|
||||
attribute C_USE_SOFTECC of U0 : label is 0;
|
||||
attribute C_USE_URAM : integer;
|
||||
attribute C_USE_URAM of U0 : label is 0;
|
||||
attribute C_WEA_WIDTH : integer;
|
||||
attribute C_WEA_WIDTH of U0 : label is 1;
|
||||
attribute C_WEB_WIDTH : integer;
|
||||
attribute C_WEB_WIDTH of U0 : label is 1;
|
||||
attribute C_WRITE_DEPTH_A : integer;
|
||||
attribute C_WRITE_DEPTH_A of U0 : label is 64;
|
||||
attribute C_WRITE_DEPTH_B : integer;
|
||||
attribute C_WRITE_DEPTH_B of U0 : label is 64;
|
||||
attribute C_WRITE_MODE_A : string;
|
||||
attribute C_WRITE_MODE_A of U0 : label is "WRITE_FIRST";
|
||||
attribute C_WRITE_MODE_B : string;
|
||||
attribute C_WRITE_MODE_B of U0 : label is "WRITE_FIRST";
|
||||
attribute C_WRITE_WIDTH_A : integer;
|
||||
attribute C_WRITE_WIDTH_A of U0 : label is 32;
|
||||
attribute C_WRITE_WIDTH_B : integer;
|
||||
attribute C_WRITE_WIDTH_B of U0 : label is 32;
|
||||
attribute C_XDEVICEFAMILY : string;
|
||||
attribute C_XDEVICEFAMILY of U0 : label is "artix7";
|
||||
attribute downgradeipidentifiedwarnings of U0 : label is "yes";
|
||||
attribute x_interface_info : string;
|
||||
attribute x_interface_info of clka : signal is "xilinx.com:interface:bram:1.0 BRAM_PORTA CLK";
|
||||
attribute x_interface_parameter : string;
|
||||
attribute x_interface_parameter of clka : signal is "XIL_INTERFACENAME BRAM_PORTA, MEM_SIZE 8192, MEM_WIDTH 32, MEM_ECC NONE, MASTER_TYPE OTHER, READ_LATENCY 1";
|
||||
attribute x_interface_info of ena : signal is "xilinx.com:interface:bram:1.0 BRAM_PORTA EN";
|
||||
attribute x_interface_info of addra : signal is "xilinx.com:interface:bram:1.0 BRAM_PORTA ADDR";
|
||||
attribute x_interface_info of dina : signal is "xilinx.com:interface:bram:1.0 BRAM_PORTA DIN";
|
||||
attribute x_interface_info of douta : signal is "xilinx.com:interface:bram:1.0 BRAM_PORTA DOUT";
|
||||
attribute x_interface_info of wea : signal is "xilinx.com:interface:bram:1.0 BRAM_PORTA WE";
|
||||
begin
|
||||
U0: entity work.data_bram_bank_blk_mem_gen_v8_4_4
|
||||
port map (
|
||||
addra(5 downto 0) => addra(5 downto 0),
|
||||
addrb(5 downto 0) => B"000000",
|
||||
clka => clka,
|
||||
clkb => '0',
|
||||
dbiterr => NLW_U0_dbiterr_UNCONNECTED,
|
||||
deepsleep => '0',
|
||||
dina(31 downto 0) => dina(31 downto 0),
|
||||
dinb(31 downto 0) => B"00000000000000000000000000000000",
|
||||
douta(31 downto 0) => douta(31 downto 0),
|
||||
doutb(31 downto 0) => NLW_U0_doutb_UNCONNECTED(31 downto 0),
|
||||
eccpipece => '0',
|
||||
ena => ena,
|
||||
enb => '0',
|
||||
injectdbiterr => '0',
|
||||
injectsbiterr => '0',
|
||||
rdaddrecc(5 downto 0) => NLW_U0_rdaddrecc_UNCONNECTED(5 downto 0),
|
||||
regcea => '0',
|
||||
regceb => '0',
|
||||
rsta => '0',
|
||||
rsta_busy => NLW_U0_rsta_busy_UNCONNECTED,
|
||||
rstb => '0',
|
||||
rstb_busy => NLW_U0_rstb_busy_UNCONNECTED,
|
||||
s_aclk => '0',
|
||||
s_aresetn => '0',
|
||||
s_axi_araddr(31 downto 0) => B"00000000000000000000000000000000",
|
||||
s_axi_arburst(1 downto 0) => B"00",
|
||||
s_axi_arid(3 downto 0) => B"0000",
|
||||
s_axi_arlen(7 downto 0) => B"00000000",
|
||||
s_axi_arready => NLW_U0_s_axi_arready_UNCONNECTED,
|
||||
s_axi_arsize(2 downto 0) => B"000",
|
||||
s_axi_arvalid => '0',
|
||||
s_axi_awaddr(31 downto 0) => B"00000000000000000000000000000000",
|
||||
s_axi_awburst(1 downto 0) => B"00",
|
||||
s_axi_awid(3 downto 0) => B"0000",
|
||||
s_axi_awlen(7 downto 0) => B"00000000",
|
||||
s_axi_awready => NLW_U0_s_axi_awready_UNCONNECTED,
|
||||
s_axi_awsize(2 downto 0) => B"000",
|
||||
s_axi_awvalid => '0',
|
||||
s_axi_bid(3 downto 0) => NLW_U0_s_axi_bid_UNCONNECTED(3 downto 0),
|
||||
s_axi_bready => '0',
|
||||
s_axi_bresp(1 downto 0) => NLW_U0_s_axi_bresp_UNCONNECTED(1 downto 0),
|
||||
s_axi_bvalid => NLW_U0_s_axi_bvalid_UNCONNECTED,
|
||||
s_axi_dbiterr => NLW_U0_s_axi_dbiterr_UNCONNECTED,
|
||||
s_axi_injectdbiterr => '0',
|
||||
s_axi_injectsbiterr => '0',
|
||||
s_axi_rdaddrecc(5 downto 0) => NLW_U0_s_axi_rdaddrecc_UNCONNECTED(5 downto 0),
|
||||
s_axi_rdata(31 downto 0) => NLW_U0_s_axi_rdata_UNCONNECTED(31 downto 0),
|
||||
s_axi_rid(3 downto 0) => NLW_U0_s_axi_rid_UNCONNECTED(3 downto 0),
|
||||
s_axi_rlast => NLW_U0_s_axi_rlast_UNCONNECTED,
|
||||
s_axi_rready => '0',
|
||||
s_axi_rresp(1 downto 0) => NLW_U0_s_axi_rresp_UNCONNECTED(1 downto 0),
|
||||
s_axi_rvalid => NLW_U0_s_axi_rvalid_UNCONNECTED,
|
||||
s_axi_sbiterr => NLW_U0_s_axi_sbiterr_UNCONNECTED,
|
||||
s_axi_wdata(31 downto 0) => B"00000000000000000000000000000000",
|
||||
s_axi_wlast => '0',
|
||||
s_axi_wready => NLW_U0_s_axi_wready_UNCONNECTED,
|
||||
s_axi_wstrb(0) => '0',
|
||||
s_axi_wvalid => '0',
|
||||
sbiterr => NLW_U0_sbiterr_UNCONNECTED,
|
||||
shutdown => '0',
|
||||
sleep => '0',
|
||||
wea(0) => wea(0),
|
||||
web(0) => '0'
|
||||
);
|
||||
end STRUCTURE;
|
||||
25
lacpu/rtl/xilinx_ip/data_sram_bank/data_bram_bank_stub.v
Normal file
25
lacpu/rtl/xilinx_ip/data_sram_bank/data_bram_bank_stub.v
Normal file
@@ -0,0 +1,25 @@
|
||||
// Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
|
||||
// --------------------------------------------------------------------------------
|
||||
// Tool Version: Vivado v.2019.2 (win64) Build 2708876 Wed Nov 6 21:40:23 MST 2019
|
||||
// Date : Fri Jul 21 18:49:49 2023
|
||||
// Host : BHKLaptop running 64-bit major release (build 9200)
|
||||
// Command : write_verilog -force -mode synth_stub
|
||||
// C:/Users/Unbal/Desktop/LoongArch/neulacpu/lacpu/rtl/xilinx_ip/data_sram_bank/data_bram_bank_stub.v
|
||||
// Design : data_bram_bank
|
||||
// Purpose : Stub declaration of top-level module interface
|
||||
// Device : xc7a200tfbg676-1
|
||||
// --------------------------------------------------------------------------------
|
||||
|
||||
// This empty module with port declaration file causes synthesis tools to infer a black box for IP.
|
||||
// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion.
|
||||
// Please paste the declaration into a Verilog source file or add the file as an additional source.
|
||||
(* x_core_info = "blk_mem_gen_v8_4_4,Vivado 2019.2" *)
|
||||
module data_bram_bank(clka, ena, wea, addra, dina, douta)
|
||||
/* synthesis syn_black_box black_box_pad_pin="clka,ena,wea[0:0],addra[5:0],dina[31:0],douta[31:0]" */;
|
||||
input clka;
|
||||
input ena;
|
||||
input [0:0]wea;
|
||||
input [5:0]addra;
|
||||
input [31:0]dina;
|
||||
output [31:0]douta;
|
||||
endmodule
|
||||
35
lacpu/rtl/xilinx_ip/data_sram_bank/data_bram_bank_stub.vhdl
Normal file
35
lacpu/rtl/xilinx_ip/data_sram_bank/data_bram_bank_stub.vhdl
Normal file
@@ -0,0 +1,35 @@
|
||||
-- Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
|
||||
-- --------------------------------------------------------------------------------
|
||||
-- Tool Version: Vivado v.2019.2 (win64) Build 2708876 Wed Nov 6 21:40:23 MST 2019
|
||||
-- Date : Fri Jul 21 18:49:49 2023
|
||||
-- Host : BHKLaptop running 64-bit major release (build 9200)
|
||||
-- Command : write_vhdl -force -mode synth_stub
|
||||
-- C:/Users/Unbal/Desktop/LoongArch/neulacpu/lacpu/rtl/xilinx_ip/data_sram_bank/data_bram_bank_stub.vhdl
|
||||
-- Design : data_bram_bank
|
||||
-- Purpose : Stub declaration of top-level module interface
|
||||
-- Device : xc7a200tfbg676-1
|
||||
-- --------------------------------------------------------------------------------
|
||||
library IEEE;
|
||||
use IEEE.STD_LOGIC_1164.ALL;
|
||||
|
||||
entity data_bram_bank is
|
||||
Port (
|
||||
clka : in STD_LOGIC;
|
||||
ena : in STD_LOGIC;
|
||||
wea : in STD_LOGIC_VECTOR ( 0 to 0 );
|
||||
addra : in STD_LOGIC_VECTOR ( 5 downto 0 );
|
||||
dina : in STD_LOGIC_VECTOR ( 31 downto 0 );
|
||||
douta : out STD_LOGIC_VECTOR ( 31 downto 0 )
|
||||
);
|
||||
|
||||
end data_bram_bank;
|
||||
|
||||
architecture stub of data_bram_bank is
|
||||
attribute syn_black_box : boolean;
|
||||
attribute black_box_pad_pin : string;
|
||||
attribute syn_black_box of stub : architecture is true;
|
||||
attribute black_box_pad_pin of stub : architecture is "clka,ena,wea[0:0],addra[5:0],dina[31:0],douta[31:0]";
|
||||
attribute x_core_info : string;
|
||||
attribute x_core_info of stub : architecture is "blk_mem_gen_v8_4_4,Vivado 2019.2";
|
||||
begin
|
||||
end;
|
||||
193187
lacpu/rtl/xilinx_ip/data_sram_bank/hdl/blk_mem_gen_v8_4_vhsyn_rfs.vhd
Normal file
193187
lacpu/rtl/xilinx_ip/data_sram_bank/hdl/blk_mem_gen_v8_4_vhsyn_rfs.vhd
Normal file
File diff suppressed because it is too large
Load Diff
359
lacpu/rtl/xilinx_ip/data_sram_bank/synth/data_bram_bank.vhd
Normal file
359
lacpu/rtl/xilinx_ip/data_sram_bank/synth/data_bram_bank.vhd
Normal file
@@ -0,0 +1,359 @@
|
||||
-- (c) Copyright 1995-2023 Xilinx, Inc. All rights reserved.
|
||||
--
|
||||
-- This file contains confidential and proprietary information
|
||||
-- of Xilinx, Inc. and is protected under U.S. and
|
||||
-- international copyright and other intellectual property
|
||||
-- laws.
|
||||
--
|
||||
-- DISCLAIMER
|
||||
-- This disclaimer is not a license and does not grant any
|
||||
-- rights to the materials distributed herewith. Except as
|
||||
-- otherwise provided in a valid license issued to you by
|
||||
-- Xilinx, and to the maximum extent permitted by applicable
|
||||
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
|
||||
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
|
||||
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
|
||||
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
|
||||
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
|
||||
-- (2) Xilinx shall not be liable (whether in contract or tort,
|
||||
-- including negligence, or under any other theory of
|
||||
-- liability) for any loss or damage of any kind or nature
|
||||
-- related to, arising under or in connection with these
|
||||
-- materials, including for any direct, or any indirect,
|
||||
-- special, incidental, or consequential loss or damage
|
||||
-- (including loss of data, profits, goodwill, or any type of
|
||||
-- loss or damage suffered as a result of any action brought
|
||||
-- by a third party) even if such damage or loss was
|
||||
-- reasonably foreseeable or Xilinx had been advised of the
|
||||
-- possibility of the same.
|
||||
--
|
||||
-- CRITICAL APPLICATIONS
|
||||
-- Xilinx products are not designed or intended to be fail-
|
||||
-- safe, or for use in any application requiring fail-safe
|
||||
-- performance, such as life-support or safety devices or
|
||||
-- systems, Class III medical devices, nuclear facilities,
|
||||
-- applications related to the deployment of airbags, or any
|
||||
-- other applications that could lead to death, personal
|
||||
-- injury, or severe property or environmental damage
|
||||
-- (individually and collectively, "Critical
|
||||
-- Applications"). Customer assumes the sole risk and
|
||||
-- liability of any use of Xilinx products in Critical
|
||||
-- Applications, subject only to applicable laws and
|
||||
-- regulations governing limitations on product liability.
|
||||
--
|
||||
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
|
||||
-- PART OF THIS FILE AT ALL TIMES.
|
||||
--
|
||||
-- DO NOT MODIFY THIS FILE.
|
||||
|
||||
-- IP VLNV: xilinx.com:ip:blk_mem_gen:8.4
|
||||
-- IP Revision: 4
|
||||
|
||||
LIBRARY ieee;
|
||||
USE ieee.std_logic_1164.ALL;
|
||||
USE ieee.numeric_std.ALL;
|
||||
|
||||
LIBRARY blk_mem_gen_v8_4_4;
|
||||
USE blk_mem_gen_v8_4_4.blk_mem_gen_v8_4_4;
|
||||
|
||||
ENTITY data_bram_bank IS
|
||||
PORT (
|
||||
clka : IN STD_LOGIC;
|
||||
ena : IN STD_LOGIC;
|
||||
wea : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
|
||||
addra : IN STD_LOGIC_VECTOR(5 DOWNTO 0);
|
||||
dina : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
|
||||
douta : OUT STD_LOGIC_VECTOR(31 DOWNTO 0)
|
||||
);
|
||||
END data_bram_bank;
|
||||
|
||||
ARCHITECTURE data_bram_bank_arch OF data_bram_bank IS
|
||||
ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING;
|
||||
ATTRIBUTE DowngradeIPIdentifiedWarnings OF data_bram_bank_arch: ARCHITECTURE IS "yes";
|
||||
COMPONENT blk_mem_gen_v8_4_4 IS
|
||||
GENERIC (
|
||||
C_FAMILY : STRING;
|
||||
C_XDEVICEFAMILY : STRING;
|
||||
C_ELABORATION_DIR : STRING;
|
||||
C_INTERFACE_TYPE : INTEGER;
|
||||
C_AXI_TYPE : INTEGER;
|
||||
C_AXI_SLAVE_TYPE : INTEGER;
|
||||
C_USE_BRAM_BLOCK : INTEGER;
|
||||
C_ENABLE_32BIT_ADDRESS : INTEGER;
|
||||
C_CTRL_ECC_ALGO : STRING;
|
||||
C_HAS_AXI_ID : INTEGER;
|
||||
C_AXI_ID_WIDTH : INTEGER;
|
||||
C_MEM_TYPE : INTEGER;
|
||||
C_BYTE_SIZE : INTEGER;
|
||||
C_ALGORITHM : INTEGER;
|
||||
C_PRIM_TYPE : INTEGER;
|
||||
C_LOAD_INIT_FILE : INTEGER;
|
||||
C_INIT_FILE_NAME : STRING;
|
||||
C_INIT_FILE : STRING;
|
||||
C_USE_DEFAULT_DATA : INTEGER;
|
||||
C_DEFAULT_DATA : STRING;
|
||||
C_HAS_RSTA : INTEGER;
|
||||
C_RST_PRIORITY_A : STRING;
|
||||
C_RSTRAM_A : INTEGER;
|
||||
C_INITA_VAL : STRING;
|
||||
C_HAS_ENA : INTEGER;
|
||||
C_HAS_REGCEA : INTEGER;
|
||||
C_USE_BYTE_WEA : INTEGER;
|
||||
C_WEA_WIDTH : INTEGER;
|
||||
C_WRITE_MODE_A : STRING;
|
||||
C_WRITE_WIDTH_A : INTEGER;
|
||||
C_READ_WIDTH_A : INTEGER;
|
||||
C_WRITE_DEPTH_A : INTEGER;
|
||||
C_READ_DEPTH_A : INTEGER;
|
||||
C_ADDRA_WIDTH : INTEGER;
|
||||
C_HAS_RSTB : INTEGER;
|
||||
C_RST_PRIORITY_B : STRING;
|
||||
C_RSTRAM_B : INTEGER;
|
||||
C_INITB_VAL : STRING;
|
||||
C_HAS_ENB : INTEGER;
|
||||
C_HAS_REGCEB : INTEGER;
|
||||
C_USE_BYTE_WEB : INTEGER;
|
||||
C_WEB_WIDTH : INTEGER;
|
||||
C_WRITE_MODE_B : STRING;
|
||||
C_WRITE_WIDTH_B : INTEGER;
|
||||
C_READ_WIDTH_B : INTEGER;
|
||||
C_WRITE_DEPTH_B : INTEGER;
|
||||
C_READ_DEPTH_B : INTEGER;
|
||||
C_ADDRB_WIDTH : INTEGER;
|
||||
C_HAS_MEM_OUTPUT_REGS_A : INTEGER;
|
||||
C_HAS_MEM_OUTPUT_REGS_B : INTEGER;
|
||||
C_HAS_MUX_OUTPUT_REGS_A : INTEGER;
|
||||
C_HAS_MUX_OUTPUT_REGS_B : INTEGER;
|
||||
C_MUX_PIPELINE_STAGES : INTEGER;
|
||||
C_HAS_SOFTECC_INPUT_REGS_A : INTEGER;
|
||||
C_HAS_SOFTECC_OUTPUT_REGS_B : INTEGER;
|
||||
C_USE_SOFTECC : INTEGER;
|
||||
C_USE_ECC : INTEGER;
|
||||
C_EN_ECC_PIPE : INTEGER;
|
||||
C_READ_LATENCY_A : INTEGER;
|
||||
C_READ_LATENCY_B : INTEGER;
|
||||
C_HAS_INJECTERR : INTEGER;
|
||||
C_SIM_COLLISION_CHECK : STRING;
|
||||
C_COMMON_CLK : INTEGER;
|
||||
C_DISABLE_WARN_BHV_COLL : INTEGER;
|
||||
C_EN_SLEEP_PIN : INTEGER;
|
||||
C_USE_URAM : INTEGER;
|
||||
C_EN_RDADDRA_CHG : INTEGER;
|
||||
C_EN_RDADDRB_CHG : INTEGER;
|
||||
C_EN_DEEPSLEEP_PIN : INTEGER;
|
||||
C_EN_SHUTDOWN_PIN : INTEGER;
|
||||
C_EN_SAFETY_CKT : INTEGER;
|
||||
C_DISABLE_WARN_BHV_RANGE : INTEGER;
|
||||
C_COUNT_36K_BRAM : STRING;
|
||||
C_COUNT_18K_BRAM : STRING;
|
||||
C_EST_POWER_SUMMARY : STRING
|
||||
);
|
||||
PORT (
|
||||
clka : IN STD_LOGIC;
|
||||
rsta : IN STD_LOGIC;
|
||||
ena : IN STD_LOGIC;
|
||||
regcea : IN STD_LOGIC;
|
||||
wea : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
|
||||
addra : IN STD_LOGIC_VECTOR(5 DOWNTO 0);
|
||||
dina : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
|
||||
douta : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
|
||||
clkb : IN STD_LOGIC;
|
||||
rstb : IN STD_LOGIC;
|
||||
enb : IN STD_LOGIC;
|
||||
regceb : IN STD_LOGIC;
|
||||
web : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
|
||||
addrb : IN STD_LOGIC_VECTOR(5 DOWNTO 0);
|
||||
dinb : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
|
||||
doutb : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
|
||||
injectsbiterr : IN STD_LOGIC;
|
||||
injectdbiterr : IN STD_LOGIC;
|
||||
eccpipece : IN STD_LOGIC;
|
||||
sbiterr : OUT STD_LOGIC;
|
||||
dbiterr : OUT STD_LOGIC;
|
||||
rdaddrecc : OUT STD_LOGIC_VECTOR(5 DOWNTO 0);
|
||||
sleep : IN STD_LOGIC;
|
||||
deepsleep : IN STD_LOGIC;
|
||||
shutdown : IN STD_LOGIC;
|
||||
rsta_busy : OUT STD_LOGIC;
|
||||
rstb_busy : OUT STD_LOGIC;
|
||||
s_aclk : IN STD_LOGIC;
|
||||
s_aresetn : IN STD_LOGIC;
|
||||
s_axi_awid : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
|
||||
s_axi_awaddr : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
|
||||
s_axi_awlen : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
|
||||
s_axi_awsize : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
|
||||
s_axi_awburst : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
|
||||
s_axi_awvalid : IN STD_LOGIC;
|
||||
s_axi_awready : OUT STD_LOGIC;
|
||||
s_axi_wdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
|
||||
s_axi_wstrb : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
|
||||
s_axi_wlast : IN STD_LOGIC;
|
||||
s_axi_wvalid : IN STD_LOGIC;
|
||||
s_axi_wready : OUT STD_LOGIC;
|
||||
s_axi_bid : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
|
||||
s_axi_bresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
|
||||
s_axi_bvalid : OUT STD_LOGIC;
|
||||
s_axi_bready : IN STD_LOGIC;
|
||||
s_axi_arid : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
|
||||
s_axi_araddr : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
|
||||
s_axi_arlen : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
|
||||
s_axi_arsize : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
|
||||
s_axi_arburst : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
|
||||
s_axi_arvalid : IN STD_LOGIC;
|
||||
s_axi_arready : OUT STD_LOGIC;
|
||||
s_axi_rid : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
|
||||
s_axi_rdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
|
||||
s_axi_rresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
|
||||
s_axi_rlast : OUT STD_LOGIC;
|
||||
s_axi_rvalid : OUT STD_LOGIC;
|
||||
s_axi_rready : IN STD_LOGIC;
|
||||
s_axi_injectsbiterr : IN STD_LOGIC;
|
||||
s_axi_injectdbiterr : IN STD_LOGIC;
|
||||
s_axi_sbiterr : OUT STD_LOGIC;
|
||||
s_axi_dbiterr : OUT STD_LOGIC;
|
||||
s_axi_rdaddrecc : OUT STD_LOGIC_VECTOR(5 DOWNTO 0)
|
||||
);
|
||||
END COMPONENT blk_mem_gen_v8_4_4;
|
||||
ATTRIBUTE X_CORE_INFO : STRING;
|
||||
ATTRIBUTE X_CORE_INFO OF data_bram_bank_arch: ARCHITECTURE IS "blk_mem_gen_v8_4_4,Vivado 2019.2";
|
||||
ATTRIBUTE CHECK_LICENSE_TYPE : STRING;
|
||||
ATTRIBUTE CHECK_LICENSE_TYPE OF data_bram_bank_arch : ARCHITECTURE IS "data_bram_bank,blk_mem_gen_v8_4_4,{}";
|
||||
ATTRIBUTE CORE_GENERATION_INFO : STRING;
|
||||
ATTRIBUTE CORE_GENERATION_INFO OF data_bram_bank_arch: ARCHITECTURE IS "data_bram_bank,blk_mem_gen_v8_4_4,{x_ipProduct=Vivado 2019.2,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=blk_mem_gen,x_ipVersion=8.4,x_ipCoreRevision=4,x_ipLanguage=VERILOG,x_ipSimLanguage=MIXED,C_FAMILY=artix7,C_XDEVICEFAMILY=artix7,C_ELABORATION_DIR=./,C_INTERFACE_TYPE=0,C_AXI_TYPE=1,C_AXI_SLAVE_TYPE=0,C_USE_BRAM_BLOCK=0,C_ENABLE_32BIT_ADDRESS=0,C_CTRL_ECC_ALGO=NONE,C_HAS_AXI_ID=0,C_AXI_ID_WIDTH=4,C_MEM_TYPE=0,C_BYTE_SIZE=9,C_ALGORITHM=1,C_PRIM_TYPE=1,C_LOAD_INIT_FILE=0,C_INIT_FILE_NAME=no_c" &
|
||||
"oe_file_loaded,C_INIT_FILE=data_bram_bank.mem,C_USE_DEFAULT_DATA=0,C_DEFAULT_DATA=0,C_HAS_RSTA=0,C_RST_PRIORITY_A=CE,C_RSTRAM_A=0,C_INITA_VAL=0,C_HAS_ENA=1,C_HAS_REGCEA=0,C_USE_BYTE_WEA=0,C_WEA_WIDTH=1,C_WRITE_MODE_A=WRITE_FIRST,C_WRITE_WIDTH_A=32,C_READ_WIDTH_A=32,C_WRITE_DEPTH_A=64,C_READ_DEPTH_A=64,C_ADDRA_WIDTH=6,C_HAS_RSTB=0,C_RST_PRIORITY_B=CE,C_RSTRAM_B=0,C_INITB_VAL=0,C_HAS_ENB=0,C_HAS_REGCEB=0,C_USE_BYTE_WEB=0,C_WEB_WIDTH=1,C_WRITE_MODE_B=WRITE_FIRST,C_WRITE_WIDTH_B=32,C_READ_WIDTH_B=32" &
|
||||
",C_WRITE_DEPTH_B=64,C_READ_DEPTH_B=64,C_ADDRB_WIDTH=6,C_HAS_MEM_OUTPUT_REGS_A=0,C_HAS_MEM_OUTPUT_REGS_B=0,C_HAS_MUX_OUTPUT_REGS_A=0,C_HAS_MUX_OUTPUT_REGS_B=0,C_MUX_PIPELINE_STAGES=0,C_HAS_SOFTECC_INPUT_REGS_A=0,C_HAS_SOFTECC_OUTPUT_REGS_B=0,C_USE_SOFTECC=0,C_USE_ECC=0,C_EN_ECC_PIPE=0,C_READ_LATENCY_A=1,C_READ_LATENCY_B=1,C_HAS_INJECTERR=0,C_SIM_COLLISION_CHECK=ALL,C_COMMON_CLK=0,C_DISABLE_WARN_BHV_COLL=0,C_EN_SLEEP_PIN=0,C_USE_URAM=0,C_EN_RDADDRA_CHG=0,C_EN_RDADDRB_CHG=0,C_EN_DEEPSLEEP_PIN=0,C_E" &
|
||||
"N_SHUTDOWN_PIN=0,C_EN_SAFETY_CKT=0,C_DISABLE_WARN_BHV_RANGE=0,C_COUNT_36K_BRAM=0,C_COUNT_18K_BRAM=1,C_EST_POWER_SUMMARY=Estimated Power for IP _ 3.53845 mW}";
|
||||
ATTRIBUTE X_INTERFACE_INFO : STRING;
|
||||
ATTRIBUTE X_INTERFACE_PARAMETER : STRING;
|
||||
ATTRIBUTE X_INTERFACE_INFO OF douta: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTA DOUT";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF dina: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTA DIN";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF addra: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTA ADDR";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF wea: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTA WE";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF ena: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTA EN";
|
||||
ATTRIBUTE X_INTERFACE_PARAMETER OF clka: SIGNAL IS "XIL_INTERFACENAME BRAM_PORTA, MEM_SIZE 8192, MEM_WIDTH 32, MEM_ECC NONE, MASTER_TYPE OTHER, READ_LATENCY 1";
|
||||
ATTRIBUTE X_INTERFACE_INFO OF clka: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTA CLK";
|
||||
BEGIN
|
||||
U0 : blk_mem_gen_v8_4_4
|
||||
GENERIC MAP (
|
||||
C_FAMILY => "artix7",
|
||||
C_XDEVICEFAMILY => "artix7",
|
||||
C_ELABORATION_DIR => "./",
|
||||
C_INTERFACE_TYPE => 0,
|
||||
C_AXI_TYPE => 1,
|
||||
C_AXI_SLAVE_TYPE => 0,
|
||||
C_USE_BRAM_BLOCK => 0,
|
||||
C_ENABLE_32BIT_ADDRESS => 0,
|
||||
C_CTRL_ECC_ALGO => "NONE",
|
||||
C_HAS_AXI_ID => 0,
|
||||
C_AXI_ID_WIDTH => 4,
|
||||
C_MEM_TYPE => 0,
|
||||
C_BYTE_SIZE => 9,
|
||||
C_ALGORITHM => 1,
|
||||
C_PRIM_TYPE => 1,
|
||||
C_LOAD_INIT_FILE => 0,
|
||||
C_INIT_FILE_NAME => "no_coe_file_loaded",
|
||||
C_INIT_FILE => "data_bram_bank.mem",
|
||||
C_USE_DEFAULT_DATA => 0,
|
||||
C_DEFAULT_DATA => "0",
|
||||
C_HAS_RSTA => 0,
|
||||
C_RST_PRIORITY_A => "CE",
|
||||
C_RSTRAM_A => 0,
|
||||
C_INITA_VAL => "0",
|
||||
C_HAS_ENA => 1,
|
||||
C_HAS_REGCEA => 0,
|
||||
C_USE_BYTE_WEA => 0,
|
||||
C_WEA_WIDTH => 1,
|
||||
C_WRITE_MODE_A => "WRITE_FIRST",
|
||||
C_WRITE_WIDTH_A => 32,
|
||||
C_READ_WIDTH_A => 32,
|
||||
C_WRITE_DEPTH_A => 64,
|
||||
C_READ_DEPTH_A => 64,
|
||||
C_ADDRA_WIDTH => 6,
|
||||
C_HAS_RSTB => 0,
|
||||
C_RST_PRIORITY_B => "CE",
|
||||
C_RSTRAM_B => 0,
|
||||
C_INITB_VAL => "0",
|
||||
C_HAS_ENB => 0,
|
||||
C_HAS_REGCEB => 0,
|
||||
C_USE_BYTE_WEB => 0,
|
||||
C_WEB_WIDTH => 1,
|
||||
C_WRITE_MODE_B => "WRITE_FIRST",
|
||||
C_WRITE_WIDTH_B => 32,
|
||||
C_READ_WIDTH_B => 32,
|
||||
C_WRITE_DEPTH_B => 64,
|
||||
C_READ_DEPTH_B => 64,
|
||||
C_ADDRB_WIDTH => 6,
|
||||
C_HAS_MEM_OUTPUT_REGS_A => 0,
|
||||
C_HAS_MEM_OUTPUT_REGS_B => 0,
|
||||
C_HAS_MUX_OUTPUT_REGS_A => 0,
|
||||
C_HAS_MUX_OUTPUT_REGS_B => 0,
|
||||
C_MUX_PIPELINE_STAGES => 0,
|
||||
C_HAS_SOFTECC_INPUT_REGS_A => 0,
|
||||
C_HAS_SOFTECC_OUTPUT_REGS_B => 0,
|
||||
C_USE_SOFTECC => 0,
|
||||
C_USE_ECC => 0,
|
||||
C_EN_ECC_PIPE => 0,
|
||||
C_READ_LATENCY_A => 1,
|
||||
C_READ_LATENCY_B => 1,
|
||||
C_HAS_INJECTERR => 0,
|
||||
C_SIM_COLLISION_CHECK => "ALL",
|
||||
C_COMMON_CLK => 0,
|
||||
C_DISABLE_WARN_BHV_COLL => 0,
|
||||
C_EN_SLEEP_PIN => 0,
|
||||
C_USE_URAM => 0,
|
||||
C_EN_RDADDRA_CHG => 0,
|
||||
C_EN_RDADDRB_CHG => 0,
|
||||
C_EN_DEEPSLEEP_PIN => 0,
|
||||
C_EN_SHUTDOWN_PIN => 0,
|
||||
C_EN_SAFETY_CKT => 0,
|
||||
C_DISABLE_WARN_BHV_RANGE => 0,
|
||||
C_COUNT_36K_BRAM => "0",
|
||||
C_COUNT_18K_BRAM => "1",
|
||||
C_EST_POWER_SUMMARY => "Estimated Power for IP : 3.53845 mW"
|
||||
)
|
||||
PORT MAP (
|
||||
clka => clka,
|
||||
rsta => '0',
|
||||
ena => ena,
|
||||
regcea => '0',
|
||||
wea => wea,
|
||||
addra => addra,
|
||||
dina => dina,
|
||||
douta => douta,
|
||||
clkb => '0',
|
||||
rstb => '0',
|
||||
enb => '0',
|
||||
regceb => '0',
|
||||
web => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
|
||||
addrb => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 6)),
|
||||
dinb => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
|
||||
injectsbiterr => '0',
|
||||
injectdbiterr => '0',
|
||||
eccpipece => '0',
|
||||
sleep => '0',
|
||||
deepsleep => '0',
|
||||
shutdown => '0',
|
||||
s_aclk => '0',
|
||||
s_aresetn => '0',
|
||||
s_axi_awid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
|
||||
s_axi_awaddr => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
|
||||
s_axi_awlen => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
|
||||
s_axi_awsize => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 3)),
|
||||
s_axi_awburst => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)),
|
||||
s_axi_awvalid => '0',
|
||||
s_axi_wdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
|
||||
s_axi_wstrb => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
|
||||
s_axi_wlast => '0',
|
||||
s_axi_wvalid => '0',
|
||||
s_axi_bready => '0',
|
||||
s_axi_arid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
|
||||
s_axi_araddr => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
|
||||
s_axi_arlen => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
|
||||
s_axi_arsize => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 3)),
|
||||
s_axi_arburst => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)),
|
||||
s_axi_arvalid => '0',
|
||||
s_axi_rready => '0',
|
||||
s_axi_injectsbiterr => '0',
|
||||
s_axi_injectdbiterr => '0'
|
||||
);
|
||||
END data_bram_bank_arch;
|
||||
Reference in New Issue
Block a user