[Modified] Debug & board test with cache & pass n58 with 40 MHz

lacpu/rtl/mycpu/csr.v

@@ -223,7 +223,10 @@ module csr(
 
                 timer_en    <= 1'b0;
         end
-        else if(except_en & ~stallreq_axi) begin
+        else if (stallreq_axi) begin
+            
+        end
+        else if(except_en) begin
             if((|csr_vec[7:0] & !inst_ertn) | excp_adef) begin
                 crmd[ `PLV] <=  2'b0;
                 crmd[  `IE] <=  1'b0;

lacpu/rtl/mycpu/exe_stage.v

@@ -80,7 +80,8 @@ module exe_stage
 
     wire [31:0] csr_wdata;
     wire [63:0] csr_bus;
-
+    
+    wire        excp_adef;  
     wire        excp_ale;
 
     assign {csr_vec_temp     ,//300:237
@@ -130,7 +131,9 @@ module exe_stage
                            inst      //31 :0
                           };
     
-    assign br_flush = br_taken;
+    assign br_flush = br_taken & ~(csr_cancel|csr_cancel_reg);
+
+    assign excp_adef = csr_vec[6];
 
     always @ (posedge clk) begin
         if (reset) begin
@@ -186,7 +189,7 @@ module exe_stage
     wire csr_cancel;
     reg  csr_cancel_reg;
     
-    assign csr_cancel = flush ? 1'b0 : |csr_vec[31:0];// TODO!
+    assign csr_cancel = /*flush ? 1'b0 :*/ |csr_vec[31:0] | excp_adef;// TODO!
 
     always @ (posedge clk) begin
         if (reset) begin

lacpu/rtl/mycpu/id_stage.v

@@ -106,12 +106,12 @@ module id_stage
                            csr_addr                             ,//228:215
                            csr_we                               ,//214:214
                            alu_op                               ,//213:202
-                           mul_div_op       & {4{pc_valid_r}}   ,//198:189
-                           mul_div_sign     & pc_valid_r        ,//197:197
-                           branch_op        & {9{pc_valid_r}}   ,//196:188
-                           store_op         & {3{pc_valid_r}}   ,//187:185
-                           load_op          & {6{pc_valid_r}}   ,//184:179
-                           reg_we           & pc_valid_r        ,//178:178
+                           mul_div_op       & { 4{pc_valid_r}}  ,//198:189
+                           mul_div_sign     &     pc_valid_r    ,//197:197
+                           branch_op        & { 9{pc_valid_r}}  ,//196:188
+                           store_op         & { 3{pc_valid_r}}  ,//187:185
+                           load_op          & { 6{pc_valid_r}}  ,//184:179
+                           reg_we           &     pc_valid_r    ,//178:178
                            src1_is_pc                           ,//177:177
                            src2_is_imm                          ,//176:176
                            src2_is_4                            ,//175:175
@@ -153,11 +153,11 @@ module id_stage
 
     always @ (posedge clk) begin
         if (reset) begin
-            inst_r <= 64'b0;
+            inst_r <= 32'b0;
             stall_flag <= 1'b0;
         end
         else if (flush) begin
-            inst_r <= 64'b0;
+            inst_r <= 32'b0;
             stall_flag <= 1'b0;
         end
         //if not stall, get inst from inst_sram

lacpu/rtl/mycpu/if_stage.v

@@ -69,7 +69,7 @@ module if_stage
     assign next_pc = br_taken ? br_target : seq_pc;
 
 
-    assign inst_sram_en     = flush | (br_taken ? 1'b0 : pc_valid);
+    assign inst_sram_en     = (/*flush |*/ br_taken) ? 1'b0 : pc_valid;
     assign inst_sram_we     = 4'h0;
     assign inst_sram_addr   = fs_pc;
     assign inst_sram_wdata  = 32'b0;