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[Add] add div.w[u], mod.w[u]

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包焕垲
2023-05-27 23:52:30 +08:00
parent 9a72e27ca4
commit 3b43e06054
9 changed files with 271 additions and 35 deletions
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38
lacpu/rtl/cpu/cpu_top.v
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@@ -15,6 +15,24 @@ module mycpu_top(
output [31:0] data_sram_addr,
output [31:0] data_sram_wdata,
input [31:0] data_sram_rdata,
//div
output [31:0] div_divisor_data,
output div_divisor_valid,
input div_divisor_ready,
output [31:0] div_dividend_data,
output div_dividend_valid,
input div_dividend_ready,
input div_dout_valid,
input [63:0] div_dout_data,
//divu
output [31:0] divu_divisor_data,
output divu_divisor_valid,
input divu_divisor_ready,
output [31:0] divu_dividend_data,
output divu_dividend_valid,
input divu_dividend_ready,
input divu_dout_valid,
input [63:0] divu_dout_data,
// trace debug interface
output [31:0] debug_wb_pc,
output [ 3:0] debug_wb_rf_wen,
@@ -107,7 +125,25 @@ module mycpu_top(
.data_sram_en (data_sram_en ),
.data_sram_wen (data_sram_wen ),
.data_sram_addr (data_sram_addr ),
.data_sram_wdata(data_sram_wdata)
.data_sram_wdata(data_sram_wdata),
//div
.div_divisor_data (div_divisor_data ),
.div_divisor_valid (div_divisor_valid ),
.div_divisor_ready (div_divisor_ready ),
.div_dividend_data (div_dividend_data ),
.div_dividend_valid (div_dividend_valid ),
.div_dividend_ready (div_dividend_ready ),
.div_dout_valid (div_dout_valid ),
.div_dout_data (div_dout_data ),
//divu
.divu_divisor_data (divu_divisor_data ),
.divu_divisor_valid (divu_divisor_valid ),
.divu_divisor_ready (divu_divisor_ready ),
.divu_dividend_data (divu_dividend_data ),
.divu_dividend_valid(divu_dividend_valid),
.divu_dividend_ready(divu_dividend_ready),
.divu_dout_valid (divu_dout_valid ),
.divu_dout_data (divu_dout_data )
);
// MEM stage
mem_stage mem_stage(