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[Add] switch to 7-stage and pass func test

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包焕垲
2023-07-28 15:29:06 +08:00
parent bf2dd4655b
commit 3a070d35fc
12 changed files with 431 additions and 305 deletions
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81
lacpu/rtl/mycpu/exe_stage.v
View File

@@ -16,11 +16,14 @@ module exe_stage
//output stallreq_es_for_cache, //output stallreq_es_for_cache,
input [DS_TO_ES_BUS_WD -1:0] ds_to_es_bus, input [DS_TO_ES_BUS_WD -1:0] ds_to_es_bus,
output [ES_TO_MS_BUS_WD -1:0] es_to_ms_bus, output [ES_TO_MS_BUS_WD -1:0] es_to_ms1_bus,
input [MS_TO_ES_BUS_WD -1:0] ms_to_es_bus,
input [MS_TO_ES_BUS_WD -1:0] ms1_to_es_bus,
input [MS_TO_ES_BUS_WD -1:0] ms_to_es_bus,
input [WS_TO_ES_BUS_WD -1:0] ws_to_es_bus, input [WS_TO_ES_BUS_WD -1:0] ws_to_es_bus,
output [BR_BUS_WD -1:0] br_bus, output [BR_BUS_WD -1:0] br_bus,
input br_taken_buffer,
output data_sram_en, output data_sram_en,
output [ 3:0] data_sram_we, output [ 3:0] data_sram_we,
@@ -56,6 +59,9 @@ module exe_stage
wire [31:0] es_pc; wire [31:0] es_pc;
wire [31:0] inst; wire [31:0] inst;
wire ms1_reg_we;
wire [ 4:0] ms1_dest;
wire [31:0] ms1_result;
wire ms_reg_we; wire ms_reg_we;
wire [ 4:0] ms_dest; wire [ 4:0] ms_dest;
wire [31:0] ms_result; wire [31:0] ms_result;
@@ -111,6 +117,11 @@ module exe_stage
inst //31 :0 inst //31 :0
} = ds_to_es_bus_r; } = ds_to_es_bus_r;
assign {ms1_reg_we,
ms1_dest,
ms1_result
} = ms1_to_es_bus;
assign {ms_reg_we, assign {ms_reg_we,
ms_dest, ms_dest,
ms_result ms_result
@@ -121,19 +132,19 @@ module exe_stage
ws_result ws_result
} = ws_to_es_bus; } = ws_to_es_bus;
assign es_to_ms_bus = {csr_vec ,//270:207 assign es_to_ms1_bus = {csr_vec ,//270:207
csr_bus ,//206:143 csr_bus ,//206:143
load_op ,//142:137 load_op ,//142:137
store_op ,//136:134 store_op ,//136:134
reg_we ,//133:133 reg_we ,//133:133
dest ,//132:128 dest ,//132:128
es_result,//127:96 es_result,//127:96
src1 ,//95 :64 src1 ,//95 :64
es_pc ,//63 :32 es_pc ,//63 :32
inst //31 :0 inst //31 :0
}; };
assign br_flush = br_taken & ~(csr_cancel|csr_cancel_reg); assign br_flush = (br_taken & ~(csr_cancel|csr_cancel_reg))/* | br_taken_buffer*/; // TODO!
assign excp_adef = csr_vec[6]; assign excp_adef = csr_vec[6];
@@ -158,12 +169,14 @@ module exe_stage
end end
end end
assign src1 = ms_reg_we & (ms_dest == rj ) & (rj != 1'b0) ? ms_result : assign src1 = ms1_reg_we & (ms1_dest == rj ) & (rj != 1'b0) ? ms1_result : // TODO!
ws_reg_we & (ws_dest == rj ) & (rj != 1'b0) ? ws_result : ms_reg_we & (ms_dest == rj ) & (rj != 1'b0) ? ms_result :
rj_value; ws_reg_we & (ws_dest == rj ) & (rj != 1'b0) ? ws_result :
assign src2 = ms_reg_we & (ms_dest == rkd) & (rkd != 1'b0) ? ms_result : rj_value;
ws_reg_we & (ws_dest == rkd) & (rkd != 1'b0) ? ws_result : assign src2 = ms1_reg_we & (ms1_dest == rkd) & (rkd != 1'b0) ? ms1_result : // TODO!
rkd_value; ms_reg_we & (ms_dest == rkd) & (rkd != 1'b0) ? ms_result :
ws_reg_we & (ws_dest == rkd) & (rkd != 1'b0) ? ws_result :
rkd_value;
assign alu_src1 = src1_is_pc ? es_pc : assign alu_src1 = src1_is_pc ? es_pc :
src1; src1;
@@ -191,7 +204,7 @@ module exe_stage
wire csr_cancel; wire csr_cancel;
reg csr_cancel_reg; reg csr_cancel_reg;
assign csr_cancel = /*flush ? 1'b0 :*/ |csr_vec[31:0] | excp_adef;// TODO? assign csr_cancel = |csr_vec[31:0] | excp_adef;
always @ (posedge clk) begin always @ (posedge clk) begin
if (reset) begin if (reset) begin
@@ -254,31 +267,5 @@ module exe_stage
assign csr_vec = {csr_vec_temp[63:8], excp_ale, csr_vec_temp[6:0]}; assign csr_vec = {csr_vec_temp[63:8], excp_ale, csr_vec_temp[6:0]};
assign stallreq_es = stallreq_for_mul_div; assign stallreq_es = stallreq_for_mul_div;
// always @(posedge clk) begin
// if (reset) begin
// stallreq_es_for_cache_r <= 1'b0;
// end
// else if (flush) begin
// stallreq_es_for_cache_r <= 1'b0;
// end
// //nop, id stall and ex not stall
// else if (stall[2] & (!stall[3])) begin
// stallreq_es_for_cache_r <= 1'b0;
// end
// //nop, id not stall and br_bus[32]
// else if (!stall[2] & br_flush) begin
// stallreq_es_for_cache_r <= 1'b0;
// end
// // id not stall so can go on
// else if (!stall[2] & (|load_op | |store_op)) begin
// stallreq_es_for_cache_r <= 1'b1;
// end
// else begin
// stallreq_es_for_cache_r <= 1'b0;
// end
// end
// assign stallreq_es_for_cache = stallreq_es_for_cache_r;
endmodule endmodule

156
lacpu/rtl/mycpu/id_stage.v
View File

@@ -1,6 +1,6 @@
module id_stage module id_stage
#( #(
parameter FS_TO_DS_BUS_WD = 65, parameter FS_TO_DS_BUS_WD = 34,
parameter DS_TO_ES_BUS_WD = 301, parameter DS_TO_ES_BUS_WD = 301,
parameter WS_TO_RF_BUS_WD = 38 parameter WS_TO_RF_BUS_WD = 38
) )
@@ -14,19 +14,20 @@ module id_stage
output stallreq_ds, output stallreq_ds,
input pc_valid, //input pc_valid,
input [31:0] inst_sram_rdata, input [31:0] inst_sram_rdata,
input [ 1:0] csr_plv, input [ 1:0] csr_plv,
input csr_has_int, input csr_has_int,
input [FS_TO_DS_BUS_WD -1:0] fs_to_ds_bus, input [FS_TO_DS_BUS_WD -1:0] fs2_to_ds_bus,
input [WS_TO_RF_BUS_WD -1:0] ws_to_rf_bus, input [WS_TO_RF_BUS_WD -1:0] ws_to_rf_bus,
output [DS_TO_ES_BUS_WD -1:0] ds_to_es_bus output [DS_TO_ES_BUS_WD -1:0] ds_to_es_bus
); );
reg [FS_TO_DS_BUS_WD -1:0] fs_to_ds_bus_r; reg [FS_TO_DS_BUS_WD -1:0] fs2_to_ds_bus_r;
reg pc_valid_r; //reg pc_valid_r;
reg [31:0] inst_r; reg [31:0] inst_sram_rdata_buffer;
reg [31:0] inst_sram_rdata_r;
reg stall_flag; reg stall_flag;
reg [ 6:0] es_load_buffer; reg [ 6:0] es_load_buffer;
@@ -35,6 +36,8 @@ module id_stage
wire br_flush; wire br_flush;
wire [31:0] ds_pc; wire [31:0] ds_pc;
wire pc_valid;
wire src1_is_pc; wire src1_is_pc;
wire src2_is_imm; wire src2_is_imm;
wire src2_is_4; wire src2_is_4;
@@ -80,16 +83,15 @@ module id_stage
wire stallreq_csr; wire stallreq_csr;
wire excp_adef; wire excp_adef;
wire [31:0] csr_vec_h;
wire [31:0] csr_vec_l; wire [31:0] csr_vec_l;
wire [63:0] csr_vec; wire [63:0] csr_vec;
assign {csr_vec_h, assign {pc_valid,
excp_adef, excp_adef,
ds_pc ds_pc
} = fs_to_ds_bus_r; } = fs2_to_ds_bus_r;
assign csr_vec = {csr_vec_h, csr_vec_l}; assign csr_vec = {32'b0, csr_vec_l};
assign br_flush = br_taken; assign br_flush = br_taken;
@@ -100,83 +102,75 @@ module id_stage
assign ds_to_es_bus = {csr_vec & {64{pc_valid_r}} ,//300:237 assign ds_to_es_bus = {csr_vec & {64{pc_valid}} ,//300:237
csr_op ,//236:230 csr_op ,//236:230
csr_wdata_sel ,//229:229 csr_wdata_sel ,//229:229
csr_addr ,//228:215 csr_addr ,//228:215
csr_we ,//214:214 csr_we ,//214:214
alu_op ,//213:202 alu_op ,//213:202
mul_div_op & { 4{pc_valid_r}} ,//198:189 mul_div_op & { 4{pc_valid}} ,//198:189
mul_div_sign & pc_valid_r ,//197:197 mul_div_sign & pc_valid ,//197:197
branch_op & { 9{pc_valid_r}} ,//196:188 branch_op & { 9{pc_valid}} ,//196:188
store_op & { 3{pc_valid_r}} ,//187:185 store_op & { 3{pc_valid}} ,//187:185
load_op & { 6{pc_valid_r}} ,//184:179 load_op & { 6{pc_valid}} ,//184:179
reg_we & pc_valid_r ,//178:178 reg_we & pc_valid ,//178:178
src1_is_pc ,//177:177 src1_is_pc ,//177:177
src2_is_imm ,//176:176 src2_is_imm ,//176:176
src2_is_4 ,//175:175 src2_is_4 ,//175:175
rj ,//174:170 rj ,//174:170
rkd ,//169:165 rkd ,//169:165
rj_value ,//164:133 rj_value ,//164:133
rkd_value ,//132:101 rkd_value ,//132:101
dest ,//100:96 dest ,//100:96
imm ,//95 :64 imm ,//95 :64
ds_pc ,//63 :32 ds_pc ,//63 :32
inst & {32{pc_valid_r}} //31 :0 inst & {32{pc_valid}} //31 :0
}; };
always @ (posedge clk)begin
always @(posedge clk) begin
if (reset) begin if (reset) begin
pc_valid_r <= 1'b0; fs2_to_ds_bus_r <= 0;
fs_to_ds_bus_r <= 0; inst_sram_rdata_r <= 0;
stall_flag <= 0;
end end
else if (flush) begin else if (flush) begin
pc_valid_r <= 1'b0; fs2_to_ds_bus_r <= 0;
fs_to_ds_bus_r <= 0; inst_sram_rdata_r <= 0;
stall_flag <= 0;
end end
//nop, ID stall and EX not stall else if ((!stall[1]) & (!stall[2]) & br_flush) begin
else if (stall[1] & (!stall[2]))begin fs2_to_ds_bus_r <= 0;
pc_valid_r <= 1'b0; inst_sram_rdata_r <= 0;
fs_to_ds_bus_r <= 0; stall_flag <= 0;
end end
//nop, ID not stall but branch else if (stall[1] & (!stall[2])) begin
else if (!stall[1] & br_flush) begin fs2_to_ds_bus_r <= 0;
pc_valid_r <= 1'b0; inst_sram_rdata_r <= 0;
fs_to_ds_bus_r <= 0; stall_flag <= 0;
end end
// ID not stall so go on else if ((!stall[1]) & stall_flag) begin
else if (!stall[1]) begin fs2_to_ds_bus_r <= fs2_to_ds_bus;
pc_valid_r <= pc_valid; inst_sram_rdata_r <= inst_sram_rdata_buffer;
fs_to_ds_bus_r <= fs_to_ds_bus; stall_flag <= 0;
end
else if ((!stall[1]) & (!stall_flag)) begin
fs2_to_ds_bus_r <= fs2_to_ds_bus;
inst_sram_rdata_r <= inst_sram_rdata;
stall_flag <= 0;
end
else if ((!stall_flag) & br_flush) begin
inst_sram_rdata_buffer <= 0;
stall_flag <= 1'b1;
end
else if (!stall_flag) begin
inst_sram_rdata_buffer <= inst_sram_rdata;
stall_flag <= 1'b1;
end end
end end
always @ (posedge clk) begin assign next_inst = inst_sram_rdata_r;
if (reset) begin assign inst = !pc_valid ? 32'b0 : next_inst;
inst_r <= 64'b0;
stall_flag <= 1'b0;
end
else if (flush) begin
inst_r <= 64'b0;
stall_flag <= 1'b0;
end
//if not stall, get inst from inst_sram
else if (!stall[1]) begin
inst_r <= inst_sram_rdata;
stall_flag <= 1'b0;
end
else if (stall_flag) begin
end
//if stall and id stall, get inst from inst_ram ?
else if (stall[1]&stall[2]) begin
inst_r <= inst_sram_rdata;
stall_flag <= 1'b1;
end
end
assign next_inst = stall_flag ? inst_r : inst_sram_rdata;
assign inst = ~pc_valid_r ? 32'b0 : next_inst;
inst_decoder u_inst_decoder( inst_decoder u_inst_decoder(
.inst (inst ), .inst (inst ),
@@ -250,8 +244,12 @@ module id_stage
} = es_load_buffer; } = es_load_buffer;
assign es_is_csr = es_csr_buffer; assign es_is_csr = es_csr_buffer;
//ex段为load指令，且发生数据相关时，id段需要被暂停 //ex段为load指令，且发生数据相关时，id段需要被暂停
assign stallreq_load = es_is_load & es_reg_we & ((es_dest==rj & rj!=0)|(es_dest==rkd & rkd!=0)); assign stallreq_load = es_is_load & es_reg_we & ((es_dest==rj & rj!=0)|(es_dest==rkd & rkd!=0)); //TODO?
assign stallreq_csr = es_is_csr & es_reg_we & ((es_dest==rj & rj!=0)|(es_dest==rkd & rkd!=0)); assign stallreq_csr = es_is_csr & es_reg_we & ((es_dest==rj & rj!=0)|(es_dest==rkd & rkd!=0));
assign stallreq_ds = stallreq_load | stallreq_csr;
wire stallreq_forward;
assign stallreq_forward = es_reg_we & ((es_dest==rj & rj!=0)|(es_dest==rkd & rkd!=0)); // TODO!
assign stallreq_ds = stallreq_load | stallreq_csr/* | stallreq_forward*/;
endmodule endmodule

82
lacpu/rtl/mycpu/if_stage.v
View File

@@ -1,7 +1,7 @@
module if_stage module if1_stage
#( #(
parameter BR_BUS_WD = 33, parameter BR_BUS_WD = 33,
parameter FS_TO_DS_BUS_WD = 65 parameter FS_TO_DS_BUS_WD = 34
) )
( (
input clk , input clk ,
@@ -12,23 +12,18 @@ module if_stage
input [31:0] new_pc, input [31:0] new_pc,
//output stallreq_fs_for_cache,
output inst_sram_en , output inst_sram_en ,
output [ 3:0] inst_sram_we , output [ 3:0] inst_sram_we ,
output [31:0] inst_sram_addr , output [31:0] inst_sram_addr ,
output [31:0] inst_sram_wdata, output [31:0] inst_sram_wdata,
input [BR_BUS_WD -1:0] br_bus, input [BR_BUS_WD -1:0] br_bus,
output [FS_TO_DS_BUS_WD -1:0] fs_to_ds_bus output [FS_TO_DS_BUS_WD -1:0] fs1_to_fs2_bus
); );
reg pc_valid; reg pc_valid;
reg [31:0] fs_pc; reg [31:0] fs_pc;
reg excp_adef; reg excp_adef;
reg [31:0] csr_vec_h;
reg stallreq_fs_for_cache_r;
wire [31:0] seq_pc; wire [31:0] seq_pc;
wire [31:0] next_pc; wire [31:0] next_pc;
@@ -37,10 +32,10 @@ module if_stage
wire [31:0] br_target; wire [31:0] br_target;
assign fs_to_ds_bus = {csr_vec_h, //64:33 assign fs1_to_fs2_bus = {inst_sram_en, //33:33
excp_adef, //32:32 excp_adef, //32:32
fs_pc //31:0 fs_pc //31:0
}; };
assign {br_taken, assign {br_taken,
br_target br_target
@@ -51,44 +46,65 @@ module if_stage
pc_valid <= 1'b0; pc_valid <= 1'b0;
fs_pc <= 32'h1bff_fffc; fs_pc <= 32'h1bff_fffc;
excp_adef <= 1'b0; excp_adef <= 1'b0;
csr_vec_h <= 32'b0;
end end
else if (flush) begin else if (flush) begin
pc_valid <= 1'b1; pc_valid <= 1'b1;
fs_pc <= new_pc; fs_pc <= new_pc;
excp_adef <= |new_pc[1:0]; excp_adef <= |new_pc[1:0];
csr_vec_h <= 32'b0;
end end
else if (!stall[0]) begin else if (!stall[0]) begin
pc_valid <= 1'b1; pc_valid <= 1'b1;
fs_pc <= next_pc; fs_pc <= next_pc;
excp_adef <= |next_pc[1:0]; excp_adef <= |next_pc[1:0];
csr_vec_h <= 0; // TODO!
end end
end end
assign seq_pc = fs_pc + 3'h4; assign seq_pc = fs_pc + 3'h4;
assign next_pc = br_taken ? br_target : seq_pc; assign next_pc = br_taken ? br_target : seq_pc;
// always @ (posedge clk) begin assign inst_sram_en = br_taken ? 1'b0 : pc_valid;
// if (reset) begin
// stallreq_fs_for_cache_r <= 1'b0;
// end
// else if (flush) begin
// stallreq_fs_for_cache_r <= 1'b0;
// end
// else if (!stall[0]) begin
// stallreq_fs_for_cache_r <= 1'b1;
// end
// else begin
// stallreq_fs_for_cache_r <= 1'b0;
// end
// end
// assign stallreq_fs_for_cache = stallreq_fs_for_cache_r & (!br_taken);
assign inst_sram_en = (/*flush |*/ br_taken) ? 1'b0 : pc_valid;
assign inst_sram_we = 4'h0; assign inst_sram_we = 4'h0;
assign inst_sram_addr = fs_pc; assign inst_sram_addr = fs_pc;
assign inst_sram_wdata = 32'b0; assign inst_sram_wdata = 32'b0;
endmodule
module if2_stage
#(
parameter FS_TO_DS_BUS_WD = 34
)
(
input clk ,
input reset,
input flush,
input [ 5:0] stall,
input br_taken,
input [FS_TO_DS_BUS_WD -1:0] fs1_to_fs2_bus,
output [FS_TO_DS_BUS_WD -1:0] fs2_to_ds_bus
);
reg [FS_TO_DS_BUS_WD -1:0] fs1_to_fs2_bus_r;
wire br_flush;
assign br_flush = br_taken;
assign fs2_to_ds_bus = fs1_to_fs2_bus_r;
always @ (posedge clk) begin
if (reset) begin
fs1_to_fs2_bus_r <= 0;
end
else if (flush | br_flush) begin
fs1_to_fs2_bus_r <= 0;
end
else if (stall[0] & !stall[1]) begin
fs1_to_fs2_bus_r <= 0;
end
else if (!stall[0]) begin
fs1_to_fs2_bus_r <= fs1_to_fs2_bus;
end
end
endmodule endmodule

139
lacpu/rtl/mycpu/mem_stage.v
View File

@@ -1,4 +1,56 @@
module mem_stage module mem1_stage
#(
parameter ES_TO_MS_BUS_WD = 271,
parameter MS_TO_ES_BUS_WD = 38
)
(
input clk,
input reset,
input flush,
input [ 5:0] stall,
input [ES_TO_MS_BUS_WD -1:0] es_to_ms1_bus,
output [ES_TO_MS_BUS_WD -1:0] ms1_to_ms2_bus,
output [MS_TO_ES_BUS_WD -1:0] ms1_to_es_bus
);
reg [ES_TO_MS_BUS_WD -1:0] es_to_ms1_bus_r;
wire reg_we;
wire [ 4:0] dest;
wire [31:0] es_result;
assign ms1_to_ms2_bus = es_to_ms1_bus_r;
assign reg_we = es_to_ms1_bus_r[133:133];
assign dest = es_to_ms1_bus_r[132:128];
assign es_result = es_to_ms1_bus_r[127:96];
assign ms1_to_es_bus = {reg_we,
dest,
es_result
};
always @(posedge clk) begin
if (reset) begin
es_to_ms1_bus_r <= 0;
end
else if (flush) begin
es_to_ms1_bus_r <= 0;
end
else if(stall[3] & (!stall[4])) begin
es_to_ms1_bus_r <= 0;
end
else if(!stall[3]) begin
es_to_ms1_bus_r <= es_to_ms1_bus;
end
end
endmodule
module mem2_stage
#( #(
parameter ES_TO_MS_BUS_WD = 271, parameter ES_TO_MS_BUS_WD = 271,
parameter MS_TO_ES_BUS_WD = 38, parameter MS_TO_ES_BUS_WD = 38,
@@ -20,16 +72,17 @@ module mem_stage
input [ 7:0] ext_int, input [ 7:0] ext_int,
input [ES_TO_MS_BUS_WD -1:0] es_to_ms_bus, input [ES_TO_MS_BUS_WD -1:0] ms1_to_ms2_bus,
output [MS_TO_ES_BUS_WD -1:0] ms_to_es_bus, output [MS_TO_ES_BUS_WD -1:0] ms_to_es_bus,
output [MS_TO_WS_BUS_WD -1:0] ms_to_ws_bus, output [MS_TO_WS_BUS_WD -1:0] ms2_to_ws_bus,
input [31:0] data_sram_rdata input [31:0] data_sram_rdata
); );
reg [ES_TO_MS_BUS_WD -1:0] es_to_ms_bus_r; reg [ES_TO_MS_BUS_WD -1:0] ms1_to_ms2_bus_r;
reg [31:0] data_sram_rdata_r; reg [31:0] data_sram_rdata_r;
reg [31:0] csr_rdata_r; reg [31:0] data_sram_rdata_buffer;
reg [31:0] csr_rdata_buffer;
reg stall_flag; reg stall_flag;
wire [63:0] csr_vec; wire [63:0] csr_vec;
@@ -77,63 +130,61 @@ module mem_stage
src1 ,//95 :64 src1 ,//95 :64
ms_pc ,//63 :32 ms_pc ,//63 :32
inst //31 :0 inst //31 :0
} = es_to_ms_bus_r; } = ms1_to_ms2_bus_r;
assign ms_to_es_bus = {reg_we, assign ms_to_es_bus = {reg_we,
dest, dest,
es_result ms_final_result//es_result
}; };
assign ms_to_ws_bus = {reg_we ,//101:101 assign ms2_to_ws_bus = {reg_we ,//101:101
dest ,//100:96 dest ,//100:96
ms_final_result ,//95 :64 ms_final_result ,//95 :64
ms_pc ,//63 :32 ms_pc ,//63 :32
inst //31 :0 inst //31 :0
}; };
always @ (posedge clk) begin always @(posedge clk) begin
if (reset) begin if (reset) begin
es_to_ms_bus_r <= 0; ms1_to_ms2_bus_r <= 0;
data_sram_rdata_r <= 0;
csr_rdata_buffer <= 0;
stall_flag <= 0;
end end
else if (flush) begin else if (flush) begin
es_to_ms_bus_r <= 0; ms1_to_ms2_bus_r <= 0;
end
else if (stall[3]&(!stall[4])) begin
es_to_ms_bus_r <= 0;
end
else if (!stall[3]) begin
es_to_ms_bus_r <= es_to_ms_bus;
end
end
always @ (posedge clk) begin
if (reset) begin
data_sram_rdata_r <= 0; data_sram_rdata_r <= 0;
csr_rdata_r <= 0; csr_rdata_buffer <= 0;
stall_flag <= 1'b0; stall_flag <= 0;
end end
else if (flush) begin else if (stall[3] & (!stall[4])) begin
ms1_to_ms2_bus_r <= 0;
data_sram_rdata_r <= 0; data_sram_rdata_r <= 0;
csr_rdata_r <= 0; csr_rdata_buffer <= 0;
stall_flag <= 1'b0; stall_flag <= 0;
end end
else if (!stall[3]) begin else if ((!stall[3]) & stall_flag) begin
ms1_to_ms2_bus_r <= ms1_to_ms2_bus;
data_sram_rdata_r <= data_sram_rdata_buffer;
csr_rdata_buffer <= 0;
stall_flag <= 0;
end
else if ((!stall[3]) & (!stall_flag)) begin
ms1_to_ms2_bus_r <= ms1_to_ms2_bus;
data_sram_rdata_r <= data_sram_rdata; data_sram_rdata_r <= data_sram_rdata;
csr_rdata_r <= csr_rdata; csr_rdata_buffer <= 0;
stall_flag <= 1'b0; stall_flag <= 0;
end end
else if (stall_flag) begin else if(!stall_flag) begin
data_sram_rdata_buffer <= data_sram_rdata;
end csr_rdata_buffer <= csr_rdata;
else if (stall[3]&stall[4])begin stall_flag <= 1'b1;
data_sram_rdata_r <= data_sram_rdata;
csr_rdata_r <= csr_rdata;
stall_flag <= 1'b1;
end end
end end
assign data_temp = stall_flag ? data_sram_rdata_r : data_sram_rdata; assign data_temp = data_sram_rdata_r;
assign csr_result = stall_flag ? csr_rdata_r : csr_rdata; assign csr_result = stall_flag ? csr_rdata_buffer : csr_rdata;
assign {inst_ld_b, assign {inst_ld_b,
inst_ld_h, inst_ld_h,

60
lacpu/rtl/mycpu/mul_div_lock.v
View File

@@ -8,58 +8,74 @@ module mul_div_lock (
input div_en, input div_en,
input stallreq_for_mul, input stallreq_for_mul,
input stallreq_for_div, input stallreq_for_div,
input sign_flag,
input rem_flag,
output [31:0] a_locked, output [31:0] a_locked,
output [31:0] b_locked, output [31:0] b_locked,
output mul_en_locked, output mul_en_locked,
output div_en_locked output div_en_locked,
output sign_flag_locked,
output rem_flag_locked
); );
reg first_enable; reg first_enable;
reg mul_en_musk; reg mul_en_musk;
reg div_en_musk; reg div_en_musk;
reg [31:0] a_buffer; reg [31:0] a_buffer;
reg [31:0] b_buffer; reg [31:0] b_buffer;
reg sign_flag_buffer;
reg rem_flag_buffer;
wire stallreq = stallreq_for_mul | stallreq_for_div; wire stallreq = stallreq_for_mul | stallreq_for_div;
assign mul_en_locked = mul_en & mul_en_musk; assign mul_en_locked = mul_en & mul_en_musk;
assign div_en_locked = div_en & div_en_musk; assign div_en_locked = div_en & div_en_musk;
assign a_locked = first_enable ? a : a_buffer; assign a_locked = first_enable ? a : a_buffer;
assign b_locked = first_enable ? b : b_buffer; assign b_locked = first_enable ? b : b_buffer;
assign sign_flag_locked = first_enable ? sign_flag : sign_flag_buffer;
assign rem_flag_locked = first_enable ? rem_flag : rem_flag_buffer;
always @ (posedge clk) begin always @ (posedge clk) begin
if (reset) begin if (reset) begin
a_buffer <= 0; a_buffer <= 0;
b_buffer <= 0; b_buffer <= 0;
mul_en_musk <= 1; sign_flag_buffer <= 0;
div_en_musk <= 1; rem_flag_buffer <= 0;
mul_en_musk <= 1;
div_en_musk <= 1;
first_enable <= 1; first_enable <= 1;
end end
else if (mul_en & first_enable) begin else if (mul_en & first_enable) begin
a_buffer <= a; a_buffer <= a;
b_buffer <= b; b_buffer <= b;
mul_en_musk <= 0; sign_flag_buffer <= sign_flag;
div_en_musk <= 1; rem_flag_buffer <= rem_flag;
mul_en_musk <= 0;
div_en_musk <= 1;
first_enable <= 0; first_enable <= 0;
end end
else if (div_en & first_enable) begin else if (div_en & first_enable) begin
a_buffer <= a; a_buffer <= a;
b_buffer <= b; b_buffer <= b;
mul_en_musk <= 1; sign_flag_buffer <= sign_flag;
div_en_musk <= 0; rem_flag_buffer <= rem_flag;
mul_en_musk <= 1;
div_en_musk <= 0;
first_enable <= 0; first_enable <= 0;
end end
else if (!stallreq & (mul_en|div_en) & !first_enable & !stall[2]) begin else if (!stallreq & (mul_en|div_en) & !first_enable & !stall[2]) begin
a_buffer <= 0; a_buffer <= 0;
b_buffer <= 0; b_buffer <= 0;
mul_en_musk <= 1; sign_flag_buffer <= 0;
div_en_musk <= 1; rem_flag_buffer <= 0;
mul_en_musk <= 1;
div_en_musk <= 1;
first_enable <= 1; first_enable <= 1;
end end
end end

14
lacpu/rtl/mycpu/mul_div_top.v
View File

@@ -29,6 +29,8 @@ module mul_div_top(
wire [31:0] b_locked; wire [31:0] b_locked;
wire mul_en_locked; wire mul_en_locked;
wire div_en_locked; wire div_en_locked;
wire sign_flag_locked;
wire rem_flag_locked;
assign mul_en = mul_div_op[0] | mul_div_op[1]; assign mul_en = mul_div_op[0] | mul_div_op[1];
assign div_en = mul_div_op[2] | mul_div_op[3]; assign div_en = mul_div_op[2] | mul_div_op[3];
@@ -43,12 +45,16 @@ module mul_div_top(
.stall (stall ), .stall (stall ),
.a (src_a ), .a (src_a ),
.b (src_b ), .b (src_b ),
.sign_flag (sign_flag ),
.rem_flag (a[31] ),
.mul_en (mul_en ), .mul_en (mul_en ),
.div_en (div_en ), .div_en (div_en ),
.stallreq_for_mul (stallreq_for_mul ), .stallreq_for_mul (stallreq_for_mul ),
.stallreq_for_div (stallreq_for_div ), .stallreq_for_div (stallreq_for_div ),
.a_locked (a_locked ), .a_locked (a_locked ),
.b_locked (b_locked ), .b_locked (b_locked ),
.sign_flag_locked (sign_flag_locked ),
.rem_flag_locked (rem_flag_locked ),
.mul_en_locked (mul_en_locked ), .mul_en_locked (mul_en_locked ),
.div_en_locked (div_en_locked ) .div_en_locked (div_en_locked )
); );
@@ -78,10 +84,10 @@ module mul_div_top(
); );
assign stallreq = stallreq_for_mul | stallreq_for_div; assign stallreq = stallreq_for_mul | stallreq_for_div;
assign mul_div_result = mul_div_op[0] ? (mul_div_sign & (a[31] ^ b[31]) & |result_l ) ? { ~result_l[31:0] + 1'b1} : result_l : assign mul_div_result = mul_div_op[0] ? (mul_div_sign & sign_flag_locked & |result_l ) ? { ~result_l[31:0] + 1'b1} : result_l :
mul_div_op[1] ? (mul_div_sign & (a[31] ^ b[31]) & |result_h ) ? {a[31] ^ b[31], ~result_h[30:0] } : result_h : mul_div_op[1] ? (mul_div_sign & sign_flag_locked & |result_h ) ? {sign_flag_locked, ~result_h[30:0] } : result_h :
mul_div_op[2] ? (mul_div_sign & (a[31] ^ b[31]) & |quotient ) ? {a[31] ^ b[31], ~quotient[30:0] + 1'b1} : quotient : mul_div_op[2] ? (mul_div_sign & sign_flag_locked & |quotient ) ? {sign_flag_locked, ~quotient[30:0] + 1'b1} : quotient :
mul_div_op[3] ? (mul_div_sign & a[31] & |remainder) ? {a[31] , ~remainder[30:0] + 1'b1} : remainder : mul_div_op[3] ? (mul_div_sign & rem_flag_locked & |remainder) ? {rem_flag_locked , ~remainder[30:0] + 1'b1} : remainder :
32'b0; 32'b0;
endmodule endmodule

98
lacpu/rtl/mycpu/mycpu_core.v
View File

@@ -2,7 +2,7 @@
module mycpu_core module mycpu_core
#( #(
parameter FS_TO_DS_BUS_WD = 65, parameter FS_TO_DS_BUS_WD = 34,
parameter DS_TO_ES_BUS_WD = 301, parameter DS_TO_ES_BUS_WD = 301,
parameter ES_TO_MS_BUS_WD = 271, parameter ES_TO_MS_BUS_WD = 271,
parameter MS_TO_WS_BUS_WD = 102, parameter MS_TO_WS_BUS_WD = 102,
@@ -42,22 +42,27 @@ module mycpu_core
); );
reg reset; reg reset;
reg br_taken_buffer;
reg [31:0] br_target_buffer;
always @(posedge clk) reset <= ~resetn; always @(posedge clk) reset <= ~resetn;
wire [FS_TO_DS_BUS_WD -1:0] fs_to_ds_bus; wire [FS_TO_DS_BUS_WD -1:0] fs1_to_fs2_bus;
wire [FS_TO_DS_BUS_WD -1:0] fs2_to_ds_bus;
wire [DS_TO_ES_BUS_WD -1:0] ds_to_es_bus; wire [DS_TO_ES_BUS_WD -1:0] ds_to_es_bus;
wire [ES_TO_MS_BUS_WD -1:0] es_to_ms_bus; wire [ES_TO_MS_BUS_WD -1:0] es_to_ms1_bus;
wire [MS_TO_WS_BUS_WD -1:0] ms_to_ws_bus; wire [ES_TO_MS_BUS_WD -1:0] ms1_to_ms2_bus;
wire [MS_TO_WS_BUS_WD -1:0] ms2_to_ws_bus;
wire [WS_TO_RF_BUS_WD -1:0] ws_to_rf_bus; wire [WS_TO_RF_BUS_WD -1:0] ws_to_rf_bus;
wire [MS_TO_ES_BUS_WD -1:0] ms1_to_es_bus;
wire [MS_TO_ES_BUS_WD -1:0] ms_to_es_bus; wire [MS_TO_ES_BUS_WD -1:0] ms_to_es_bus;
wire [WS_TO_ES_BUS_WD -1:0] ws_to_es_bus; wire [WS_TO_ES_BUS_WD -1:0] ws_to_es_bus;
wire [BR_BUS_WD -1:0] br_bus; wire [BR_BUS_WD -1:0] br_bus;
wire [BR_BUS_WD -1:0] br_bus_real;
wire flush; wire flush;
//wire stallreq_fs_for_cache;
//wire stallreq_es_for_cache;
wire stallreq_es; wire stallreq_es;
wire stallreq_ds; wire stallreq_ds;
wire [ 5:0] stall; wire [ 5:0] stall;
@@ -66,35 +71,68 @@ module mycpu_core
wire [ 1:0] csr_plv; wire [ 1:0] csr_plv;
wire csr_has_int; wire csr_has_int;
wire stallreq_cache; wire stallreq_cache;
wire br_taken;
wire [31:0] br_target;
assign stallreq_cache = stallreq_dcache | stallreq_icache | stallreq_uncache; assign stallreq_cache = stallreq_dcache | stallreq_icache | stallreq_uncache;
if_stage if_stage( always @ (posedge clk) begin
if (reset) begin
br_taken_buffer <= 1'b0;
br_target_buffer <= 32'b0;
end
else if (!stall[0]) begin
br_taken_buffer <= 1'b0;
br_target_buffer <= 32'b0;
end
else if (!br_taken_buffer) begin
br_taken_buffer <= br_bus[32];
br_target_buffer <= br_bus[31:0];
end
end
assign br_taken = br_bus[32] | br_taken_buffer;
assign br_target = br_bus[32] ? br_bus[31:0] :
br_taken_buffer ? br_target_buffer :
32'b0;
assign br_bus_real = {br_taken, br_target};
if1_stage if1_stage(
.clk (clk ), .clk (clk ),
.reset (reset ), .reset (reset ),
.flush (flush ), .flush (flush ),
.stall (stall ), .stall (stall ),
.new_pc (new_pc ), .new_pc (new_pc ),
//.stallreq_fs_for_cache (stallreq_fs_for_cache ), .fs1_to_fs2_bus (fs1_to_fs2_bus ),
.fs_to_ds_bus (fs_to_ds_bus ), .br_bus (br_bus_real ),
.br_bus (br_bus ),
.inst_sram_en (inst_sram_en ), .inst_sram_en (inst_sram_en ),
.inst_sram_we (inst_sram_we ), .inst_sram_we (inst_sram_we ),
.inst_sram_addr (inst_sram_addr ), .inst_sram_addr (inst_sram_addr ),
.inst_sram_wdata (inst_sram_wdata ) .inst_sram_wdata (inst_sram_wdata )
); );
if2_stage if2_stage(
.clk (clk ),
.reset (reset ),
.flush (flush ),
.stall (stall ),
.br_taken (br_taken ),
.fs1_to_fs2_bus (fs1_to_fs2_bus ),
.fs2_to_ds_bus (fs2_to_ds_bus )
);
id_stage id_stage( id_stage id_stage(
.clk (clk ), .clk (clk ),
.reset (reset ), .reset (reset ),
.flush (flush ), .flush (flush ),
.stall (stall ), .stall (stall ),
.br_taken (br_bus[32] ), .br_taken (br_taken ),
.stallreq_ds (stallreq_ds ), .stallreq_ds (stallreq_ds ),
.fs_to_ds_bus (fs_to_ds_bus ), .fs2_to_ds_bus (fs2_to_ds_bus ),
.pc_valid (inst_sram_en ),
.inst_sram_rdata (inst_sram_rdata ), .inst_sram_rdata (inst_sram_rdata ),
.csr_plv (csr_plv ), .csr_plv (csr_plv ),
.csr_has_int (csr_has_int ), .csr_has_int (csr_has_int ),
@@ -110,13 +148,14 @@ module mycpu_core
.stallreq_es (stallreq_es ), .stallreq_es (stallreq_es ),
.ds_to_es_bus (ds_to_es_bus ), .ds_to_es_bus (ds_to_es_bus ),
.es_to_ms_bus (es_to_ms_bus ), .es_to_ms1_bus (es_to_ms1_bus ),
.ms1_to_es_bus (ms1_to_es_bus ),
.ms_to_es_bus (ms_to_es_bus ), .ms_to_es_bus (ms_to_es_bus ),
.ws_to_es_bus (ws_to_es_bus ), .ws_to_es_bus (ws_to_es_bus ),
//.stallreq_es_for_cache (stallreq_es_for_cache),
.br_bus (br_bus ), .br_bus (br_bus ),
.br_taken_buffer (br_taken_buffer ),
.data_sram_en (data_sram_en ), .data_sram_en (data_sram_en ),
.data_sram_we (data_sram_we ), .data_sram_we (data_sram_we ),
@@ -124,7 +163,20 @@ module mycpu_core
.data_sram_wdata (data_sram_wdata ) .data_sram_wdata (data_sram_wdata )
); );
mem_stage mem_stage( mem1_stage mem1_stage(
.clk (clk ),
.reset (reset ),
.flush (flush ),
.stall (stall ),
.es_to_ms1_bus (es_to_ms1_bus ),
.ms1_to_ms2_bus (ms1_to_ms2_bus ),
.ms1_to_es_bus (ms1_to_es_bus )
);
mem2_stage mem2_stage(
.clk (clk ), .clk (clk ),
.reset (reset ), .reset (reset ),
.flush (flush ), .flush (flush ),
@@ -136,9 +188,9 @@ module mycpu_core
.stallreq_axi (stallreq_cache ), .stallreq_axi (stallreq_cache ),
.ext_int (ext_int ), .ext_int (ext_int ),
.es_to_ms_bus (es_to_ms_bus ), .ms1_to_ms2_bus (ms1_to_ms2_bus ),
.ms_to_es_bus (ms_to_es_bus ), .ms_to_es_bus (ms_to_es_bus ),
.ms_to_ws_bus (ms_to_ws_bus ), .ms2_to_ws_bus (ms2_to_ws_bus ),
.data_sram_rdata (data_sram_rdata ) .data_sram_rdata (data_sram_rdata )
); );
@@ -149,7 +201,7 @@ module mycpu_core
.flush (flush ), .flush (flush ),
.stall (stall ), .stall (stall ),
.ms_to_ws_bus (ms_to_ws_bus ), .ms2_to_ws_bus (ms2_to_ws_bus ),
.ws_to_rf_bus (ws_to_rf_bus ), .ws_to_rf_bus (ws_to_rf_bus ),
.ws_to_es_bus (ws_to_es_bus ), .ws_to_es_bus (ws_to_es_bus ),
@@ -162,11 +214,9 @@ module mycpu_core
pip_ctrl pip_ctrl( pip_ctrl pip_ctrl(
.reset (reset ), .reset (reset ),
.except_en (except_en ), .except_en (except_en ),
//.stallreq_fs_for_cache (stallreq_fs_for_cache ),
//.stallreq_es_for_cache (stallreq_es_for_cache ),
.stallreq_ds (stallreq_ds ), .stallreq_ds (stallreq_ds ),
.stallreq_es (stallreq_es ), .stallreq_es (stallreq_es ),
.stallreq_axi (stallreq_cache ), // TODO! .stallreq_axi (stallreq_cache ),
.stallreq_cache (stallreq_cache ), .stallreq_cache (stallreq_cache ),
.flush (flush ), .flush (flush ),
.stall (stall ) .stall (stall )

6
lacpu/rtl/mycpu/mycpu_top.v
View File

@@ -90,8 +90,8 @@ module mycpu_top
assign resetn = aresetn; assign resetn = aresetn;
// icache tag // icache tag
wire icache_cached; //wire icache_cached;
wire icache_uncached; //wire icache_uncached;
wire icache_refresh; wire icache_refresh;
wire icache_miss; wire icache_miss;
wire [31:0] icache_raddr; wire [31:0] icache_raddr;
@@ -204,7 +204,7 @@ module mycpu_top
.stallreq (stallreq_uncache ), .stallreq (stallreq_uncache ),
.conf_en (data_sram_en & ~dcache_cached ), .conf_en (data_sram_en & ~dcache_cached ),
.conf_we (data_sram_we ), .conf_we (data_sram_we ),
.conf_addr (data_sram_addr_mmu ), // _mmu ? .conf_addr (data_sram_addr_mmu ),
.conf_wdata (data_sram_wdata ), .conf_wdata (data_sram_wdata ),
.conf_rdata (uncache_temp_rdata ), .conf_rdata (uncache_temp_rdata ),
.axi_en (uncache_en ), .axi_en (uncache_en ),

15
lacpu/rtl/mycpu/pip_ctrl.v
View File

@@ -2,8 +2,8 @@
module pip_ctrl( module pip_ctrl(
input reset, input reset,
input except_en, input except_en,
input stallreq_fs_for_cache, //input stallreq_fs_for_cache,
input stallreq_es_for_cache, //input stallreq_es_for_cache,
input stallreq_ds, input stallreq_ds,
input stallreq_es, input stallreq_es,
input stallreq_axi, input stallreq_axi,
@@ -30,15 +30,16 @@ module pip_ctrl(
flush = 1; flush = 1;
stall = `StallBus'b0; stall = `StallBus'b0;
end end
//id段发生暂停，此时id及之前暂停
else if (stallreq_ds) begin
flush = 0;
stall = `StallBus'b000111;
end
else if (stallreq_es) begin else if (stallreq_es) begin
flush = 0; flush = 0;
stall = `StallBus'b111111; stall = `StallBus'b111111;
end end
//id段å<C2B5>‘生暂å<E2809A>œï¼Œæ­¤æ—¶idå<64>Šä¹‹å‰<C3A5>æš‚å<E2809A>?
else if (stallreq_ds) begin
flush = 0;
stall = `StallBus'b000111;
end
// else if(stallreq_fs_for_cache) begin // else if(stallreq_fs_for_cache) begin
// flush = 0; // flush = 0;
// stall = `StallBus'b000011; // stall = `StallBus'b000011;

14
lacpu/rtl/mycpu/wb_stage.v
View File

@@ -10,7 +10,7 @@ module wb_stage
input flush, input flush,
input [5:0] stall, input [5:0] stall,
input [MS_TO_WS_BUS_WD -1:0] ms_to_ws_bus, input [MS_TO_WS_BUS_WD -1:0] ms2_to_ws_bus,
output [WS_TO_RF_BUS_WD -1:0] ws_to_rf_bus, output [WS_TO_RF_BUS_WD -1:0] ws_to_rf_bus,
output [WS_TO_ES_BUS_WD -1:0] ws_to_es_bus, output [WS_TO_ES_BUS_WD -1:0] ws_to_es_bus,
@@ -19,7 +19,7 @@ module wb_stage
output [ 4:0] debug_wb_rf_wnum, output [ 4:0] debug_wb_rf_wnum,
output [31:0] debug_wb_rf_wdata output [31:0] debug_wb_rf_wdata
); );
reg [MS_TO_WS_BUS_WD -1:0] ms_to_ws_bus_r; reg [MS_TO_WS_BUS_WD -1:0] ms2_to_ws_bus_r;
wire reg_we; wire reg_we;
wire [ 4:0] dest; wire [ 4:0] dest;
@@ -32,7 +32,7 @@ module wb_stage
ms_final_result ,//95 :64 ms_final_result ,//95 :64
ws_pc ,//63 :32 ws_pc ,//63 :32
inst //31 :0 inst //31 :0
} = ms_to_ws_bus_r; } = ms2_to_ws_bus_r;
assign ws_to_rf_bus = {reg_we, assign ws_to_rf_bus = {reg_we,
dest, dest,
@@ -46,16 +46,16 @@ module wb_stage
always @ (posedge clk) begin always @ (posedge clk) begin
if (reset) begin if (reset) begin
ms_to_ws_bus_r <= 0; ms2_to_ws_bus_r <= 0;
end end
else if (flush) begin else if (flush) begin
ms_to_ws_bus_r <= 0; ms2_to_ws_bus_r <= 0;
end end
else if (stall[4]&(!stall[5])) begin else if (stall[4]&(!stall[5])) begin
ms_to_ws_bus_r <= 0; ms2_to_ws_bus_r <= 0;
end end
else if (!stall[4]) begin else if (!stall[4]) begin
ms_to_ws_bus_r <= ms_to_ws_bus; ms2_to_ws_bus_r <= ms2_to_ws_bus;
end end
end end

44
lacpu/rtl/xilinx_ip/clk_pll/clk_pll.xci
View File

@@ -98,17 +98,17 @@
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKIN2_JITTER_PS">100.0</spirit:configurableElementValue> <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKIN2_JITTER_PS">100.0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT0_1">0000</spirit:configurableElementValue> <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT0_1">0000</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT0_2">0000</spirit:configurableElementValue> <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT0_2">0000</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT0_ACTUAL_FREQ">100.00000</spirit:configurableElementValue> <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT0_ACTUAL_FREQ">65.00000</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT1_1">0000</spirit:configurableElementValue> <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT1_1">0000</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT1_2">0000</spirit:configurableElementValue> <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT1_2">0000</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT1_ACTUAL_FREQ">100.00000</spirit:configurableElementValue> <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT1_ACTUAL_FREQ">100.00000</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT1_DRIVES">BUFG</spirit:configurableElementValue> <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT1_DRIVES">BUFG</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT1_DUTY_CYCLE">50.0</spirit:configurableElementValue> <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT1_DUTY_CYCLE">50.0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT1_MATCHED_ROUTING">false</spirit:configurableElementValue> <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT1_MATCHED_ROUTING">false</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT1_OUT_FREQ">100.00000</spirit:configurableElementValue> <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT1_OUT_FREQ">65.00000</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT1_PHASE">0.000</spirit:configurableElementValue> <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT1_PHASE">0.000</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT1_REQUESTED_DUTY_CYCLE">50.000</spirit:configurableElementValue> <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT1_REQUESTED_DUTY_CYCLE">50.000</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT1_REQUESTED_OUT_FREQ">100.000</spirit:configurableElementValue> <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT1_REQUESTED_OUT_FREQ">65.000</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT1_REQUESTED_PHASE">0.000</spirit:configurableElementValue> <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT1_REQUESTED_PHASE">0.000</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT1_SEQUENCE_NUMBER">1</spirit:configurableElementValue> <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT1_SEQUENCE_NUMBER">1</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT2_1">0000</spirit:configurableElementValue> <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_CLKOUT2_1">0000</spirit:configurableElementValue>
@@ -203,12 +203,12 @@
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_DIN_PORT">din</spirit:configurableElementValue> <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_DIN_PORT">din</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_DIVCLK">0000</spirit:configurableElementValue> <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_DIVCLK">0000</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_DIVIDE1_AUTO">1</spirit:configurableElementValue> <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_DIVIDE1_AUTO">1</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_DIVIDE2_AUTO">1.0</spirit:configurableElementValue> <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_DIVIDE2_AUTO">0.65</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_DIVIDE3_AUTO">1.0</spirit:configurableElementValue> <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_DIVIDE3_AUTO">0.65</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_DIVIDE4_AUTO">1.0</spirit:configurableElementValue> <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_DIVIDE4_AUTO">0.65</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_DIVIDE5_AUTO">1.0</spirit:configurableElementValue> <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_DIVIDE5_AUTO">0.65</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_DIVIDE6_AUTO">1.0</spirit:configurableElementValue> <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_DIVIDE6_AUTO">0.65</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_DIVIDE7_AUTO">1.0</spirit:configurableElementValue> <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_DIVIDE7_AUTO">0.65</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_DOUT_PORT">dout</spirit:configurableElementValue> <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_DOUT_PORT">dout</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_DRDY_PORT">drdy</spirit:configurableElementValue> <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_DRDY_PORT">drdy</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_DWE_PORT">dwe</spirit:configurableElementValue> <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_DWE_PORT">dwe</spirit:configurableElementValue>
@@ -246,16 +246,16 @@
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCMBUFGCEDIV6">false</spirit:configurableElementValue> <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCMBUFGCEDIV6">false</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCMBUFGCEDIV7">false</spirit:configurableElementValue> <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCMBUFGCEDIV7">false</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_BANDWIDTH">OPTIMIZED</spirit:configurableElementValue> <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_BANDWIDTH">OPTIMIZED</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_CLKFBOUT_MULT_F">9.000</spirit:configurableElementValue> <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_CLKFBOUT_MULT_F">13.000</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_CLKFBOUT_PHASE">0.000</spirit:configurableElementValue> <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_CLKFBOUT_PHASE">0.000</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_CLKFBOUT_USE_FINE_PS">FALSE</spirit:configurableElementValue> <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_CLKFBOUT_USE_FINE_PS">FALSE</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_CLKIN1_PERIOD">10.000</spirit:configurableElementValue> <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_CLKIN1_PERIOD">10.000</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_CLKIN2_PERIOD">10.000</spirit:configurableElementValue> <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_CLKIN2_PERIOD">10.000</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_CLKOUT0_DIVIDE_F">9.000</spirit:configurableElementValue> <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_CLKOUT0_DIVIDE_F">20.000</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_CLKOUT0_DUTY_CYCLE">0.500</spirit:configurableElementValue> <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_CLKOUT0_DUTY_CYCLE">0.500</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_CLKOUT0_PHASE">0.000</spirit:configurableElementValue> <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_CLKOUT0_PHASE">0.000</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_CLKOUT0_USE_FINE_PS">FALSE</spirit:configurableElementValue> <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_CLKOUT0_USE_FINE_PS">FALSE</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_CLKOUT1_DIVIDE">9</spirit:configurableElementValue> <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_CLKOUT1_DIVIDE">13</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_CLKOUT1_DUTY_CYCLE">0.500</spirit:configurableElementValue> <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_CLKOUT1_DUTY_CYCLE">0.500</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_CLKOUT1_PHASE">0.000</spirit:configurableElementValue> <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_CLKOUT1_PHASE">0.000</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_CLKOUT1_USE_FINE_PS">FALSE</spirit:configurableElementValue> <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_MMCM_CLKOUT1_USE_FINE_PS">FALSE</spirit:configurableElementValue>
@@ -292,8 +292,8 @@
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_NUM_OUT_CLKS">2</spirit:configurableElementValue> <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_NUM_OUT_CLKS">2</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_OUTCLK_SUM_ROW0A"> Output Output Phase Duty Cycle Pk-to-Pk Phase</spirit:configurableElementValue> <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_OUTCLK_SUM_ROW0A"> Output Output Phase Duty Cycle Pk-to-Pk Phase</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_OUTCLK_SUM_ROW0B"> Clock Freq (MHz) (degrees) (%) Jitter (ps) Error (ps)</spirit:configurableElementValue> <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_OUTCLK_SUM_ROW0B"> Clock Freq (MHz) (degrees) (%) Jitter (ps) Error (ps)</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_OUTCLK_SUM_ROW1">_cpu_clk__100.00000______0.000______50.0______137.681____105.461</spirit:configurableElementValue> <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_OUTCLK_SUM_ROW1">_cpu_clk__65.00000______0.000______50.0______118.571_____82.897</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_OUTCLK_SUM_ROW2">timer_clk__100.00000______0.000______50.0______137.681____105.461</spirit:configurableElementValue> <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_OUTCLK_SUM_ROW2">timer_clk__100.00000______0.000______50.0______109.471_____82.897</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_OUTCLK_SUM_ROW3">no_CLK_OUT3_output</spirit:configurableElementValue> <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_OUTCLK_SUM_ROW3">no_CLK_OUT3_output</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_OUTCLK_SUM_ROW4">no_CLK_OUT4_output</spirit:configurableElementValue> <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_OUTCLK_SUM_ROW4">no_CLK_OUT4_output</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_OUTCLK_SUM_ROW5">no_CLK_OUT5_output</spirit:configurableElementValue> <spirit:configurableElementValue spirit:referenceId="MODELPARAM_VALUE.C_OUTCLK_SUM_ROW5">no_CLK_OUT5_output</spirit:configurableElementValue>
@@ -414,18 +414,18 @@
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKIN2_JITTER_PS">100.0</spirit:configurableElementValue> <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKIN2_JITTER_PS">100.0</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKIN2_UI_JITTER">0.010</spirit:configurableElementValue> <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKIN2_UI_JITTER">0.010</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT1_DRIVES">BUFG</spirit:configurableElementValue> <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT1_DRIVES">BUFG</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT1_JITTER">137.681</spirit:configurableElementValue> <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT1_JITTER">118.571</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT1_MATCHED_ROUTING">false</spirit:configurableElementValue> <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT1_MATCHED_ROUTING">false</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT1_PHASE_ERROR">105.461</spirit:configurableElementValue> <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT1_PHASE_ERROR">82.897</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT1_REQUESTED_DUTY_CYCLE">50.000</spirit:configurableElementValue> <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT1_REQUESTED_DUTY_CYCLE">50.000</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT1_REQUESTED_OUT_FREQ">100.000</spirit:configurableElementValue> <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT1_REQUESTED_OUT_FREQ">65.000</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT1_REQUESTED_PHASE">0.000</spirit:configurableElementValue> <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT1_REQUESTED_PHASE">0.000</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT1_SEQUENCE_NUMBER">1</spirit:configurableElementValue> <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT1_SEQUENCE_NUMBER">1</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT1_USED">true</spirit:configurableElementValue> <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT1_USED">true</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT2_DRIVES">BUFG</spirit:configurableElementValue> <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT2_DRIVES">BUFG</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT2_JITTER">137.681</spirit:configurableElementValue> <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT2_JITTER">109.471</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT2_MATCHED_ROUTING">false</spirit:configurableElementValue> <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT2_MATCHED_ROUTING">false</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT2_PHASE_ERROR">105.461</spirit:configurableElementValue> <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT2_PHASE_ERROR">82.897</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT2_REQUESTED_DUTY_CYCLE">50.000</spirit:configurableElementValue> <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT2_REQUESTED_DUTY_CYCLE">50.000</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT2_REQUESTED_OUT_FREQ">100.000</spirit:configurableElementValue> <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT2_REQUESTED_OUT_FREQ">100.000</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT2_REQUESTED_PHASE">0.000</spirit:configurableElementValue> <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.CLKOUT2_REQUESTED_PHASE">0.000</spirit:configurableElementValue>
@@ -525,16 +525,16 @@
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.JITTER_SEL">No_Jitter</spirit:configurableElementValue> <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.JITTER_SEL">No_Jitter</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.LOCKED_PORT">locked</spirit:configurableElementValue> <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.LOCKED_PORT">locked</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_BANDWIDTH">OPTIMIZED</spirit:configurableElementValue> <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_BANDWIDTH">OPTIMIZED</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKFBOUT_MULT_F">9</spirit:configurableElementValue> <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKFBOUT_MULT_F">13</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKFBOUT_PHASE">0.000</spirit:configurableElementValue> <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKFBOUT_PHASE">0.000</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKFBOUT_USE_FINE_PS">false</spirit:configurableElementValue> <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKFBOUT_USE_FINE_PS">false</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKIN1_PERIOD">10.000</spirit:configurableElementValue> <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKIN1_PERIOD">10.000</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKIN2_PERIOD">10.000</spirit:configurableElementValue> <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKIN2_PERIOD">10.000</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKOUT0_DIVIDE_F">9</spirit:configurableElementValue> <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKOUT0_DIVIDE_F">20</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKOUT0_DUTY_CYCLE">0.500</spirit:configurableElementValue> <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKOUT0_DUTY_CYCLE">0.500</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKOUT0_PHASE">0.000</spirit:configurableElementValue> <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKOUT0_PHASE">0.000</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKOUT0_USE_FINE_PS">false</spirit:configurableElementValue> <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKOUT0_USE_FINE_PS">false</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKOUT1_DIVIDE">9</spirit:configurableElementValue> <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKOUT1_DIVIDE">13</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKOUT1_DUTY_CYCLE">0.500</spirit:configurableElementValue> <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKOUT1_DUTY_CYCLE">0.500</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKOUT1_PHASE">0.000</spirit:configurableElementValue> <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKOUT1_PHASE">0.000</spirit:configurableElementValue>
<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKOUT1_USE_FINE_PS">false</spirit:configurableElementValue> <spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.MMCM_CLKOUT1_USE_FINE_PS">false</spirit:configurableElementValue>

27
lacpu/run_vivado/la32r/la32r.xpr
View File

@@ -36,13 +36,13 @@
<Option Name="WTVcsLaunchSim" Val="0"/> <Option Name="WTVcsLaunchSim" Val="0"/>
<Option Name="WTRivieraLaunchSim" Val="0"/> <Option Name="WTRivieraLaunchSim" Val="0"/>
<Option Name="WTActivehdlLaunchSim" Val="0"/> <Option Name="WTActivehdlLaunchSim" Val="0"/>
<Option Name="WTXSimExportSim" Val="23"/> <Option Name="WTXSimExportSim" Val="24"/>
<Option Name="WTModelSimExportSim" Val="23"/> <Option Name="WTModelSimExportSim" Val="24"/>
<Option Name="WTQuestaExportSim" Val="23"/> <Option Name="WTQuestaExportSim" Val="24"/>
<Option Name="WTIesExportSim" Val="23"/> <Option Name="WTIesExportSim" Val="24"/>
<Option Name="WTVcsExportSim" Val="23"/> <Option Name="WTVcsExportSim" Val="24"/>
<Option Name="WTRivieraExportSim" Val="23"/> <Option Name="WTRivieraExportSim" Val="24"/>
<Option Name="WTActivehdlExportSim" Val="23"/> <Option Name="WTActivehdlExportSim" Val="24"/>
<Option Name="GenerateIPUpgradeLog" Val="TRUE"/> <Option Name="GenerateIPUpgradeLog" Val="TRUE"/>
<Option Name="XSimRadix" Val="hex"/> <Option Name="XSimRadix" Val="hex"/>
<Option Name="XSimTimeUnit" Val="ns"/> <Option Name="XSimTimeUnit" Val="ns"/>
@@ -391,11 +391,10 @@
<Runs Version="1" Minor="11"> <Runs Version="1" Minor="11">
<Run Id="synth_1" Type="Ft3:Synth" SrcSet="sources_1" Part="xc7a200tfbg676-1" ConstrsSet="constrs_1" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" State="current" Dir="$PRUNDIR/synth_1" IncludeInArchive="true"> <Run Id="synth_1" Type="Ft3:Synth" SrcSet="sources_1" Part="xc7a200tfbg676-1" ConstrsSet="constrs_1" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" State="current" Dir="$PRUNDIR/synth_1" IncludeInArchive="true">
<Strategy Version="1" Minor="2"> <Strategy Version="1" Minor="2">
<StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2019"/> <StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2019">
<Step Id="synth_design"> <Desc>Vivado Synthesis Defaults</Desc>
<Option Id="FlattenHierarchy">1</Option> </StratHandle>
<Option Id="KeepEquivalentRegisters">1</Option> <Step Id="synth_design"/>
</Step>
</Strategy> </Strategy>
<GeneratedRun Dir="$PRUNDIR" File="gen_run.xml"/> <GeneratedRun Dir="$PRUNDIR" File="gen_run.xml"/>
<ReportStrategy Name="Vivado Synthesis Default Reports" Flow="Vivado Synthesis 2019"/> <ReportStrategy Name="Vivado Synthesis Default Reports" Flow="Vivado Synthesis 2019"/>
@@ -444,7 +443,9 @@
</Run> </Run>
<Run Id="impl_1" Type="Ft2:EntireDesign" Part="xc7a200tfbg676-1" ConstrsSet="constrs_1" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" State="current" Dir="$PRUNDIR/impl_1" SynthRun="synth_1" IncludeInArchive="true" GenFullBitstream="true"> <Run Id="impl_1" Type="Ft2:EntireDesign" Part="xc7a200tfbg676-1" ConstrsSet="constrs_1" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" State="current" Dir="$PRUNDIR/impl_1" SynthRun="synth_1" IncludeInArchive="true" GenFullBitstream="true">
<Strategy Version="1" Minor="2"> <Strategy Version="1" Minor="2">
<StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2019"/> <StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2019">
<Desc>Default settings for Implementation.</Desc>
</StratHandle>
<Step Id="init_design"/> <Step Id="init_design"/>
<Step Id="opt_design"/> <Step Id="opt_design"/>
<Step Id="power_opt_design"/> <Step Id="power_opt_design"/>