UnbalancedCat/neulacpu
1
0
Fork 0
Code Issues Pull Requests Actions Packages Projects Releases Wiki Activity

[Add] switch to 7-stage and pass func test

Browse Source
This commit is contained in:
包焕垲
2023-07-28 15:29:06 +08:00
parent bf2dd4655b
commit 3a070d35fc
12 changed files with 431 additions and 305 deletions
Download Patch File Download Diff File Expand all files Collapse all files

98
lacpu/rtl/mycpu/mycpu_core.v
View File

@@ -2,7 +2,7 @@
module mycpu_core
#(
parameter FS_TO_DS_BUS_WD = 65,
parameter FS_TO_DS_BUS_WD = 34,
parameter DS_TO_ES_BUS_WD = 301,
parameter ES_TO_MS_BUS_WD = 271,
parameter MS_TO_WS_BUS_WD = 102,
@@ -42,22 +42,27 @@ module mycpu_core
);
reg reset;
reg br_taken_buffer;
reg [31:0] br_target_buffer;
always @(posedge clk) reset <= ~resetn;
wire [FS_TO_DS_BUS_WD -1:0] fs_to_ds_bus;
wire [FS_TO_DS_BUS_WD -1:0] fs1_to_fs2_bus;
wire [FS_TO_DS_BUS_WD -1:0] fs2_to_ds_bus;
wire [DS_TO_ES_BUS_WD -1:0] ds_to_es_bus;
wire [ES_TO_MS_BUS_WD -1:0] es_to_ms_bus;
wire [MS_TO_WS_BUS_WD -1:0] ms_to_ws_bus;
wire [ES_TO_MS_BUS_WD -1:0] es_to_ms1_bus;
wire [ES_TO_MS_BUS_WD -1:0] ms1_to_ms2_bus;
wire [MS_TO_WS_BUS_WD -1:0] ms2_to_ws_bus;
wire [WS_TO_RF_BUS_WD -1:0] ws_to_rf_bus;
wire [MS_TO_ES_BUS_WD -1:0] ms1_to_es_bus;
wire [MS_TO_ES_BUS_WD -1:0] ms_to_es_bus;
wire [WS_TO_ES_BUS_WD -1:0] ws_to_es_bus;
wire [BR_BUS_WD -1:0] br_bus;
wire [BR_BUS_WD -1:0] br_bus_real;
wire flush;
//wire stallreq_fs_for_cache;
//wire stallreq_es_for_cache;
wire stallreq_es;
wire stallreq_ds;
wire [ 5:0] stall;
@@ -66,35 +71,68 @@ module mycpu_core
wire [ 1:0] csr_plv;
wire csr_has_int;
wire stallreq_cache;
wire br_taken;
wire [31:0] br_target;
assign stallreq_cache = stallreq_dcache | stallreq_icache | stallreq_uncache;
if_stage if_stage(
always @ (posedge clk) begin
if (reset) begin
br_taken_buffer <= 1'b0;
br_target_buffer <= 32'b0;
end
else if (!stall[0]) begin
br_taken_buffer <= 1'b0;
br_target_buffer <= 32'b0;
end
else if (!br_taken_buffer) begin
br_taken_buffer <= br_bus[32];
br_target_buffer <= br_bus[31:0];
end
end
assign br_taken = br_bus[32] | br_taken_buffer;
assign br_target = br_bus[32] ? br_bus[31:0] :
br_taken_buffer ? br_target_buffer :
32'b0;
assign br_bus_real = {br_taken, br_target};
if1_stage if1_stage(
.clk (clk ),
.reset (reset ),
.flush (flush ),
.stall (stall ),
.new_pc (new_pc ),
//.stallreq_fs_for_cache (stallreq_fs_for_cache ),
.fs_to_ds_bus (fs_to_ds_bus ),
.br_bus (br_bus ),
.fs1_to_fs2_bus (fs1_to_fs2_bus ),
.br_bus (br_bus_real ),
.inst_sram_en (inst_sram_en ),
.inst_sram_we (inst_sram_we ),
.inst_sram_addr (inst_sram_addr ),
.inst_sram_wdata (inst_sram_wdata )
);
if2_stage if2_stage(
.clk (clk ),
.reset (reset ),
.flush (flush ),
.stall (stall ),
.br_taken (br_taken ),
.fs1_to_fs2_bus (fs1_to_fs2_bus ),
.fs2_to_ds_bus (fs2_to_ds_bus )
);
id_stage id_stage(
.clk (clk ),
.reset (reset ),
.flush (flush ),
.stall (stall ),
.br_taken (br_bus[32] ),
.br_taken (br_taken ),
.stallreq_ds (stallreq_ds ),
.fs_to_ds_bus (fs_to_ds_bus ),
.pc_valid (inst_sram_en ),
.fs2_to_ds_bus (fs2_to_ds_bus ),
.inst_sram_rdata (inst_sram_rdata ),
.csr_plv (csr_plv ),
.csr_has_int (csr_has_int ),
@@ -110,13 +148,14 @@ module mycpu_core
.stallreq_es (stallreq_es ),
.ds_to_es_bus (ds_to_es_bus ),
.es_to_ms_bus (es_to_ms_bus ),
.es_to_ms1_bus (es_to_ms1_bus ),
.ms1_to_es_bus (ms1_to_es_bus ),
.ms_to_es_bus (ms_to_es_bus ),
.ws_to_es_bus (ws_to_es_bus ),
//.stallreq_es_for_cache (stallreq_es_for_cache),
.br_bus (br_bus ),
.br_taken_buffer (br_taken_buffer ),
.data_sram_en (data_sram_en ),
.data_sram_we (data_sram_we ),
@@ -124,7 +163,20 @@ module mycpu_core
.data_sram_wdata (data_sram_wdata )
);
mem_stage mem_stage(
mem1_stage mem1_stage(
.clk (clk ),
.reset (reset ),
.flush (flush ),
.stall (stall ),
.es_to_ms1_bus (es_to_ms1_bus ),
.ms1_to_ms2_bus (ms1_to_ms2_bus ),
.ms1_to_es_bus (ms1_to_es_bus )
);
mem2_stage mem2_stage(
.clk (clk ),
.reset (reset ),
.flush (flush ),
@@ -136,9 +188,9 @@ module mycpu_core
.stallreq_axi (stallreq_cache ),
.ext_int (ext_int ),
.es_to_ms_bus (es_to_ms_bus ),
.ms1_to_ms2_bus (ms1_to_ms2_bus ),
.ms_to_es_bus (ms_to_es_bus ),
.ms_to_ws_bus (ms_to_ws_bus ),
.ms2_to_ws_bus (ms2_to_ws_bus ),
.data_sram_rdata (data_sram_rdata )
);
@@ -149,7 +201,7 @@ module mycpu_core
.flush (flush ),
.stall (stall ),
.ms_to_ws_bus (ms_to_ws_bus ),
.ms2_to_ws_bus (ms2_to_ws_bus ),
.ws_to_rf_bus (ws_to_rf_bus ),
.ws_to_es_bus (ws_to_es_bus ),
@@ -162,11 +214,9 @@ module mycpu_core
pip_ctrl pip_ctrl(
.reset (reset ),
.except_en (except_en ),
//.stallreq_fs_for_cache (stallreq_fs_for_cache ),
//.stallreq_es_for_cache (stallreq_es_for_cache ),
.stallreq_ds (stallreq_ds ),
.stallreq_es (stallreq_es ),
.stallreq_axi (stallreq_cache ), // TODO!
.stallreq_axi (stallreq_cache ),
.stallreq_cache (stallreq_cache ),
.flush (flush ),
.stall (stall )