diff --git a/lacpu/rtl/cpu/cpu_top.v b/lacpu/rtl/cpu/cpu_top.v
index 1feeb3d..abb3db6 100755
--- a/lacpu/rtl/cpu/cpu_top.v
+++ b/lacpu/rtl/cpu/cpu_top.v
@@ -1,4 +1,4 @@
-`include "mycpu.v"
+`include "mycpu.vh"
 
 module mycpu_top(
     input         clk,
diff --git a/lacpu/rtl/cpu/div.v b/lacpu/rtl/cpu/div.v
new file mode 100644
index 0000000..e69de29
diff --git a/lacpu/rtl/cpu/exe_stage.v b/lacpu/rtl/cpu/exe_stage.v
index 2be0b12..48630df 100755
--- a/lacpu/rtl/cpu/exe_stage.v
+++ b/lacpu/rtl/cpu/exe_stage.v
@@ -1,4 +1,4 @@
-`include "mycpu.v"
+`include "mycpu.vh"
 
 module exe_stage(
     input                          clk           ,
diff --git a/lacpu/rtl/cpu/forward.v b/lacpu/rtl/cpu/forward.v
index 07d0429..afef503 100644
--- a/lacpu/rtl/cpu/forward.v
+++ b/lacpu/rtl/cpu/forward.v
@@ -1,4 +1,4 @@
-`include "mycpu.v"
+`include "mycpu.vh"
 
 module forward(
     input                       clk         ,
diff --git a/lacpu/rtl/cpu/id_stage.v b/lacpu/rtl/cpu/id_stage.v
index 9dfa501..ec82cb7 100755
--- a/lacpu/rtl/cpu/id_stage.v
+++ b/lacpu/rtl/cpu/id_stage.v
@@ -1,4 +1,4 @@
-`include "mycpu.v"
+`include "mycpu.vh"
 
 // 译码阶段
 module id_stage(
diff --git a/lacpu/rtl/cpu/if_stage.v b/lacpu/rtl/cpu/if_stage.v
index a985ee3..9cdf127 100755
--- a/lacpu/rtl/cpu/if_stage.v
+++ b/lacpu/rtl/cpu/if_stage.v
@@ -1,4 +1,4 @@
-`include "mycpu.v"
+`include "mycpu.vh"
 
 // 取指阶段
 module if_stage(
diff --git a/lacpu/rtl/cpu/loaduse.v b/lacpu/rtl/cpu/loaduse.v
index 164e832..197da7f 100644
--- a/lacpu/rtl/cpu/loaduse.v
+++ b/lacpu/rtl/cpu/loaduse.v
@@ -1,4 +1,4 @@
-`include "mycpu.v"
+`include "mycpu.vh"
 
 module loaduse(  
     input  [`DS_TO_LU_BUS_WD -1:0] ds_to_lu_bus,
diff --git a/lacpu/rtl/cpu/mem_stage.v b/lacpu/rtl/cpu/mem_stage.v
index 4989ddf..479b872 100755
--- a/lacpu/rtl/cpu/mem_stage.v
+++ b/lacpu/rtl/cpu/mem_stage.v
@@ -1,4 +1,4 @@
-`include "mycpu.v"
+`include "mycpu.vh"
 
 module mem_stage(
     input                          clk            ,
diff --git a/lacpu/rtl/cpu/mycpu.v b/lacpu/rtl/cpu/mycpu.vh
similarity index 100%
rename from lacpu/rtl/cpu/mycpu.v
rename to lacpu/rtl/cpu/mycpu.vh
diff --git a/lacpu/rtl/cpu/wb_stage.v b/lacpu/rtl/cpu/wb_stage.v
index 86d018c..9e33022 100755
--- a/lacpu/rtl/cpu/wb_stage.v
+++ b/lacpu/rtl/cpu/wb_stage.v
@@ -1,4 +1,4 @@
-`include "mycpu.v"
+`include "mycpu.vh"
 
 module wb_stage(
     input                           clk           ,