[Add] add ext_int

lacpu/rtl/mycpu/csr.v

@@ -16,6 +16,9 @@ module csr(
     input  [13:0] csr_addr,
     input         csr_wdata_sel,
     input  [31:0] csr_wdata,
+
+    input  [ 7:0] ext_int,
+
     output [31:0] csr_rdata,
 
     output        except_en,
@@ -324,7 +327,7 @@ module csr(
                 estat[11] <= 1'b1;
                 timer_en  <= tcfg[`PERIODIC];
             end
-            //estat[9:0] <= intrpt; // ???
+            estat[9:2] <= ext_int; // TODO?
             
             // tval
             if(timer_en) begin

lacpu/rtl/mycpu/if_stage.v

@@ -12,8 +12,6 @@ module if_stage
 
     input  [31:0] new_pc,
 
-    input         timer_int,
-
     output        inst_sram_en   ,
     output [ 3:0] inst_sram_we   ,
     output [31:0] inst_sram_addr ,
@@ -61,7 +59,7 @@ module if_stage
             pc_valid  <= 1'b1;
             fs_pc     <= next_pc;
             excp_adef <= |next_pc[1:0];
-            csr_vec_h <= 0; // timer_int; TODO!
+            csr_vec_h <= 0; // TODO!
         end
     end
 

lacpu/rtl/mycpu/mem_stage.v

@@ -18,6 +18,8 @@ module mem_stage
 
     input         stallreq_axi,
 
+    input  [ 7:0] ext_int,
+
     input  [ES_TO_MS_BUS_WD -1:0] es_to_ms_bus,
     output [MS_TO_ES_BUS_WD -1:0] ms_to_es_bus,
     output [MS_TO_WS_BUS_WD -1:0] ms_to_ws_bus,
@@ -186,7 +188,8 @@ module mem_stage
         .csr_rdata      (csr_rdata         ),
         .except_en      (except_en         ),
         .new_pc         (new_pc            ),
-        .stallreq_axi   (stallreq_axi      )
+        .stallreq_axi   (stallreq_axi      ),
+        .ext_int        (ext_int           )
     );
     
     assign ms_final_result = (|load_op)  ? ms_result  :

lacpu/rtl/mycpu/mycpu_core.v

@@ -16,7 +16,7 @@ module mycpu_core
 (
     input         clk,
     input         resetn,
-    output        timer_int,
+    input  [ 7:0] ext_int,
 
     // inst sram interface
     output        inst_sram_en,
@@ -75,7 +75,6 @@ module mycpu_core
         .flush           (flush           ),
         .stall           (stall           ),
         .new_pc          (new_pc          ),
-        .timer_int       (timer_int       ),
         .fs_to_ds_bus    (fs_to_ds_bus    ),
         .br_bus          (br_bus          ),
         .inst_sram_en    (inst_sram_en    ),
@@ -130,6 +129,7 @@ module mycpu_core
         .csr_plv         (csr_plv         ),
         .csr_has_int     (csr_has_int     ),
         .stallreq_axi    (stallreq_cache  ),
+        .ext_int         (ext_int         ),
 
         .es_to_ms_bus    (es_to_ms_bus    ),
         .ms_to_es_bus    (ms_to_es_bus    ),

lacpu/rtl/mycpu/mycpu_top.v

@@ -9,7 +9,7 @@ module mycpu_top
 (
     input         aclk,
     input         aresetn,
-    output        timer_int,
+    input  [ 7:0] ext_int,
 
     output [ 3:0] arid,
     output [31:0] araddr,
@@ -135,6 +135,7 @@ module mycpu_top
     mycpu_core mycpu_core(
         .clk                (clk                ),
         .resetn             (resetn             ),
+        .ext_int            (ext_int            ),
 
         .inst_sram_en       (inst_sram_en       ),
         .inst_sram_we       (inst_sram_we       ),

lacpu/run_vivado/la32r/la32r.xpr

@@ -391,9 +391,7 @@
   <Runs Version="1" Minor="11">
     <Run Id="synth_1" Type="Ft3:Synth" SrcSet="sources_1" Part="xc7a200tfbg676-1" ConstrsSet="constrs_1" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" State="current" Dir="$PRUNDIR/synth_1" IncludeInArchive="true">
       <Strategy Version="1" Minor="2">
-        <StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2019">
+        <StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2019"/>
-          <Desc>Vivado Synthesis Defaults</Desc>
-        </StratHandle>
         <Step Id="synth_design">
           <Option Id="FlattenHierarchy">1</Option>
           <Option Id="KeepEquivalentRegisters">1</Option>
@@ -436,9 +434,7 @@
     </Run>
     <Run Id="clk_pll_synth_1" Type="Ft3:Synth" SrcSet="clk_pll" Part="xc7a200tfbg676-1" ConstrsSet="clk_pll" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" Dir="$PRUNDIR/clk_pll_synth_1" IncludeInArchive="true">
       <Strategy Version="1" Minor="2">
-        <StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2019">
+        <StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2019"/>
-          <Desc>Vivado Synthesis Defaults</Desc>
-        </StratHandle>
         <Step Id="synth_design"/>
       </Strategy>
       <GeneratedRun Dir="$PRUNDIR" File="gen_run.xml"/>
@@ -448,9 +444,7 @@
     </Run>
     <Run Id="impl_1" Type="Ft2:EntireDesign" Part="xc7a200tfbg676-1" ConstrsSet="constrs_1" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" State="current" Dir="$PRUNDIR/impl_1" SynthRun="synth_1" IncludeInArchive="true" GenFullBitstream="true">
       <Strategy Version="1" Minor="2">
-        <StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2019">
+        <StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2019"/>
-          <Desc>Default settings for Implementation.</Desc>
-        </StratHandle>
         <Step Id="init_design"/>
         <Step Id="opt_design"/>
         <Step Id="power_opt_design"/>
@@ -519,9 +513,7 @@
     </Run>
     <Run Id="clk_pll_impl_1" Type="Ft2:EntireDesign" Part="xc7a200tfbg676-1" ConstrsSet="clk_pll" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" SynthRun="clk_pll_synth_1" IncludeInArchive="false" GenFullBitstream="true">
       <Strategy Version="1" Minor="2">
-        <StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2019">
+        <StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2019"/>
-          <Desc>Default settings for Implementation.</Desc>
-        </StratHandle>
         <Step Id="init_design"/>
         <Step Id="opt_design"/>
         <Step Id="power_opt_design"/>