[Add] add icache dcache axi & pass test n46(before syscall)
This commit is contained in:
@@ -1,33 +1,69 @@
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`default_nettype wire
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module mycpu_top
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#(
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parameter FS_TO_DS_BUS_WD = 65,
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parameter DS_TO_ES_BUS_WD = 301,
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parameter ES_TO_MS_BUS_WD = 271,
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parameter MS_TO_WS_BUS_WD = 102,
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parameter WS_TO_RF_BUS_WD = 38,
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parameter MS_TO_ES_BUS_WD = 38,
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parameter WS_TO_ES_BUS_WD = 38,
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parameter BR_BUS_WD = 33
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parameter HIT_WD = 2,
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parameter LRU_WD = 1,
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parameter CACHELINE_WD = 512
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)
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(
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input clk,
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input resetn,
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input aclk,
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input aresetn,
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output timer_int,
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// inst sram interface
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output inst_sram_en,
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output [ 3:0] inst_sram_we,
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output [31:0] inst_sram_addr,
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output [31:0] inst_sram_wdata,
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input [31:0] inst_sram_rdata,
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// data sram interface
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output data_sram_en,
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output [ 3:0] data_sram_we,
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output [31:0] data_sram_addr,
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output [31:0] data_sram_wdata,
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input [31:0] data_sram_rdata,
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output [ 3:0] arid,
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output [31:0] araddr,
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output [ 3:0] arlen,
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output [ 2:0] arsize,
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output [ 1:0] arburst,
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output [ 1:0] arlock,
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output [ 3:0] arcache,
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output [ 2:0] arprot,
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output arvalid,
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input arready,
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input [ 3:0] rid,
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input [31:0] rdata,
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input [ 1:0] rresp,
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input rlast,
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input rvalid,
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output rready,
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output [ 3:0] awid,
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output [31:0] awaddr,
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output [ 3:0] awlen,
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output [ 2:0] awsize,
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output [ 1:0] awburst,
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output [ 1:0] awlock,
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output [ 3:0] awcache,
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output [ 2:0] awprot,
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output awvalid,
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input awready,
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output [ 3:0] wid,
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output [31:0] wdata,
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output [ 3:0] wstrb,
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output wlast,
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output wvalid,
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input wready,
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input [ 3:0] bid,
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input [ 1:0] bresp,
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input bvalid,
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output bready,
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// // inst sram interface
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// output inst_sram_en,
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// output [ 3:0] inst_sram_we,
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// output [31:0] inst_sram_addr,
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// output [31:0] inst_sram_wdata,
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// input [31:0] inst_sram_rdata,
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// // data sram interface
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// output data_sram_en,
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// output [ 3:0] data_sram_we,
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// output [31:0] data_sram_addr,
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// output [31:0] data_sram_wdata,
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// input [31:0] data_sram_rdata,
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// trace debug interface
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output [31:0] debug_wb_pc,
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output [ 3:0] debug_wb_rf_we,
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@@ -35,122 +71,239 @@ module mycpu_top
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output [31:0] debug_wb_rf_wdata
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);
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reg reset;
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always @(posedge clk) reset <= ~resetn;
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wire inst_sram_en;
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wire [ 3:0] inst_sram_we;
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wire [31:0] inst_sram_addr;
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wire [31:0] inst_sram_wdata;
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wire [31:0] inst_sram_rdata;
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wire [FS_TO_DS_BUS_WD -1:0] fs_to_ds_bus;
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wire [DS_TO_ES_BUS_WD -1:0] ds_to_es_bus;
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wire [ES_TO_MS_BUS_WD -1:0] es_to_ms_bus;
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wire [MS_TO_WS_BUS_WD -1:0] ms_to_ws_bus;
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wire [WS_TO_RF_BUS_WD -1:0] ws_to_rf_bus;
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wire data_sram_en;
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wire [ 3:0] data_sram_we;
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wire [31:0] data_sram_addr;
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wire [31:0] data_sram_wdata;
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wire [31:0] data_sram_rdata;
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wire [MS_TO_ES_BUS_WD -1:0] ms_to_es_bus;
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wire [WS_TO_ES_BUS_WD -1:0] ws_to_es_bus;
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wire clk;
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wire resetn;
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wire [BR_BUS_WD -1:0] br_bus;
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assign clk = aclk;
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assign resetn = aresetn;
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wire flush;
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wire stallreq_es;
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wire stallreq_ds;
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wire [ 5:0] stall;
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wire except_en;
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wire [31:0] new_pc;
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// icache tag
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wire icache_cached;
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wire icache_uncached;
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wire icache_refresh;
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wire icache_miss;
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wire [31:0] icache_raddr;
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//wire icache_write_back;
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wire [31:0] icache_waddr;
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// icache data
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wire [CACHELINE_WD -1:0] icache_cacheline_new;
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wire [CACHELINE_WD -1:0] icache_cacheline_old;
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wire [ 1:0] csr_plv;
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wire csr_has_int;
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if_stage if_stage(
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.clk (clk ),
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.reset (reset ),
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.flush (flush ),
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.stall (stall ),
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.new_pc (new_pc ),
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.timer_int (timer_int ),
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.fs_to_ds_bus (fs_to_ds_bus ),
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.br_bus (br_bus ),
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.inst_sram_en (inst_sram_en ),
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.inst_sram_we (inst_sram_we ),
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.inst_sram_addr (inst_sram_addr ),
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.inst_sram_wdata (inst_sram_wdata )
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// dcache tag
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wire dcache_cached;
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wire dcache_uncached;
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wire dcache_refresh;
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wire dcache_miss;
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wire [31:0] dcache_raddr;
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wire dcache_write_back;
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wire [31:0] dcache_waddr;
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// dcache data
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wire [CACHELINE_WD -1:0] dcache_cacheline_new;
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wire [CACHELINE_WD -1:0] dcache_cacheline_old;
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// uncache tag
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wire uncache_refresh;
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wire uncache_en;
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wire [ 3:0] uncache_we;
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wire [31:0] uncache_addr;
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wire [31:0] uncache_wdata;
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// uncache data
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wire [31:0] uncache_rdata;
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wire [31:0] data_sram_addr_mmu;
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wire [31:0] dcache_temp_rdata;
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wire [31:0] uncache_temp_rdata;
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wire stallreq_icache;
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wire stallreq_dcache;
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wire stallreq_uncache;
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mycpu_core mycpu_core(
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.clk (clk ),
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.resetn (resetn ),
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.inst_sram_en (inst_sram_en ),
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.inst_sram_we (inst_sram_we ),
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.inst_sram_addr (inst_sram_addr ),
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.inst_sram_wdata (inst_sram_wdata ),
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.inst_sram_rdata (inst_sram_rdata ),
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.data_sram_en (data_sram_en ),
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.data_sram_we (data_sram_we ),
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.data_sram_addr (data_sram_addr ),
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.data_sram_wdata (data_sram_wdata ),
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.data_sram_rdata (data_sram_rdata ),
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.stallreq_dcache (stallreq_dcache ),
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.stallreq_icache (stallreq_icache ),
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.stallreq_uncache (stallreq_uncache ),
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.debug_wb_pc (debug_wb_pc ),
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.debug_wb_rf_we (debug_wb_rf_we ),
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.debug_wb_rf_wnum (debug_wb_rf_wnum ),
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.debug_wb_rf_wdata (debug_wb_rf_wdata )
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);
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id_stage id_stage(
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.clk (clk ),
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.reset (reset ),
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.flush (flush ),
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.stall (stall ),
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.br_taken (br_bus[32] ),
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.stallreq_ds (stallreq_ds ),
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.fs_to_ds_bus (fs_to_ds_bus ),
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.pc_valid (inst_sram_en ),
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.inst_sram_rdata (inst_sram_rdata ),
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.csr_plv (csr_plv ),
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.csr_has_int (csr_has_int ),
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.ws_to_rf_bus (ws_to_rf_bus ),
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.ds_to_es_bus (ds_to_es_bus )
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icache icache(
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.clk (clk ),
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.reset (~resetn ),
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.inst_sram_en (inst_sram_en ),
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.inst_sram_we (inst_sram_we ),
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.inst_sram_addr (inst_sram_addr ),
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.inst_sram_wdata (inst_sram_wdata ),
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.icache_refresh (icache_refresh ),
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.icache_cacheline_new (icache_cacheline_new),
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.stallreq_icache (stallreq_icache ),
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.inst_sram_rdata (inst_sram_rdata ),
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.icache_miss (icache_miss ),
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.icache_raddr (icache_raddr ),
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.icache_waddr (icache_waddr ),
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.icache_cacheline_old (icache_cacheline_old)
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);
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exe_stage exe_stage(
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.clk (clk ),
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.reset (reset ),
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.flush (flush ),
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.stall (stall ),
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.stallreq_es (stallreq_es ),
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.ds_to_es_bus (ds_to_es_bus ),
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.es_to_ms_bus (es_to_ms_bus ),
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.ms_to_es_bus (ms_to_es_bus ),
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.ws_to_es_bus (ws_to_es_bus ),
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.br_bus (br_bus ),
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.data_sram_en (data_sram_en ),
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.data_sram_we (data_sram_we ),
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.data_sram_addr (data_sram_addr ),
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.data_sram_wdata (data_sram_wdata )
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dcache dcache(
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.clk (clk ),
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.reset (~resetn ),
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.data_sram_en (data_sram_en ),
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.data_sram_we (data_sram_we ),
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.data_sram_addr (data_sram_addr_mmu ),
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.data_sram_wdata (data_sram_wdata ),
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.dcache_refresh (dcache_refresh ),
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.dcache_uncached (dcache_uncached ),
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.dcache_cacheline_new (dcache_cacheline_new),
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.stallreq_dcache (stallreq_dcache ),
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.data_sram_rdata (dcache_temp_rdata ),
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.dcache_miss (dcache_miss ),
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.dcache_raddr (dcache_raddr ),
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.dcache_waddr (dcache_waddr ),
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.dcache_write_back (dcache_write_back ),
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.dcache_cacheline_old (dcache_cacheline_old)
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);
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mem_stage mem_stage(
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.clk (clk ),
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.reset (reset ),
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.flush (flush ),
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.stall (stall ),
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.except_en (except_en ),
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.new_pc (new_pc ),
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.csr_plv (csr_plv ),
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.csr_has_int (csr_has_int ),
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.es_to_ms_bus (es_to_ms_bus ),
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.ms_to_es_bus (ms_to_es_bus ),
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.ms_to_ws_bus (ms_to_ws_bus ),
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.data_sram_rdata (data_sram_rdata )
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uncache uncache(
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.clk (clk ),
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.resetn (resetn ),
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.stallreq (stallreq_uncache ),
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.conf_en (data_sram_en & ~dcache_cached ),
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.conf_we (data_sram_we ),
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.conf_addr (data_sram_addr_mmu ), // _mmu ?
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.conf_wdata (data_sram_wdata ),
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.conf_rdata (uncache_temp_rdata ),
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.axi_en (uncache_en ),
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.axi_wsel (uncache_we ),
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.axi_addr (uncache_addr ),
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.axi_wdata (uncache_wdata ),
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.reload (uncache_refresh ),
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.axi_rdata (uncache_rdata )
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);
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wb_stage wb_stage(
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.clk (clk ),
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.reset (reset ),
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.flush (flush ),
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.stall (stall ),
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reg dcache_cached_r;
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//assign dcache_cached = ~dcache_uncached;
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assign dcache_uncached = ~dcache_cached;
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always @ (posedge clk) begin
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dcache_cached_r <= dcache_cached;
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end
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assign data_sram_rdata = dcache_cached_r ? dcache_temp_rdata : uncache_temp_rdata;
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.ms_to_ws_bus (ms_to_ws_bus ),
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.ws_to_rf_bus (ws_to_rf_bus ),
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.ws_to_es_bus (ws_to_es_bus ),
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.debug_wb_pc (debug_wb_pc ),
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.debug_wb_rf_we (debug_wb_rf_we ),
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.debug_wb_rf_wnum (debug_wb_rf_wnum ),
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.debug_wb_rf_wdata (debug_wb_rf_wdata)
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// mmu u_inst_mmu(
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// .addr_i (inst_sram_addr ),
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// .addr_o (inst_sram_addr_mmu ),
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// .cache_v (icache_cached )
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// );
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mmu data_mmu(
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.addr_i (data_sram_addr ),
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.addr_o (data_sram_addr_mmu ),
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.cache_v (dcache_cached )
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);
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pip_ctrl pip_ctrl(
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.reset (reset ),
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.except_en (except_en ),
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.stallreq_ds (stallreq_ds ),
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.stallreq_es (stallreq_es ),
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.stallreq_axi (1'b0 ), // TODO!
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.flush (flush ),
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.stall (stall )
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// cache signal from tlb
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// begin
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//assign dcache_uncached = 1'b0;
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// end
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axi_ctrl_v5 axi_ctrl(
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.clk (clk ),
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.reset (~resetn ),
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.icache_re (icache_miss ),
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.icache_raddr (icache_raddr ),
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.icache_cacheline_new (icache_cacheline_new ),
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.icache_we (1'b0 ),
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.icache_waddr (icache_waddr ),
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.icache_cacheline_old (icache_cacheline_old ),
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.icache_refresh (icache_refresh ),
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.dcache_re (dcache_miss ),
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.dcache_raddr (dcache_raddr ),
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.dcache_cacheline_new (dcache_cacheline_new ),
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.dcache_we (dcache_write_back ),
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.dcache_waddr (dcache_waddr ),
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.dcache_cacheline_old (dcache_cacheline_old ),
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.dcache_refresh (dcache_refresh ),
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.uncache_en (uncache_en ),
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.uncache_we (uncache_we ),
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.uncache_addr (uncache_addr ),
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.uncache_wdata (uncache_wdata ),
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.uncache_rdata (uncache_rdata ),
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.uncache_refresh (uncache_refresh ),
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.arid (arid ),
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.araddr (araddr ),
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.arlen (arlen ),
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.arsize (arsize ),
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.arburst (arburst ),
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.arlock (arlock ),
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.arcache (arcache ),
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.arprot (arprot ),
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.arvalid (arvalid ),
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.arready (arready ),
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.rid (rid ),
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.rdata (rdata ),
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.rresp (rresp ),
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.rlast (rlast ),
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.rvalid (rvalid ),
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.rready (rready ),
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.awid (awid ),
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.awaddr (awaddr ),
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.awlen (awlen ),
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.awsize (awsize ),
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.awburst (awburst ),
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.awlock (awlock ),
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.awcache (awcache ),
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.awprot (awprot ),
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.awvalid (awvalid ),
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.awready (awready ),
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.wid (wid ),
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.wdata (wdata ),
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.wstrb (wstrb ),
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.wlast (wlast ),
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.wvalid (wvalid ),
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.wready (wready ),
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.bid (bid ),
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.bresp (bresp ),
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.bvalid (bvalid ),
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.bready (bready )
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);
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endmodule
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