UnbalancedCat/neulacpu
1
0
Fork 0
Code Issues Pull Requests Actions Packages Projects Releases Wiki Activity

[Add] add op_mu.wl, op_mulh.w[u]

Browse Source
This commit is contained in:
包焕垲
2023-05-23 12:09:45 +08:00
parent bf41b61af0
commit 115d0492da
4 changed files with 54 additions and 27 deletions
Download Patch File Download Diff File Expand all files Collapse all files

64
lacpu/rtl/cpu/alu.v
View File

@@ -1,5 +1,5 @@
module alu(
input [11:0] alu_op ,
input [14:0] alu_op ,
input [31:0] alu_src1 ,
input [31:0] alu_src2 ,
output [31:0] alu_result ,
@@ -22,20 +22,26 @@ module alu(
wire op_sll;
wire op_srl;
wire op_sra;
wire op_mul;
wire op_mulh;
wire op_mulhu;
assign op_add = alu_op[ 0];
assign op_sub = alu_op[ 1];
assign op_slt = alu_op[ 2];
assign op_sltu = alu_op[ 3];
assign op_and = alu_op[ 4];
assign op_nor = alu_op[ 5];
assign op_or = alu_op[ 6];
assign op_xor = alu_op[ 7];
assign op_sll = alu_op[ 8];
assign op_srl = alu_op[ 9];
assign op_sra = alu_op[10];
assign op_lui = alu_op[11];
assign op_add = alu_op[ 0];
assign op_sub = alu_op[ 1];
assign op_slt = alu_op[ 2];
assign op_sltu = alu_op[ 3];
assign op_and = alu_op[ 4];
assign op_nor = alu_op[ 5];
assign op_or = alu_op[ 6];
assign op_xor = alu_op[ 7];
assign op_sll = alu_op[ 8];
assign op_srl = alu_op[ 9];
assign op_sra = alu_op[10];
assign op_lui = alu_op[11];
assign op_mul = alu_op[12];
assign op_mulh = alu_op[13];
assign op_mulhu = alu_op[14];
wire [31:0] add_sub_result;
wire [31:0] slt_result;
@@ -48,6 +54,9 @@ module alu(
wire [31:0] sll_result;
wire [63:0] sr64_result;
wire [31:0] sr_result;
wire [63:0] mul64_result;
wire [63:0] mulu64_result;
wire [31:0] mul_result;
// 32-bit adder
wire [31:0] adder_a;
@@ -88,17 +97,26 @@ module alu(
assign sr_result = sr64_result[31:0];
// MUL MULH result
assign mul64_result = $signed(alu_src1) * $signed(alu_src2);
assign mulu64_result = alu_src1 * alu_src2;
assign mul_result = op_mul ? mul64_result[31: 0] :
op_mulh ? mul64_result[63:32] :
/*op_mulhu*/ mulu64_result[63:32];
// final result mux
assign alu_result = ({32{op_add|op_sub}} & add_sub_result)
| ({32{op_slt }} & slt_result)
| ({32{op_sltu }} & sltu_result)
| ({32{op_and }} & and_result)
| ({32{op_nor }} & nor_result)
| ({32{op_or }} & or_result)
| ({32{op_xor }} & xor_result)
| ({32{op_lui }} & lui_result)
| ({32{op_sll }} & sll_result)
| ({32{op_srl|op_sra}} & sr_result);
assign alu_result = ({32{op_add|op_sub }} & add_sub_result)
| ({32{op_slt }} & slt_result)
| ({32{op_sltu }} & sltu_result)
| ({32{op_and }} & and_result)
| ({32{op_nor }} & nor_result)
| ({32{op_or }} & or_result)
| ({32{op_xor }} & xor_result)
| ({32{op_lui }} & lui_result)
| ({32{op_sll }} & sll_result)
| ({32{op_srl|op_sra }} & sr_result)
| ({32{op_mul|op_mulh|op_mulhu}} & mul_result);
assign Carry = op_sub ^ adder_cout;
assign Sign = alu_result[31];
assign Overflow = (op_add|op_sub) ? ( adder_a[31] & adder_b[31] & adder_cout)