From 104518d87582a1bc65036029b75162f902f75bfa Mon Sep 17 00:00:00 2001 From: bLueriVerLHR Date: Thu, 20 Jul 2023 18:43:45 +0800 Subject: [PATCH] [Update] chg rv to la --- lasoft/xv6-la/kernel/csr.h | 36 +++++++ lasoft/xv6-la/kernel/elf.h | 2 + lasoft/xv6-la/kernel/entry.S | 16 +-- lasoft/xv6-la/kernel/kernelvec.S | 178 +++++++++++++++---------------- 4 files changed, 135 insertions(+), 97 deletions(-) create mode 100644 lasoft/xv6-la/kernel/csr.h diff --git a/lasoft/xv6-la/kernel/csr.h b/lasoft/xv6-la/kernel/csr.h new file mode 100644 index 0000000..1a5fac0 --- /dev/null +++ b/lasoft/xv6-la/kernel/csr.h @@ -0,0 +1,36 @@ +#ifndef CSR_H__ +#define CSR_H__ + +// CSR infos +#define CRMD 0x000 /* 当前模式信息 */ +#define PRMD 0x001 /* 例外前模式信息 */ +#define EUEN 0x002 /* 拓展部件使能 */ +#define ECFG 0x004 /* 例外配置 */ +#define ESTAT 0x005 /* 例外状态 */ +#define ERA 0x006 /* 例外返回地址 */ +#define BADV 0x007 /* 出错虚地址 */ +#define EENTRY 0x00c /* 例外地址入口 */ +#define TLBIDX 0x010 /* TLB 索引 */ +#define TLBEHI 0x011 /* TLB 表项高位 */ +#define TLBELO0 0x012 /* TLB 表项低位 0 */ +#define TLBELO1 0x013 /* TLB 表项低位 1 */ +#define ASID 0x018 /* 地址空间标识符 */ +#define PGDL 0x019 /* 低半地址空间全局目录基址 */ +#define PGDH 0x01a /* 高半地址空间全局目录基址 */ +#define PGD 0x01b /* 全局目录基址 */ +#define CPUID 0x020 /* 处理器编号 */ +#define SAVE0 0x030 /* 数据保存 0*/ +#define SAVE1 0x031 /* 数据保存 1*/ +#define SAVE2 0x032 /* 数据保存 2 */ +#define SAVE3 0x033 /* 数据保存 3 */ +#define TID 0x040 /* 定时器编号 */ +#define TCFG 0x041 /* 定时器配置 */ +#define TVAL 0x042 /* 定时器值 */ +#define TICLR 0x044 /* 定时中断清除 */ +#define LLBCTL 0x060 /* LLBit 控制 */ +#define TLBRENTRY 0x088 /* TLB 重填例外入口 */ +#define CTAG 0x098 /* 高速缓存标签 */ +#define DMW0 0x180 /* 直接映射配置窗口 0 */ +#define DMW1 0x181 /* 直接映射配置窗口 1 */ + +#endif \ No newline at end of file diff --git a/lasoft/xv6-la/kernel/elf.h b/lasoft/xv6-la/kernel/elf.h index 84555fa..f616b9e 100644 --- a/lasoft/xv6-la/kernel/elf.h +++ b/lasoft/xv6-la/kernel/elf.h @@ -1,3 +1,5 @@ +#include "types.h" + // Format of an ELF executable file #define ELF_MAGIC 0x464C457FU // "\x7FELF" in little endian diff --git a/lasoft/xv6-la/kernel/entry.S b/lasoft/xv6-la/kernel/entry.S index 5ab365e..a8433b8 100644 --- a/lasoft/xv6-la/kernel/entry.S +++ b/lasoft/xv6-la/kernel/entry.S @@ -9,13 +9,13 @@ _entry: # stack0 is declared in start.c, # with a 4096-byte stack per CPU. # sp = stack0 + (hartid * 4096) - la sp, stack0 - li a0, 1024*4 - csrr a1, mhartid - addi a1, a1, 1 - mul a0, a0, a1 - add sp, sp, a0 + la.global $sp, stack0 + li.w $a0, 1024*4 + csrrd $a1, CPUID + addi.w $a1, $a1, 1 + mul.w $a0, $a0, $a1 + add.w $sp, $sp, $a0 # jump to start() in start.c - call start + bl start spin: - j spin + b spin diff --git a/lasoft/xv6-la/kernel/kernelvec.S b/lasoft/xv6-la/kernel/kernelvec.S index fb31b32..a7d29c8 100644 --- a/lasoft/xv6-la/kernel/kernelvec.S +++ b/lasoft/xv6-la/kernel/kernelvec.S @@ -11,81 +11,81 @@ .align 4 kernelvec: # make room to save registers. - addi sp, sp, -256 + addi.w $sp, $sp, -128 # save the registers. - sd ra, 0(sp) - sd sp, 8(sp) - sd gp, 16(sp) - sd tp, 24(sp) - sd t0, 32(sp) - sd t1, 40(sp) - sd t2, 48(sp) - sd s0, 56(sp) - sd s1, 64(sp) - sd a0, 72(sp) - sd a1, 80(sp) - sd a2, 88(sp) - sd a3, 96(sp) - sd a4, 104(sp) - sd a5, 112(sp) - sd a6, 120(sp) - sd a7, 128(sp) - sd s2, 136(sp) - sd s3, 144(sp) - sd s4, 152(sp) - sd s5, 160(sp) - sd s6, 168(sp) - sd s7, 176(sp) - sd s8, 184(sp) - sd s9, 192(sp) - sd s10, 200(sp) - sd s11, 208(sp) - sd t3, 216(sp) - sd t4, 224(sp) - sd t5, 232(sp) - sd t6, 240(sp) + st.w $ra, $sp, 0 + st.w $tp, $sp, 4 + st.w $sp, $sp, 8 + st.w $a0, $sp, 12 + st.w $a1, $sp, 16 + st.w $a2, $sp, 20 + st.w $a3, $sp, 24 + st.w $a4, $sp, 28 + st.w $a5, $sp, 32 + st.w $a6, $sp, 36 + st.w $a7, $sp, 40 + st.w $t0, $sp, 44 + st.w $t1, $sp, 48 + st.w $t2, $sp, 52 + st.w $t3, $sp, 56 + st.w $t4, $sp, 60 + st.w $t5, $sp, 64 + st.w $t6, $sp, 68 + st.w $t7, $sp, 72 + st.w $t8, $sp, 76 + st.w $u0, $sp, 80 + st.w $fp, $sp, 84 + st.w $s0, $sp, 88 + st.w $s1, $sp, 92 + st.w $s2, $sp, 96 + st.w $s3, $sp, 100 + st.w $s4, $sp, 104 + st.w $s5, $sp, 108 + st.w $s6, $sp, 112 + st.w $s7, $sp, 116 + st.w $s8, $sp, 120 # call the C trap handler in trap.c - call kerneltrap + bl kerneltrap # restore registers. - ld ra, 0(sp) - ld sp, 8(sp) - ld gp, 16(sp) + ld.w $ra, $sp, 0 # not tp (contains hartid), in case we moved CPUs - ld t0, 32(sp) - ld t1, 40(sp) - ld t2, 48(sp) - ld s0, 56(sp) - ld s1, 64(sp) - ld a0, 72(sp) - ld a1, 80(sp) - ld a2, 88(sp) - ld a3, 96(sp) - ld a4, 104(sp) - ld a5, 112(sp) - ld a6, 120(sp) - ld a7, 128(sp) - ld s2, 136(sp) - ld s3, 144(sp) - ld s4, 152(sp) - ld s5, 160(sp) - ld s6, 168(sp) - ld s7, 176(sp) - ld s8, 184(sp) - ld s9, 192(sp) - ld s10, 200(sp) - ld s11, 208(sp) - ld t3, 216(sp) - ld t4, 224(sp) - ld t5, 232(sp) - ld t6, 240(sp) + ld.w $sp, $sp, 8 + ld.w $a0, $sp, 12 + ld.w $a1, $sp, 16 + ld.w $a2, $sp, 20 + ld.w $a3, $sp, 24 + ld.w $a4, $sp, 28 + ld.w $a5, $sp, 32 + ld.w $a6, $sp, 36 + ld.w $a7, $sp, 40 + ld.w $t0, $sp, 44 + ld.w $t1, $sp, 48 + ld.w $t2, $sp, 52 + ld.w $t3, $sp, 56 + ld.w $t4, $sp, 60 + ld.w $t5, $sp, 64 + ld.w $t6, $sp, 68 + ld.w $t7, $sp, 72 + ld.w $t8, $sp, 76 + ld.w $u0, $sp, 80 + ld.w $fp, $sp, 84 + ld.w $s0, $sp, 88 + ld.w $s1, $sp, 92 + ld.w $s2, $sp, 96 + ld.w $s3, $sp, 100 + ld.w $s4, $sp, 104 + ld.w $s5, $sp, 108 + ld.w $s6, $sp, 112 + ld.w $s7, $sp, 116 + ld.w $s8, $sp, 120 - addi sp, sp, 256 + addi sp, sp, 128 # return to whatever we were doing in the kernel. - sret + ertn # # machine-mode timer interrupt. @@ -93,32 +93,32 @@ kernelvec: .globl timervec .align 4 timervec: - # start.c has set up the memory that mscratch points to: - # scratch[0,8,16] : register save area. - # scratch[24] : address of CLINT's MTIMECMP register. - # scratch[32] : desired interval between interrupts. + # # start.c has set up the memory that mscratch points to: + # # scratch[0,8,16] : register save area. + # # scratch[24] : address of CLINT's MTIMECMP register. + # # scratch[32] : desired interval between interrupts. - csrrw a0, mscratch, a0 - sd a1, 0(a0) - sd a2, 8(a0) - sd a3, 16(a0) + # csrrw a0, mscratch, a0 + # sd a1, 0(a0) + # sd a2, 8(a0) + # sd a3, 16(a0) - # schedule the next timer interrupt - # by adding interval to mtimecmp. - ld a1, 24(a0) # CLINT_MTIMECMP(hart) - ld a2, 32(a0) # interval - ld a3, 0(a1) - add a3, a3, a2 - sd a3, 0(a1) + # # schedule the next timer interrupt + # # by adding interval to mtimecmp. + # ld a1, 24(a0) # CLINT_MTIMECMP(hart) + # ld a2, 32(a0) # interval + # ld a3, 0(a1) + # add a3, a3, a2 + # sd a3, 0(a1) - # arrange for a supervisor software interrupt - # after this handler returns. - li a1, 2 - csrw sip, a1 + # # arrange for a supervisor software interrupt + # # after this handler returns. + # li a1, 2 + # csrw sip, a1 - ld a3, 16(a0) - ld a2, 8(a0) - ld a1, 0(a0) - csrrw a0, mscratch, a0 + # ld a3, 16(a0) + # ld a2, 8(a0) + # ld a1, 0(a0) + # csrrw a0, mscratch, a0 - mret + ertn