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[Modified] fix bug & pass pref test on board

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包焕垲
2023-07-24 02:46:27 +08:00
parent 27ef99503d
commit 0352651836
2 changed files with 1 additions and 1 deletions
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lacpu/doc/mycpu性能计算.xlsx Normal file
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lacpu/rtl/mycpu/pip_ctrl.v
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@@ -35,7 +35,7 @@ module pip_ctrl(
end end
else if (stallreq_es) begin else if (stallreq_es) begin
flush = 0; flush = 0;
stall = `StallBus'b011111; stall = `StallBus'b111111;
end end
// else if(stallreq_cache) begin // else if(stallreq_cache) begin
// flush = 0; // flush = 0;