[Modified] fix bug & pass pref test on board

2023-07-24 02:46:27 +08:00
parent 27ef99503d
commit 0352651836
2 changed files with 1 additions and 1 deletions
--- a/lacpu/rtl/mycpu/pip_ctrl.v
+++ b/lacpu/rtl/mycpu/pip_ctrl.v
@@ -35,7 +35,7 @@ module pip_ctrl(
        end
        else if (stallreq_es) begin
            flush = 0;
-            stall = `StallBus'b011111;
+            stall = `StallBus'b111111;
        end
        // else if(stallreq_cache) begin
        //     flush = 0;