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ddr3_general_design

Verilog 0 0

基于 ax7325t 的通用 axi 转 fifo 的 mig ddr3 控制接口项目模板

Updated 2025-06-06 16:26:37 +00:00

pcie_general_design

Verilog 0 0

基于 ax7325t 的通用 xdma pcie 控制接口项目模板

Updated 2025-06-06 16:26:19 +00:00