FPGALab/pcie_general_design
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UnbalancedCat b4742f753a init v0.1
2025-04-27 20:43:23 +08:00
pcie_general_design.srcs
init v0.1
2025-04-27 20:43:23 +08:00
.gitignore
init v0.1
2025-04-27 20:43:23 +08:00
pcie_general_design.xpr
init v0.1
2025-04-27 20:43:23 +08:00
Description
基于 ax7325t 的通用 xdma pcie 控制接口项目模板
1.2 MiB
Languages
Verilog 85.5%
SystemVerilog 11.9%
Tcl 2%
Shell 0.3%
Stata 0.2%