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ddr3_general_design
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5436d507e7a73ff419f249a3a11d3c6304b163b5
ddr3_general_design
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ddr3_general_design.srcs
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sources_1
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ip
History
UnbalancedCat
5436d507e7
most logic done (out has some issue, may has plenty of bugs)
2025-01-13 23:15:13 +08:00
..
ddr3_ctrl_0
first commit
2025-01-06 22:30:12 +08:00
ddr3_ctrl_1
first commit
2025-01-06 22:30:12 +08:00
fifo_rd_data
most logic done (out has some issue, may has plenty of bugs)
2025-01-13 23:15:13 +08:00
fifo_rd_info
most logic done (out has some issue, may has plenty of bugs)
2025-01-13 23:15:13 +08:00
fifo_rw_addr
most logic done (out has some issue, may has plenty of bugs)
2025-01-13 23:15:13 +08:00
fifo_rw_cmd
most logic done (out has some issue, may has plenty of bugs)
2025-01-13 23:15:13 +08:00
fifo_wr_mask_data
most logic done (out has some issue, may has plenty of bugs)
2025-01-13 23:15:13 +08:00
