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ddr3_general_design
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dbf9cb60237b92a2f2c2bb34796c1e2743eb7d7f
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4 Commits
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UnbalancedCat
cf3f100d53
redo axi construction
2025-03-18 16:56:47 +08:00
UnbalancedCat
5771113897
add axi
2025-03-18 12:11:59 +08:00
UnbalancedCat
5436d507e7
most logic done (out has some issue, may has plenty of bugs)
2025-01-13 23:15:13 +08:00
UnbalancedCat
30fa4e98fe
first commit
2025-01-06 22:30:12 +08:00