diff --git a/ddr3_general_design.srcs/sources_1/new/ddr_axi_m_rd.v b/ddr3_general_design.srcs/sources_1/new/ddr_axi_m_rd.v index d67e893..5a27d9d 100644 --- a/ddr3_general_design.srcs/sources_1/new/ddr_axi_m_rd.v +++ b/ddr3_general_design.srcs/sources_1/new/ddr_axi_m_rd.v @@ -62,8 +62,8 @@ module ddr_axi_m_rd #( localparam [4:0] S_RD_IDLE = 5'b00001, - S_RD_ADDR_START = 5'b00010, - S_RD_ADDR_WAIT = 5'b00100, + S_RD_ADDR_WAIT = 5'b00010, + S_RD_ADDR = 5'b00100, S_RD_DATA = 5'b01000, S_RD_DONE = 5'b10000; @@ -103,38 +103,26 @@ module ddr_axi_m_rd #( always @(*) begin fifo_ddr_rd_rd_en = 1'b0; fifo_ddr_rd_v = 1'b0; - n_state = S_RD_IDLE; - case(c_state) S_RD_IDLE: begin - fifo_ddr_rd_addr = 33'b0; - fifo_ddr_rd_len = 8'b0; if (!fifo_ddr_rd_empty_i) begin fifo_ddr_rd_rd_en = 1'b1; - n_state = S_RD_ADDR_START; + n_state = S_RD_ADDR_WAIT; end else begin n_state = S_RD_IDLE; end end - S_RD_ADDR_START: begin - fifo_ddr_rd_addr = fifo_ddr_rd_addr_i; - fifo_ddr_rd_len = fifo_ddr_rd_len_i; + S_RD_ADDR_WAIT: begin + n_state = S_RD_ADDR; + end + S_RD_ADDR: begin fifo_ddr_rd_v = 1'b1; if(m_axi_arready_i) begin n_state = S_RD_DATA; end else begin - n_state = S_RD_ADDR_WAIT; - end - end - S_RD_ADDR_WAIT: begin - fifo_ddr_rd_v = 1'b1; - if(m_axi_arready_i) begin - n_state = S_RD_DATA; - end - else begin - n_state = S_RD_ADDR_WAIT; + n_state = S_RD_ADDR; end end S_RD_DATA: begin @@ -162,4 +150,19 @@ module ddr_axi_m_rd #( end endcase end + + always @(posedge ui_clk_i or posedge ui_rst_i) begin + if(ui_rst_i) begin + fifo_ddr_rd_addr <= 33'b0; + fifo_ddr_rd_len <= 8'b0; + end + else if(fifo_ddr_rd_v_i) begin + fifo_ddr_rd_addr <= fifo_ddr_rd_addr_i; + fifo_ddr_rd_len <= fifo_ddr_rd_len_i; + end + else begin + fifo_ddr_rd_addr <= fifo_ddr_rd_addr; + fifo_ddr_rd_len <= fifo_ddr_rd_len; + end + end endmodule diff --git a/ddr3_general_design.srcs/sources_1/new/ddr_axi_m_top.v b/ddr3_general_design.srcs/sources_1/new/ddr_axi_m_top.v index 74c7fe7..f700ee6 100644 --- a/ddr3_general_design.srcs/sources_1/new/ddr_axi_m_top.v +++ b/ddr3_general_design.srcs/sources_1/new/ddr_axi_m_top.v @@ -1,25 +1,24 @@ `timescale 1ns / 1ps ////////////////////////////////////////////////////////////////////////////////// // Company: -// Engineer: UnbalancedCat +// Engineer: // // Create Date: 2025/04/02 14:35:06 // Design Name: // Module Name: ddr_axi_m_top -// Project Name: ddr3_general_design -// Target Devices: ax7325_xc7k325tffg900-2 -// Tool Versions: vivado 2019.2 +// Project Name: +// Target Devices: +// Tool Versions: // Description: // // Dependencies: // // Revision: -// Revision v2.1 - add conditional compilation +// Revision 0.01 - File Created // Additional Comments: // ////////////////////////////////////////////////////////////////////////////////// -`define MIG_IP_IS_INCLUDED module ddr_axi_m_top #( parameter ADDR_WIDTH = 33, // 8GB @@ -28,29 +27,9 @@ module ddr_axi_m_top #( ( input sys_clk_i, input sys_rst_i, - -`ifdef MIG_IP_IS_INCLUDED - inout [63:0] ddr3_dq_io, - inout [7:0] ddr3_dqs_n_io, - inout [7:0] ddr3_dqs_p_io, - - output [15:0] ddr3_addr_o, - output [2:0] ddr3_ba_o, - output ddr3_ras_n_o, - output ddr3_cas_n_o, - output ddr3_we_n_o, - output ddr3_reset_n_o, - output [1:0] ddr3_ck_p_o, - output [1:0] ddr3_ck_n_o, - output [1:0] ddr3_cke_o, - output [1:0] ddr3_cs_n_o, - output [7:0] ddr3_dm_o, - output [1:0] ddr3_odt_o, - - output init_calib_complete_o, -`else input ui_clk_i, input ui_rst_i, + // Master Interface Read Address Ports output [3:0] m_axi_arid_o, output [ADDR_WIDTH-1:0] m_axi_araddr_o, @@ -69,6 +48,7 @@ module ddr_axi_m_top #( input [1:0] m_axi_rresp_i, input m_axi_rlast_i, input m_axi_rvalid_i, + // Master Interface Write Address Ports output [3:0] m_axi_awid_o, output [ADDR_WIDTH-1:0] m_axi_awaddr_o, @@ -91,7 +71,6 @@ module ddr_axi_m_top #( input [3:0] m_axi_bid_i, input [1:0] m_axi_bresp_i, input m_axi_bvalid_i, -`endif output fifo_ddr_rd_almost_full_o, output fifo_ddr_rd_full_o, @@ -137,7 +116,6 @@ module ddr_axi_m_top #( wire fifo_ddr_wr_addr_v; wire [7:0] fifo_ddr_wr_len; wire fifo_ddr_wr_len_v; - wire fifo_ddr_wdata_empty; wire fifo_ddr_wstrb_empty; wire fifo_ddr_wdata_rd_en; @@ -171,202 +149,6 @@ module ddr_axi_m_top #( assign fifo_ddr_wdata_almost_full_o = fifo_ddr_wdata_almost_full & fifo_ddr_wstrb_almost_full; assign fifo_ddr_wdata_full_o = fifo_ddr_wdata_full & fifo_ddr_wstrb_full; - -`ifdef MIG_IP_IS_INCLUDED - wire ui_clk; - wire ui_rst; - - // Slave Interface Write Address Ports - wire [3:0] m_axi_awid; - wire [32:0] m_axi_awaddr; - wire [7:0] m_axi_awlen; - wire [2:0] m_axi_awsize; - wire [1:0] m_axi_awburst; - wire [0:0] m_axi_awlock; - wire [3:0] m_axi_awcache; - wire [2:0] m_axi_awprot; - wire m_axi_awvalid; - wire m_axi_awready; - // Slave Interface Write Data Ports - wire [127:0] m_axi_wdata; - wire [15:0] m_axi_wstrb; - wire m_axi_wlast; - wire m_axi_wvalid; - wire m_axi_wready; - // Slave Interface Write Response Ports - wire m_axi_bready; - wire [3:0] m_axi_bid; - wire [1:0] m_axi_bresp; - wire m_axi_bvalid; - // Slave Interface Read Address Ports - wire [3:0] m_axi_arid; - wire [32:0] m_axi_araddr; - wire [7:0] m_axi_arlen; - wire [2:0] m_axi_arsize; - wire [1:0] m_axi_arburst; - wire [0:0] m_axi_arlock; - wire [3:0] m_axi_arcache; - wire [2:0] m_axi_arprot; - wire m_axi_arvalid; - wire m_axi_arready; - // Slave Interface Read Data Ports - wire m_axi_rready; - wire [3:0] m_axi_rid; - wire [127:0] m_axi_rdata; - wire [1:0] m_axi_rresp; - wire m_axi_rlast; - wire m_axi_rvalid; - - ddr3_ctrl ddr3_ctrl_inst( - // Memory interface ports - .ddr3_addr (ddr3_addr_o), - .ddr3_ba (ddr3_ba_o), - .ddr3_cas_n (ddr3_cas_n_o), - .ddr3_ck_n (ddr3_ck_n_o), - .ddr3_ck_p (ddr3_ck_p_o), - .ddr3_cke (ddr3_cke_o), - .ddr3_ras_n (ddr3_ras_n_o), - .ddr3_we_n (ddr3_we_n_o), - .ddr3_dq (ddr3_dq_io), - .ddr3_dqs_n (ddr3_dqs_n_io), - .ddr3_dqs_p (ddr3_dqs_p_io), - .ddr3_reset_n (ddr3_reset_n_o), - .init_calib_complete (init_calib_complete_o), - .ddr3_cs_n (ddr3_cs_n_o), - .ddr3_dm (ddr3_dm_o), - .ddr3_odt (ddr3_odt_o), - // Application interface ports - .ui_clk (ui_clk), // 100 Mhz - .ui_clk_sync_rst (ui_rst), - .mmcm_locked (), - .aresetn (~ui_rst), - .app_sr_req (1'b0), - .app_ref_req (1'b0), - .app_zq_req (1'b0), - .app_sr_active (), - .app_ref_ack (), - .app_zq_ack (), - // Slave Interface Write Address Ports - .s_axi_awid (m_axi_awid), - .s_axi_awaddr (m_axi_awaddr), - .s_axi_awlen (m_axi_awlen), - .s_axi_awsize (m_axi_awsize), - .s_axi_awburst (m_axi_awburst), - .s_axi_awlock (m_axi_awlock), - .s_axi_awcache (m_axi_awcache), - .s_axi_awprot (m_axi_awprot), - .s_axi_awqos (4'h0), - .s_axi_awvalid (m_axi_awvalid), - .s_axi_awready (m_axi_awready), - // Slave Interface Write Data Ports - .s_axi_wdata (m_axi_wdata), - .s_axi_wstrb (m_axi_wstrb), - .s_axi_wlast (m_axi_wlast), - .s_axi_wvalid (m_axi_wvalid), - .s_axi_wready (m_axi_wready), - // Slave Interface Write Response Ports - .s_axi_bid (m_axi_bid), - .s_axi_bresp (m_axi_bresp), - .s_axi_bvalid (m_axi_bvalid), - .s_axi_bready (m_axi_bready), - // Slave Interface Read Address Ports - .s_axi_arid (m_axi_arid), - .s_axi_araddr (m_axi_araddr), - .s_axi_arlen (m_axi_arlen), - .s_axi_arsize (m_axi_arsize), - .s_axi_arburst (m_axi_arburst), - .s_axi_arlock (m_axi_arlock), - .s_axi_arcache (m_axi_arcache), - .s_axi_arprot (m_axi_arprot), - .s_axi_arqos (4'h0), - .s_axi_arvalid (m_axi_arvalid), - .s_axi_arready (m_axi_arready), - // Slave Interface Read Data Ports - .s_axi_rid (m_axi_rid), - .s_axi_rdata (m_axi_rdata), - .s_axi_rresp (m_axi_rresp), - .s_axi_rlast (m_axi_rlast), - .s_axi_rvalid (m_axi_rvalid), - .s_axi_rready (m_axi_rready), - // System Clock Ports - .sys_clk_i (sys_clk_i), // 200 Mhz - .sys_rst (sys_rst_i) - ); - - - ddr_axi_m_rd #( - .ADDR_WIDTH (ADDR_WIDTH ), - .DATA_WIDTH (DATA_WIDTH ) - ) - ddr_axi_m_rd_inst ( - .ui_clk_i (ui_clk ), - .ui_rst_i (ui_rst ), - - .m_axi_arid_o (m_axi_arid ), - .m_axi_araddr_o (m_axi_araddr ), - .m_axi_arlen_o (m_axi_arlen ), - .m_axi_arsize_o (m_axi_arsize ), - .m_axi_arburst_o (m_axi_arburst ), - .m_axi_arlock_o (m_axi_arlock ), - .m_axi_arcache_o (m_axi_arcache ), - .m_axi_arprot_o (m_axi_arprot ), - .m_axi_arvalid_o (m_axi_arvalid ), - .m_axi_arready_i (m_axi_arready ), - .m_axi_rready_o (m_axi_rready ), - .m_axi_rid_i (m_axi_rid ), - .m_axi_rdata_i (m_axi_rdata ), - .m_axi_rresp_i (m_axi_rresp ), - .m_axi_rlast_i (m_axi_rlast ), - .m_axi_rvalid_i (m_axi_rvalid ), - .fifo_ddr_rd_empty_i (fifo_ddr_rd_addr_empty & fifo_ddr_rd_len_empty), - .fifo_ddr_rd_rd_en_o (fifo_ddr_rd_rd_en ), - .fifo_ddr_rd_v_i (fifo_ddr_rd_addr_v & fifo_ddr_rd_len_v), - .fifo_ddr_rd_addr_i (fifo_ddr_rd_addr ), - .fifo_ddr_rd_len_i (fifo_ddr_rd_len ), - .fifo_ddr_rdata_almost_full_i (fifo_ddr_rdata_almost_full ), - .fifo_ddr_rdata_wr_en_o (fifo_ddr_rdata_wr_en ), - .fifo_ddr_rdata_o (fifo_ddr_rdata ) - ); - - ddr_axi_m_wr #( - .ADDR_WIDTH (ADDR_WIDTH ), - .DATA_WIDTH (DATA_WIDTH ) - ) - ddr_axi_m_wr_inst ( - .ui_clk_i (ui_clk ), - .ui_rst_i (ui_rst ), - - .m_axi_awid_o (m_axi_awid ), - .m_axi_awaddr_o (m_axi_awaddr ), - .m_axi_awlen_o (m_axi_awlen ), - .m_axi_awsize_o (m_axi_awsize ), - .m_axi_awburst_o (m_axi_awburst ), - .m_axi_awlock_o (m_axi_awlock ), - .m_axi_awcache_o (m_axi_awcache ), - .m_axi_awprot_o (m_axi_awprot ), - .m_axi_awvalid_o (m_axi_awvalid ), - .m_axi_awready_i (m_axi_awready ), - .m_axi_wdata_o (m_axi_wdata ), - .m_axi_wstrb_o (m_axi_wstrb ), - .m_axi_wlast_o (m_axi_wlast ), - .m_axi_wvalid_o (m_axi_wvalid ), - .m_axi_wready_i (m_axi_wready ), - .m_axi_bready_o (m_axi_bready ), - .m_axi_bid_i (m_axi_bid ), - .m_axi_bresp_i (m_axi_bresp ), - .m_axi_bvalid_i (m_axi_bvalid ), - .fifo_ddr_wr_empty_i (fifo_ddr_wr_addr_empty & fifo_ddr_wr_len_empty), - .fifo_ddr_wr_rd_en_o (fifo_ddr_wr_rd_en ), - .fifo_ddr_wr_v_i (fifo_ddr_wr_addr_v & fifo_ddr_wr_len_v), - .fifo_ddr_wr_addr_i (fifo_ddr_wr_addr ), - .fifo_ddr_wr_len_i (fifo_ddr_wr_len ), - .fifo_ddr_wdata_empty_i (fifo_ddr_wdata_empty & fifo_ddr_wstrb_empty), - .fifo_ddr_wdata_rd_en_o (fifo_ddr_wdata_rd_en ), - .fifo_ddr_wdata_v_i (fifo_ddr_wdata_v & fifo_ddr_wstrb_v), - .fifo_ddr_wdata_i (fifo_ddr_wdata ), - .fifo_ddr_wstrb_i (fifo_ddr_wstrb ) - ); -`else ddr_axi_m_rd #( .ADDR_WIDTH (ADDR_WIDTH ), .DATA_WIDTH (DATA_WIDTH ) @@ -393,7 +175,7 @@ module ddr_axi_m_top #( .m_axi_rvalid_i (m_axi_rvalid_i ), .fifo_ddr_rd_empty_i (fifo_ddr_rd_addr_empty & fifo_ddr_rd_len_empty), .fifo_ddr_rd_rd_en_o (fifo_ddr_rd_rd_en ), - .fifo_ddr_rd_v_i (fifo_ddr_rd_addr_v & fifo_ddr_rd_len_v), + .fifo_ddr_rd_v_i (fifo_ddr_rd_addr_v & fifo_ddr_rd_len_v ), .fifo_ddr_rd_addr_i (fifo_ddr_rd_addr ), .fifo_ddr_rd_len_i (fifo_ddr_rd_len ), .fifo_ddr_rdata_almost_full_i (fifo_ddr_rdata_almost_full ), @@ -401,6 +183,7 @@ module ddr_axi_m_top #( .fifo_ddr_rdata_o (fifo_ddr_rdata ) ); + ddr_axi_m_wr #( .ADDR_WIDTH (ADDR_WIDTH ), .DATA_WIDTH (DATA_WIDTH ) @@ -439,7 +222,6 @@ module ddr_axi_m_top #( .fifo_ddr_wdata_i (fifo_ddr_wdata ), .fifo_ddr_wstrb_i (fifo_ddr_wstrb ) ); -`endif fifo_ddr_addr fifo_ddr_rd_addr_inst( .wr_clk (sys_clk_i), @@ -545,4 +327,5 @@ module ddr_axi_m_top #( .valid (fifo_ddr_wstrb_v), .rd_en (fifo_ddr_wdata_rd_en) ); + endmodule diff --git a/ddr3_general_design.srcs/sources_1/new/ddr_axi_m_wr.v b/ddr3_general_design.srcs/sources_1/new/ddr_axi_m_wr.v index 278a8b8..d43df90 100644 --- a/ddr3_general_design.srcs/sources_1/new/ddr_axi_m_wr.v +++ b/ddr3_general_design.srcs/sources_1/new/ddr_axi_m_wr.v @@ -67,11 +67,11 @@ module ddr_axi_m_wr #( localparam [6:0] S_WR_IDLE = 7'b0000001, - S_WR_ADDR = 7'b0000010, - S_WR_ADDR_WAIT = 7'b0000100, + S_WR_ADDR_WAIT = 7'b0000010, + S_WR_ADDR = 7'b0000100, S_WR_DATA_START = 7'b0001000, - S_WR_DATA = 7'b0010000, - S_WR_DATA_WAIT = 7'b0100000, + S_WR_DATA_WAIT = 7'b0010000, + S_WR_DATA = 7'b0100000, S_WR_DONE = 7'b1000000; reg [6:0] c_state; @@ -137,96 +137,64 @@ module ddr_axi_m_wr #( case(c_state) S_WR_IDLE: begin wr_data_cnt_clr = 1'b1; - fifo_ddr_wr_addr = 33'b0; - fifo_ddr_wr_len = 8'b0; if (!fifo_ddr_wr_empty_i) begin fifo_ddr_wr_rd_en = 1'b1; - n_state = S_WR_ADDR; + n_state = S_WR_ADDR_WAIT; end else begin n_state = S_WR_IDLE; end end - S_WR_ADDR: begin - fifo_ddr_wr_addr = fifo_ddr_wr_addr_i; - fifo_ddr_wr_len = fifo_ddr_wr_len_i; - fifo_ddr_wr_v = 1'b1; - if(m_axi_awready_i) begin - n_state = S_WR_DATA_START; - end - else begin - n_state = S_WR_ADDR_WAIT; - end - end S_WR_ADDR_WAIT: begin + n_state = S_WR_ADDR; + end + S_WR_ADDR: begin fifo_ddr_wr_v = 1'b1; if(m_axi_awready_i) begin n_state = S_WR_DATA_START; end else begin - n_state = S_WR_ADDR_WAIT; + n_state = S_WR_ADDR; end end S_WR_DATA_START: begin - if (!fifo_ddr_wdata_empty_i) begin + if(!fifo_ddr_wdata_empty_i) begin fifo_ddr_wdata_rd_en = 1'b1; wr_data_cnt_inc = 1'b1; - n_state = S_WR_DATA; - end else begin + n_state = S_WR_DATA_WAIT; + end + else begin n_state = S_WR_DATA_START; end end - S_WR_DATA: begin - fifo_ddr_wdata = fifo_ddr_wdata_i; - fifo_ddr_wstrb = fifo_ddr_wstrb_i; - fifo_ddr_wdata_v = 1'b1; - casex({wr_data_cnt_is_thresh, m_axi_wready_i, !fifo_ddr_wdata_empty_i}) - 3'b00x: begin - n_state = S_WR_DATA_WAIT; - end - 3'b010: begin - n_state = S_WR_DATA_START; - end - 3'b011: begin - fifo_ddr_wdata_v = 1'b1; - fifo_ddr_wdata_rd_en = 1'b1; - wr_data_cnt_inc = 1'b1; - n_state = S_WR_DATA; - end - 3'b11x: begin - m_axi_wlast = 1'b1; - n_state = S_WR_DONE; - end - 3'b10x: begin - n_state = S_WR_DATA_WAIT; - end - endcase - end S_WR_DATA_WAIT: begin + n_state = S_WR_DATA; + end + S_WR_DATA: begin fifo_ddr_wdata_v = 1'b1; - casex({wr_data_cnt_is_thresh, m_axi_wready_i, !fifo_ddr_wdata_empty_i}) + casex({wr_data_cnt_is_thresh, m_axi_wready_i, fifo_ddr_wdata_empty_i}) 3'b00x: begin - n_state = S_WR_DATA_WAIT; + n_state = S_WR_DATA; end 3'b010: begin - n_state = S_WR_DATA_START; - end - 3'b011: begin fifo_ddr_wdata_rd_en = 1'b1; wr_data_cnt_inc = 1'b1; - n_state = S_WR_DATA; + n_state = S_WR_DATA_WAIT; + end + 3'b011: begin + n_state = S_WR_DATA_START; + end + 3'b10x: begin + n_state = S_WR_DATA; end 3'b11x: begin m_axi_wlast = 1'b1; n_state = S_WR_DONE; end - 3'b10x: begin - n_state = S_WR_DATA_WAIT; - end endcase end S_WR_DONE: begin - if (m_axi_bvalid_i && m_axi_bresp_i == 2'b00) begin + if (m_axi_bvalid_i && (m_axi_bresp_i == 2'b00)) begin m_axi_bready = 1'b1; n_state = S_WR_IDLE; end else begin @@ -253,4 +221,35 @@ module ddr_axi_m_wr #( wr_data_cnt <= wr_data_cnt; end end + + always @(posedge ui_clk_i or posedge ui_rst_i) begin + if(ui_rst_i) begin + fifo_ddr_wr_addr <= 33'b0; + fifo_ddr_wr_len <= 8'b0; + end + else if(fifo_ddr_wr_v_i) begin + fifo_ddr_wr_addr <= fifo_ddr_wr_addr_i; + fifo_ddr_wr_len <= fifo_ddr_wr_len_i; + end + else begin + fifo_ddr_wr_addr <= fifo_ddr_wr_addr; + fifo_ddr_wr_len <= fifo_ddr_wr_len; + end + end + + always @(posedge ui_clk_i or posedge ui_rst_i) begin + if(ui_rst_i) begin + fifo_ddr_wdata <= 33'b0; + fifo_ddr_wstrb <= 8'b0; + end + else if(fifo_ddr_wdata_v_i) begin + fifo_ddr_wdata <= fifo_ddr_wdata_i; + fifo_ddr_wstrb <= fifo_ddr_wstrb_i; + + end + else begin + fifo_ddr_wdata <= fifo_ddr_wdata; + fifo_ddr_wstrb <= fifo_ddr_wstrb; + end + end endmodule