diff --git a/ddr_general_design.srcs/sources_1/ip/ddr_ctrl/ddr_ctrl.xci b/ddr_general_design.srcs/sources_1/ip/ddr_ctrl/ddr_ctrl.xci index dd527f1..55ad6be 100644 --- a/ddr_general_design.srcs/sources_1/ip/ddr_ctrl/ddr_ctrl.xci +++ b/ddr_general_design.srcs/sources_1/ip/ddr_ctrl/ddr_ctrl.xci @@ -1092,34 +1092,34 @@ 100000000 0 0.000 - 1 + 33 0 0 0 - 1 - 0 - 0 - 0 - 0 - 0 - 0 + 512 + 1 + 1 + 1 + 1 + 1 + 1 0 - 0 - 0 - 0 + 1 + 1 + 4 0 - 1 - 1 + 256 + 2 1 - 1 + 2 1 0.000 - AXI4LITE + AXI4 READ_WRITE 0 0 - 0 + 1 0 0 1 @@ -2169,14 +2169,14 @@ FALSE 0 0 - 32 + 33 32 32 4 1048576 - 32 + 512 4 - 1048576 + 8589934592 8 3 1 @@ -2196,24 +2196,24 @@ 1 2 1 - 8 + 30 3 - 1 - 1 - 1 - 8 + 2 + 2 + 2 + 64 OFF - 1 - 1 - 1 - 8 - 1 + 8 + 3 + 8 + 64 + 2 OFF - 14 + 16 1 1 1 - 2 + 4 1 8 8 @@ -2221,7 +2221,7 @@ OFF 1 OFF - 100.0 + 100000000 FALSE 8 3 @@ -2252,8 +2252,8 @@ 10 FALSE 10 - 1200.0 - 0 + 800 + 1 0.000 ACTIVE_LOW 29 @@ -2262,7 +2262,7 @@ 18 OFF 1 - DIFF + NONE 29 2 1 @@ -2295,15 +2295,15 @@ 18 1 1 - DIFF + NOBUF INTERNAL FALSE - 0 + 1 Custom ddr_ctrl Custom Custom - + mig_a.prj kintex7 @@ -2329,6 +2329,141 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + @@ -2343,6 +2478,7 @@ + @@ -2361,6 +2497,7 @@ + @@ -2378,6 +2515,7 @@ + @@ -2396,6 +2534,7 @@ + @@ -2413,6 +2552,7 @@ + @@ -2431,6 +2571,7 @@ + @@ -2448,6 +2589,7 @@ + @@ -2466,6 +2608,7 @@ + @@ -2483,6 +2626,7 @@ + @@ -2501,6 +2645,7 @@ + @@ -2518,6 +2663,7 @@ + @@ -2536,6 +2682,7 @@ + @@ -2553,6 +2700,7 @@ + @@ -2571,6 +2719,7 @@ + @@ -2588,6 +2737,7 @@ + @@ -2606,9 +2756,12 @@ + + + @@ -2623,6 +2776,8 @@ + + @@ -2641,9 +2796,14 @@ + + + + + diff --git a/ddr_general_design.srcs/sources_1/ip/fifo_ddr_addr/fifo_ddr_addr.xci b/ddr_general_design.srcs/sources_1/ip/fifo_ddr_addr/fifo_ddr_addr.xci index 7701259..b1b9838 100644 --- a/ddr_general_design.srcs/sources_1/ip/fifo_ddr_addr/fifo_ddr_addr.xci +++ b/ddr_general_design.srcs/sources_1/ip/fifo_ddr_addr/fifo_ddr_addr.xci @@ -152,9 +152,9 @@ 1 1 0 - 10 + 6 BlankString - 18 + 33 1 32 64 @@ -162,7 +162,7 @@ 64 2 0 - 18 + 33 0 1 0 @@ -217,8 +217,8 @@ 0 1 0 - 0 - 0 + 1 + 1 0 0 0 @@ -238,7 +238,7 @@ 0 1 0 - 1kx18 + 512x36 1kx18 512x36 1kx36 @@ -260,14 +260,14 @@ 0 0 0 - 1022 + 62 1023 1023 1023 1023 1023 1023 - 1021 + 61 0 0 0 @@ -277,10 +277,10 @@ 0 0 0 - 10 - 1024 + 6 + 64 1 - 10 + 6 0 0 0 @@ -310,8 +310,8 @@ 0 0 0 - 10 - 1024 + 6 + 64 1024 16 1024 @@ -319,7 +319,7 @@ 1024 16 1 - 10 + 6 10 4 10 @@ -340,7 +340,7 @@ fifo_ddr_addr 64 false - 10 + 6 false false 0 @@ -386,14 +386,14 @@ Common_Clock_Block_RAM Common_Clock_Block_RAM 0 - 1022 + 62 1023 1023 1023 1023 1023 1023 - 1021 + 61 false false false @@ -413,8 +413,8 @@ false false false - 18 - 1024 + 33 + 64 1024 16 1024 @@ -422,8 +422,8 @@ 1024 16 false - 18 - 1024 + 33 + 64 Embedded_Reg false false @@ -449,7 +449,7 @@ 0 1 false - 10 + 6 Fully_Registered Fully_Registered Fully_Registered @@ -473,14 +473,14 @@ false false false - false + true Active_High 0 - false + true Active_High 1 false - 10 + 6 false FIFO false @@ -548,6 +548,17 @@ + + + + + + + + + + + diff --git a/ddr_general_design.srcs/sources_1/ip/fifo_ddr_info/fifo_ddr_info.xci b/ddr_general_design.srcs/sources_1/ip/fifo_ddr_info/fifo_ddr_info.xci index 386584d..2e9ddff 100644 --- a/ddr_general_design.srcs/sources_1/ip/fifo_ddr_info/fifo_ddr_info.xci +++ b/ddr_general_design.srcs/sources_1/ip/fifo_ddr_info/fifo_ddr_info.xci @@ -152,9 +152,9 @@ 1 1 0 - 10 + 6 BlankString - 18 + 5 1 32 64 @@ -162,7 +162,7 @@ 64 2 0 - 18 + 5 0 1 0 @@ -238,7 +238,7 @@ 0 1 0 - 1kx18 + 512x36 1kx18 512x36 1kx36 @@ -260,14 +260,14 @@ 0 0 0 - 1022 + 62 1023 1023 1023 1023 1023 1023 - 1021 + 61 0 0 0 @@ -277,10 +277,10 @@ 0 0 0 - 10 - 1024 + 6 + 64 1 - 10 + 6 0 0 0 @@ -310,8 +310,8 @@ 0 0 0 - 10 - 1024 + 6 + 64 1024 16 1024 @@ -319,7 +319,7 @@ 1024 16 1 - 10 + 6 10 4 10 @@ -340,7 +340,7 @@ fifo_ddr_info 64 false - 10 + 6 false false 0 @@ -386,14 +386,14 @@ Common_Clock_Block_RAM Common_Clock_Block_RAM 0 - 1022 + 62 1023 1023 1023 1023 1023 1023 - 1021 + 61 false false false @@ -413,8 +413,8 @@ false false false - 18 - 1024 + 5 + 64 1024 16 1024 @@ -422,8 +422,8 @@ 1024 16 false - 18 - 1024 + 5 + 64 Embedded_Reg false false @@ -449,7 +449,7 @@ 0 1 false - 10 + 6 Fully_Registered Fully_Registered Fully_Registered @@ -480,7 +480,7 @@ Active_High 1 false - 10 + 6 false FIFO false @@ -548,8 +548,17 @@ + + + + + + + + + diff --git a/ddr_general_design.srcs/sources_1/new/ddr_axi_rd.v b/ddr_general_design.srcs/sources_1/new/ddr_axi_rd.v index 01a6df2..65a0762 100644 --- a/ddr_general_design.srcs/sources_1/new/ddr_axi_rd.v +++ b/ddr_general_design.srcs/sources_1/new/ddr_axi_rd.v @@ -25,11 +25,11 @@ module ddr_axi_rd( input aclk, //axi时钟 //axi读通道写地址 output [3:0] m_axi_arid , //读地址ID，用来标志一组写信号 - output [31:0] m_axi_araddr , //读地址，给出一次写突发传输的读地址 + output [32:0] m_axi_araddr , //读地址，给出一次写突发传输的读地址 output [7:0] m_axi_arlen , //突发长度，给出突发传输的次数 output [2:0] m_axi_arsize , //突发大小，给出每次突发传输的字节数 output [1:0] m_axi_arburst, //突发类型 - output [1:0] m_axi_arlock , //总线锁信号，可提供操作的原子性 + output [0:0] m_axi_arlock , //总线锁信号，可提供操作的原子性 output [3:0] m_axi_arcache, //内存类型，表明一次传输是怎样通过系统的 output [2:0] m_axi_arprot , //保护类型，表明一次传输的特权级及安全等级 output [3:0] m_axi_arqos , //质量服务QOS @@ -45,7 +45,7 @@ module ddr_axi_rd( output m_axi_rready, //表明主机能够接收读数据和响应信息 //用户端fifo接口 input rd_start , //读突发触发信号 - input [31:0] rd_adrs , //地址 + input [32:0] rd_adrs , //地址 input [9:0] rd_len , //长度 output rd_ready , //读空闲 output rd_fifo_we , //连接到读fifo的写使能 @@ -66,7 +66,7 @@ localparam S_RD_PROC = 3'd4; //读数据循环 localparam S_RD_DONE = 3'd5; //写结束 //reg define reg [2:0] rd_state ; //状态寄存器 -reg [31:0] reg_rd_adrs; //地址寄存器 +reg [32:0] reg_rd_adrs; //地址寄存器 reg [31:0] reg_rd_len ; //突发长度寄存器 reg reg_arvalid; //地址有效寄存器 @@ -76,7 +76,7 @@ reg reg_arvalid; //地址有效寄存器 assign rd_done = (rd_state == S_RD_DONE) ; assign m_axi_arid = 4'b1111;//地址id -assign m_axi_araddr[31:0] = reg_rd_adrs[31:0];//地址 +assign m_axi_araddr[32:0] = reg_rd_adrs[32:0];//地址 assign m_axi_arlen[7:0] = rd_len-32'd1;//突发长度 assign m_axi_arsize[2:0] = 3'b011;//表示AXI总线每个数据宽度是8字节，64位 assign m_axi_arburst[1:0] = 2'b01;//地址递增方式传输 @@ -94,7 +94,7 @@ assign rd_fifo_data[63:0] = m_axi_rdata[63:0];//读fifo的写数据信号 always @(posedge aclk or negedge aresetn) begin if(!aresetn) begin rd_state <= S_RD_IDLE; - reg_rd_adrs[31:0] <= 32'd0; + reg_rd_adrs[32:0] <= 33'd0; reg_rd_len[31:0] <= 32'd0; reg_arvalid <= 1'b0; end else begin @@ -102,7 +102,7 @@ assign rd_fifo_data[63:0] = m_axi_rdata[63:0];//读fifo的写数据信号 S_RD_IDLE: begin//读空闲 if(rd_start) begin//突发触发信号 rd_state <= S_RA_WAIT; - reg_rd_adrs[31:0] <= rd_adrs[31:0]; + reg_rd_adrs[32:0] <= rd_adrs[32:0]; reg_rd_len[31:0] <= rd_len[9:0] -32'd1; end reg_arvalid <= 1'b0; diff --git a/ddr_general_design.srcs/sources_1/new/ddr_ctrl_top.v b/ddr_general_design.srcs/sources_1/new/ddr_ctrl_top.v index ffcfec2..8eb2a8f 100644 --- a/ddr_general_design.srcs/sources_1/new/ddr_ctrl_top.v +++ b/ddr_general_design.srcs/sources_1/new/ddr_ctrl_top.v @@ -65,6 +65,46 @@ module ddr_ctrl_top( // Range: 0, 1 + + + +// Output declaration of module ddr_axi_rd + wire [3:0] m_axi_arid; + wire [32:0] m_axi_araddr; + wire [7:0] m_axi_arlen; + wire [2:0] m_axi_arsize; + wire [1:0] m_axi_arburst; + wire [0:0] m_axi_arlock; + wire [3:0] m_axi_arcache; + wire [2:0] m_axi_arprot; + wire [3:0] m_axi_arqos; + wire m_axi_arvalid; + wire m_axi_rready; + wire rd_ready; + wire rd_fifo_we; + wire [511:0] rd_fifo_data; + wire rd_done; + +// Output declaration of module ddr_axi_wr + wire [3:0] m_axi_awid; + wire [32:0] m_axi_awaddr; + wire [7:0] m_axi_awlen; + wire [2:0] m_axi_awsize; + wire [1:0] m_axi_awburst; + wire m_axi_awlock; + wire [3:0] m_axi_awcache; + wire [2:0] m_axi_awprot; + wire [3:0] m_axi_awqos; + wire m_axi_awvalid; + wire [511:0] m_axi_wdata; + wire [63:0] m_axi_wstrb; + wire m_axi_wlast; + wire m_axi_wvalid; + wire m_axi_bready; + wire wr_ready; + wire wr_fifo_re; + wire wr_done; + // Slave Interface Write Address Ports wire [C_S_AXI_ID_WIDTH-1:0] s_axi_awid; wire [C_S_AXI_ADDR_WIDTH-1:0] s_axi_awaddr; @@ -107,27 +147,20 @@ module ddr_ctrl_top( wire s_axi_rvalid; fifo_axi_ctrl fifo_axi_ctrl_inst( - + .rw_req (rw_req_i ), + .rw_addr (rw_addr_i ), + .rw_fifo_buzy (rw_fifo_buzy_o ), + .rd_length (rd_length_i ), + .wr_data (wr_data_i ), + .wr_mask (wr_mask_i ), + .rw_where (rw_where_i ), + .rw_in_fifo_ack (rw_in_fifo_ack_o ), + .rw_in_fifo_ack_2where (rw_in_fifo_ack_2where_o), + .rd_data (rd_data_o ), + .rd_valid (rd_valid_o ), + .rd_valid_2where (rd_valid_2where_o ) ); - -// Output declaration of module ddr_axi_rd - wire [3:0] m_axi_arid; - wire [31:0] m_axi_araddr; - wire [7:0] m_axi_arlen; - wire [2:0] m_axi_arsize; - wire [1:0] m_axi_arburst; - wire [1:0] m_axi_arlock; - wire [3:0] m_axi_arcache; - wire [2:0] m_axi_arprot; - wire [3:0] m_axi_arqos; - wire m_axi_arvalid; - wire m_axi_rready; - wire rd_ready; - wire rd_fifo_we; - wire [63:0] rd_fifo_data; - wire rd_done; - ddr_axi_rd u_ddr_axi_rd( .aresetn (aresetn ), .aclk (aclk ), @@ -157,26 +190,6 @@ ddr_axi_rd u_ddr_axi_rd( .rd_done (rd_done ) ); -// Output declaration of module ddr_axi_wr - wire [3:0] m_axi_awid; - wire [31:0] m_axi_awaddr; - wire [7:0] m_axi_awlen; - wire [2:0] m_axi_awsize; - wire [1:0] m_axi_awburst; - wire m_axi_awlock; - wire [3:0] m_axi_awcache; - wire [2:0] m_axi_awprot; - wire [3:0] m_axi_awqos; - wire m_axi_awvalid; - wire [63:0] m_axi_wdata; - wire [7:0] m_axi_wstrb; - wire m_axi_wlast; - wire m_axi_wvalid; - wire m_axi_bready; - wire wr_ready; - wire wr_fifo_re; - wire wr_done; - ddr_axi_wr u_ddr_axi_wr( .aresetn (aresetn ), .aclk (aclk ), diff --git a/ddr_general_design.srcs/sources_1/new/fifo_axi_ctrl.v b/ddr_general_design.srcs/sources_1/new/fifo_axi_ctrl.v index a99111d..3acb91e 100644 --- a/ddr_general_design.srcs/sources_1/new/fifo_axi_ctrl.v +++ b/ddr_general_design.srcs/sources_1/new/fifo_axi_ctrl.v @@ -21,13 +21,54 @@ module fifo_axi_ctrl( + input clk , + input rst , + input [1:0] rw_req , + input [32:0] rw_addr , + output rw_fifo_buzy , + input [4:0] rd_length , + input [511:0] wr_data , + input [63:0] wr_mask , + input [4:0] rw_where , + output rw_in_fifo_ack , + output [4:0] rw_in_fifo_ack_2where, + output [511:0] rd_data , + output rd_valid , + output [4:0] rd_valid_2where ); fifo2axi_convert fifo2axi_convert_inst( + .clk (), + .rst (), + .rw_req (), + .rw_addr (), + .rd_length (), + .wr_data (), + .wr_mask (), + .rw_where (), + .rw_in_fifo_ack (), + .rw_in_fifo_ack_2where (), + .rw_fifo_buzy (), + + .wr_start (), + .wr_adrs (), + .wr_len (), + .wr_ready (), + .wr_fifo_re (), + .wr_fifo_data (), + .wr_done (), + + .rd_start (), + .rd_adrs (), + .rd_len (), + .rd_ready (), + .rd_fifo_we (), + .rd_fifo_data (), + .rd_done () ); axi2fifo_convert axi2fifo_convert_inst( @@ -35,24 +76,69 @@ module fifo_axi_ctrl( ); - - fifo_ddr_addr fifo_ddr_raddr_inst( - - ); - - fifo_ddr_data fifo_ddr_rdata_inst( - - ); - fifo_ddr_addr fifo_ddr_waddr_inst( - + .clk (clk), + .srst (rst), + .full (fifo_ddr_waddr_full), + .din (fifo_ddr_waddr_din), + .wr_en (fifo_ddr_waddr_we), + .empty (fifo_ddr_waddr_empty), + .dout (fifo_ddr_waddr_dout), + .rd_en (fifo_ddr_waddr_re), + .wr_ack (fifo_ddr_waddr_wack), + .valid (fifo_ddr_waddr_rv) ); fifo_ddr_data fifo_ddr_wdata_inst( - + .clk (clk), + .srst (rst), + .full (fifo_ddr_wdata_full), + .din (fifo_ddr_wdata_din), + .wr_en (fifo_ddr_wdata_we), + .empty (fifo_ddr_wdata_empty), + .dout (fifo_ddr_wdata_dout), + .rd_en (fifo_ddr_wdata_re), + .wr_ack (fifo_ddr_wdata_wack), + .valid (fifo_ddr_wdata_rv) ); + fifo_ddr_addr fifo_ddr_raddr_inst( + .clk (clk), + .srst (rst), + .full (fifo_ddr_raddr_full), + .din (fifo_ddr_raddr_din), + .wr_en (fifo_ddr_raddr_we), + .empty (fifo_ddr_raddr_empty), + .dout (fifo_ddr_raddr_dout), + .rd_en (fifo_ddr_raddr_re), + .wr_ack (fifo_ddr_raddr_wack), + .valid (fifo_ddr_raddr_rv) + ); + + fifo_ddr_data fifo_ddr_rdata_inst( + .clk (clk), + .srst (srst), + .full (fifo_ddr_rdata_full), + .din (fifo_ddr_rdata_din), + .wr_en (fifo_ddr_rdata_we), + .empty (fifo_ddr_rdata_empty), + .dout (fifo_ddr_rdata_dout), + .rd_en (fifo_ddr_rdata_re), + .wr_ack (fifo_ddr_rdata_wack), + .valid (fifo_ddr_rdata_rv) + ); + + fifo_ddr_info fifo_ddr_info_inst( - + .clk (clk), + .srst (rst), + .full (fifo_ddr_info_full), + .din (fifo_ddr_info_din), + .wr_en (fifo_ddr_info_we), + .empty (fifo_ddr_info_empty), + .dout (fifo_ddr_info_dout), + .rd_en (fifo_ddr_info_re), + .wr_ack (fifo_ddr_info_wack), + .valid (fifo_ddr_info_rv) ); endmodule diff --git a/ddr_general_design.xpr b/ddr_general_design.xpr index 718b5cf..86ba4ac 100644 --- a/ddr_general_design.xpr +++ b/ddr_general_design.xpr @@ -3,7 +3,7 @@ - +