diff --git a/.gitignore b/.gitignore index 67e2457..9b64f80 100644 --- a/.gitignore +++ b/.gitignore @@ -9,12 +9,12 @@ doc/** !others/** # vivado -!ddr3_general_design.xpr +!ddr_general_design.xpr ## srcs -!ddr3_general_design.srcs/constrs_1/** +!ddr_general_design.srcs/constrs_1/** -!ddr3_general_design.srcs/sources_1/ip/*/*.xci -!ddr3_general_design.srcs/sources_1/ip/*/*.coe +!ddr_general_design.srcs/sources_1/ip/*/*.xci +!ddr_general_design.srcs/sources_1/ip/*/*.coe -!ddr3_general_design.srcs/sources_1/new/** \ No newline at end of file +!ddr_general_design.srcs/sources_1/new/** \ No newline at end of file diff --git a/ddr3_general_design.srcs/constrs_1/ddr3_0.ucf b/ddr3_general_design.srcs/constrs_1/ddr3_0.ucf deleted file mode 100644 index 1a4a0f9..0000000 --- a/ddr3_general_design.srcs/constrs_1/ddr3_0.ucf +++ /dev/null @@ -1,117 +0,0 @@ -NET "clk_ref_n" LOC = "T39" | IOSTANDARD = DIFF_SSTL135 | VCCAUX_IO = DONTCARE ; -NET "clk_ref_p" LOC = "U39" | IOSTANDARD = DIFF_SSTL135 | VCCAUX_IO = DONTCARE ; -NET "ddr3_addr[0]" LOC = "T40" | | VCCAUX_IO = HIGH ; -NET "ddr3_addr[10]" LOC = "P32" | | VCCAUX_IO = HIGH ; -NET "ddr3_addr[11]" LOC = "W42" | | VCCAUX_IO = HIGH ; -NET "ddr3_addr[12]" LOC = "N33" | | VCCAUX_IO = HIGH ; -NET "ddr3_addr[13]" LOC = "W33" | | VCCAUX_IO = HIGH ; -NET "ddr3_addr[14]" LOC = "U41" | | VCCAUX_IO = HIGH ; -NET "ddr3_addr[1]" LOC = "P35" | | VCCAUX_IO = HIGH ; -NET "ddr3_addr[2]" LOC = "U33" | | VCCAUX_IO = HIGH ; -NET "ddr3_addr[3]" LOC = "U34" | | VCCAUX_IO = HIGH ; -NET "ddr3_addr[4]" LOC = "N34" | | VCCAUX_IO = HIGH ; -NET "ddr3_addr[5]" LOC = "U32" | | VCCAUX_IO = HIGH ; -NET "ddr3_addr[6]" LOC = "T42" | | VCCAUX_IO = HIGH ; -NET "ddr3_addr[7]" LOC = "V38" | | VCCAUX_IO = HIGH ; -NET "ddr3_addr[8]" LOC = "R34" | | VCCAUX_IO = HIGH ; -NET "ddr3_addr[9]" LOC = "V41" | | VCCAUX_IO = HIGH ; -NET "ddr3_ba[0]" LOC = "T36" | | VCCAUX_IO = HIGH ; -NET "ddr3_ba[1]" LOC = "R33" | | VCCAUX_IO = HIGH ; -NET "ddr3_ba[2]" LOC = "T34" | | VCCAUX_IO = HIGH ; -NET "ddr3_cas_n" LOC = "P37" | | VCCAUX_IO = HIGH ; -NET "ddr3_ck_n[0]" LOC = "U38" | | VCCAUX_IO = HIGH ; -NET "ddr3_ck_p[0]" LOC = "U37" | | VCCAUX_IO = HIGH ; -NET "ddr3_cke[0]" LOC = "R32" | | VCCAUX_IO = HIGH ; -NET "ddr3_cs_n[0]" LOC = "R35" | | VCCAUX_IO = HIGH ; -NET "ddr3_dm[0]" LOC = "F41" | | VCCAUX_IO = HIGH ; -NET "ddr3_dm[1]" LOC = "B41" | | VCCAUX_IO = HIGH ; -NET "ddr3_dm[2]" LOC = "AG42" | | VCCAUX_IO = HIGH ; -NET "ddr3_dm[3]" LOC = "AK40" | | VCCAUX_IO = HIGH ; -NET "ddr3_dm[4]" LOC = "L41" | | VCCAUX_IO = HIGH ; -NET "ddr3_dm[5]" LOC = "R40" | | VCCAUX_IO = HIGH ; -NET "ddr3_dm[6]" LOC = "AA40" | | VCCAUX_IO = HIGH ; -NET "ddr3_dm[7]" LOC = "AD42" | | VCCAUX_IO = HIGH ; -NET "ddr3_dq[0]" LOC = "H41" | | VCCAUX_IO = HIGH ; -NET "ddr3_dq[10]" LOC = "A40" | | VCCAUX_IO = HIGH ; -NET "ddr3_dq[11]" LOC = "F42" | | VCCAUX_IO = HIGH ; -NET "ddr3_dq[12]" LOC = "C40" | | VCCAUX_IO = HIGH ; -NET "ddr3_dq[13]" LOC = "E40" | | VCCAUX_IO = HIGH ; -NET "ddr3_dq[14]" LOC = "B42" | | VCCAUX_IO = HIGH ; -NET "ddr3_dq[15]" LOC = "D40" | | VCCAUX_IO = HIGH ; -NET "ddr3_dq[16]" LOC = "AJ38" | | VCCAUX_IO = HIGH ; -NET "ddr3_dq[17]" LOC = "AF39" | | VCCAUX_IO = HIGH ; -NET "ddr3_dq[18]" LOC = "AH38" | | VCCAUX_IO = HIGH ; -NET "ddr3_dq[19]" LOC = "AF42" | | VCCAUX_IO = HIGH ; -NET "ddr3_dq[1]" LOC = "H39" | | VCCAUX_IO = HIGH ; -NET "ddr3_dq[20]" LOC = "AG38" | | VCCAUX_IO = HIGH ; -NET "ddr3_dq[21]" LOC = "AF40" | | VCCAUX_IO = HIGH ; -NET "ddr3_dq[22]" LOC = "AK38" | | VCCAUX_IO = HIGH ; -NET "ddr3_dq[23]" LOC = "AF41" | | VCCAUX_IO = HIGH ; -NET "ddr3_dq[24]" LOC = "AH41" | | VCCAUX_IO = HIGH ; -NET "ddr3_dq[25]" LOC = "AJ41" | | VCCAUX_IO = HIGH ; -NET "ddr3_dq[26]" LOC = "AH40" | | VCCAUX_IO = HIGH ; -NET "ddr3_dq[27]" LOC = "AL39" | | VCCAUX_IO = HIGH ; -NET "ddr3_dq[28]" LOC = "AK42" | | VCCAUX_IO = HIGH ; -NET "ddr3_dq[29]" LOC = "AK39" | | VCCAUX_IO = HIGH ; -NET "ddr3_dq[2]" LOC = "J41" | | VCCAUX_IO = HIGH ; -NET "ddr3_dq[30]" LOC = "AJ42" | | VCCAUX_IO = HIGH ; -NET "ddr3_dq[31]" LOC = "AJ40" | | VCCAUX_IO = HIGH ; -NET "ddr3_dq[32]" LOC = "L40" | | VCCAUX_IO = HIGH ; -NET "ddr3_dq[33]" LOC = "M42" | | VCCAUX_IO = HIGH ; -NET "ddr3_dq[34]" LOC = "K37" | | VCCAUX_IO = HIGH ; -NET "ddr3_dq[35]" LOC = "L42" | | VCCAUX_IO = HIGH ; -NET "ddr3_dq[36]" LOC = "L39" | | VCCAUX_IO = HIGH ; -NET "ddr3_dq[37]" LOC = "K38" | | VCCAUX_IO = HIGH ; -NET "ddr3_dq[38]" LOC = "M36" | | VCCAUX_IO = HIGH ; -NET "ddr3_dq[39]" LOC = "M41" | | VCCAUX_IO = HIGH ; -NET "ddr3_dq[3]" LOC = "F40" | | VCCAUX_IO = HIGH ; -NET "ddr3_dq[40]" LOC = "M39" | | VCCAUX_IO = HIGH ; -NET "ddr3_dq[41]" LOC = "P41" | | VCCAUX_IO = HIGH ; -NET "ddr3_dq[42]" LOC = "M38" | | VCCAUX_IO = HIGH ; -NET "ddr3_dq[43]" LOC = "N38" | | VCCAUX_IO = HIGH ; -NET "ddr3_dq[44]" LOC = "N40" | | VCCAUX_IO = HIGH ; -NET "ddr3_dq[45]" LOC = "N39" | | VCCAUX_IO = HIGH ; -NET "ddr3_dq[46]" LOC = "M37" | | VCCAUX_IO = HIGH ; -NET "ddr3_dq[47]" LOC = "P40" | | VCCAUX_IO = HIGH ; -NET "ddr3_dq[48]" LOC = "AB42" | | VCCAUX_IO = HIGH ; -NET "ddr3_dq[49]" LOC = "AA42" | | VCCAUX_IO = HIGH ; -NET "ddr3_dq[4]" LOC = "K39" | | VCCAUX_IO = HIGH ; -NET "ddr3_dq[50]" LOC = "AB39" | | VCCAUX_IO = HIGH ; -NET "ddr3_dq[51]" LOC = "Y40" | | VCCAUX_IO = HIGH ; -NET "ddr3_dq[52]" LOC = "AB41" | | VCCAUX_IO = HIGH ; -NET "ddr3_dq[53]" LOC = "W40" | | VCCAUX_IO = HIGH ; -NET "ddr3_dq[54]" LOC = "AB38" | | VCCAUX_IO = HIGH ; -NET "ddr3_dq[55]" LOC = "Y42" | | VCCAUX_IO = HIGH ; -NET "ddr3_dq[56]" LOC = "AC40" | | VCCAUX_IO = HIGH ; -NET "ddr3_dq[57]" LOC = "AE42" | | VCCAUX_IO = HIGH ; -NET "ddr3_dq[58]" LOC = "AC38" | | VCCAUX_IO = HIGH ; -NET "ddr3_dq[59]" LOC = "AE39" | | VCCAUX_IO = HIGH ; -NET "ddr3_dq[5]" LOC = "G39" | | VCCAUX_IO = HIGH ; -NET "ddr3_dq[60]" LOC = "AC41" | | VCCAUX_IO = HIGH ; -NET "ddr3_dq[61]" LOC = "AE40" | | VCCAUX_IO = HIGH ; -NET "ddr3_dq[62]" LOC = "AC39" | | VCCAUX_IO = HIGH ; -NET "ddr3_dq[63]" LOC = "AD40" | | VCCAUX_IO = HIGH ; -NET "ddr3_dq[6]" LOC = "J40" | | VCCAUX_IO = HIGH ; -NET "ddr3_dq[7]" LOC = "H40" | | VCCAUX_IO = HIGH ; -NET "ddr3_dq[8]" LOC = "A41" | | VCCAUX_IO = HIGH ; -NET "ddr3_dq[9]" LOC = "E42" | | VCCAUX_IO = HIGH ; -NET "ddr3_dqs_n[0]" LOC = "G42" | | VCCAUX_IO = HIGH ; -NET "ddr3_dqs_n[1]" LOC = "D42" | | VCCAUX_IO = HIGH ; -NET "ddr3_dqs_n[2]" LOC = "AH39" | | VCCAUX_IO = HIGH ; -NET "ddr3_dqs_n[3]" LOC = "AL42" | | VCCAUX_IO = HIGH ; -NET "ddr3_dqs_n[4]" LOC = "J42" | | VCCAUX_IO = HIGH ; -NET "ddr3_dqs_n[5]" LOC = "P42" | | VCCAUX_IO = HIGH ; -NET "ddr3_dqs_n[6]" LOC = "AA39" | | VCCAUX_IO = HIGH ; -NET "ddr3_dqs_n[7]" LOC = "AE38" | | VCCAUX_IO = HIGH ; -NET "ddr3_dqs_p[0]" LOC = "G41" | | VCCAUX_IO = HIGH ; -NET "ddr3_dqs_p[1]" LOC = "D41" | | VCCAUX_IO = HIGH ; -NET "ddr3_dqs_p[2]" LOC = "AG39" | | VCCAUX_IO = HIGH ; -NET "ddr3_dqs_p[3]" LOC = "AL41" | | VCCAUX_IO = HIGH ; -NET "ddr3_dqs_p[4]" LOC = "K42" | | VCCAUX_IO = HIGH ; -NET "ddr3_dqs_p[5]" LOC = "R42" | | VCCAUX_IO = HIGH ; -NET "ddr3_dqs_p[6]" LOC = "Y39" | | VCCAUX_IO = HIGH ; -NET "ddr3_dqs_p[7]" LOC = "AD38" | | VCCAUX_IO = HIGH ; -NET "ddr3_odt[0]" LOC = "R37" | | VCCAUX_IO = HIGH ; -NET "ddr3_ras_n" LOC = "P36" | | VCCAUX_IO = HIGH ; -NET "ddr3_reset_n" LOC = "W38" | | VCCAUX_IO = HIGH ; -NET "ddr3_we_n" LOC = "P38" | | VCCAUX_IO = HIGH ; diff --git a/ddr3_general_design.srcs/constrs_1/ddr3_1.ucf b/ddr3_general_design.srcs/constrs_1/ddr3_1.ucf deleted file mode 100644 index 093ac78..0000000 --- a/ddr3_general_design.srcs/constrs_1/ddr3_1.ucf +++ /dev/null @@ -1,115 +0,0 @@ -NET "ddr3_addr[0]" LOC = "A35" | | VCCAUX_IO = HIGH ; -NET "ddr3_addr[10]" LOC = "J37" | | VCCAUX_IO = HIGH ; -NET "ddr3_addr[11]" LOC = "D32" | | VCCAUX_IO = HIGH ; -NET "ddr3_addr[12]" LOC = "F35" | | VCCAUX_IO = HIGH ; -NET "ddr3_addr[13]" LOC = "G38" | | VCCAUX_IO = HIGH ; -NET "ddr3_addr[14]" LOC = "B32" | | VCCAUX_IO = HIGH ; -NET "ddr3_addr[1]" LOC = "E32" | | VCCAUX_IO = HIGH ; -NET "ddr3_addr[2]" LOC = "B36" | | VCCAUX_IO = HIGH ; -NET "ddr3_addr[3]" LOC = "C39" | | VCCAUX_IO = HIGH ; -NET "ddr3_addr[4]" LOC = "G33" | | VCCAUX_IO = HIGH ; -NET "ddr3_addr[5]" LOC = "A39" | | VCCAUX_IO = HIGH ; -NET "ddr3_addr[6]" LOC = "G36" | | VCCAUX_IO = HIGH ; -NET "ddr3_addr[7]" LOC = "B39" | | VCCAUX_IO = HIGH ; -NET "ddr3_addr[8]" LOC = "H38" | | VCCAUX_IO = HIGH ; -NET "ddr3_addr[9]" LOC = "A36" | | VCCAUX_IO = HIGH ; -NET "ddr3_ba[0]" LOC = "C38" | | VCCAUX_IO = HIGH ; -NET "ddr3_ba[1]" LOC = "J36" | | VCCAUX_IO = HIGH ; -NET "ddr3_ba[2]" LOC = "B34" | | VCCAUX_IO = HIGH ; -NET "ddr3_cas_n" LOC = "B33" | | VCCAUX_IO = HIGH ; -NET "ddr3_ck_n[0]" LOC = "D36" | | VCCAUX_IO = HIGH ; -NET "ddr3_ck_p[0]" LOC = "D35" | | VCCAUX_IO = HIGH ; -NET "ddr3_cke[0]" LOC = "J38" | | VCCAUX_IO = HIGH ; -NET "ddr3_cs_n[0]" LOC = "A37" | | VCCAUX_IO = HIGH ; -NET "ddr3_dm[0]" LOC = "K27" | | VCCAUX_IO = HIGH ; -NET "ddr3_dm[1]" LOC = "H23" | | VCCAUX_IO = HIGH ; -NET "ddr3_dm[2]" LOC = "N29" | | VCCAUX_IO = HIGH ; -NET "ddr3_dm[3]" LOC = "V31" | | VCCAUX_IO = HIGH ; -NET "ddr3_dm[4]" LOC = "K23" | | VCCAUX_IO = HIGH ; -NET "ddr3_dm[5]" LOC = "M27" | | VCCAUX_IO = HIGH ; -NET "ddr3_dm[6]" LOC = "J32" | | VCCAUX_IO = HIGH ; -NET "ddr3_dm[7]" LOC = "H31" | | VCCAUX_IO = HIGH ; -NET "ddr3_dq[0]" LOC = "G28" | | VCCAUX_IO = HIGH ; -NET "ddr3_dq[10]" LOC = "J21" | | VCCAUX_IO = HIGH ; -NET "ddr3_dq[11]" LOC = "G27" | | VCCAUX_IO = HIGH ; -NET "ddr3_dq[12]" LOC = "G22" | | VCCAUX_IO = HIGH ; -NET "ddr3_dq[13]" LOC = "G26" | | VCCAUX_IO = HIGH ; -NET "ddr3_dq[14]" LOC = "G21" | | VCCAUX_IO = HIGH ; -NET "ddr3_dq[15]" LOC = "H24" | | VCCAUX_IO = HIGH ; -NET "ddr3_dq[16]" LOC = "M31" | | VCCAUX_IO = HIGH ; -NET "ddr3_dq[17]" LOC = "N28" | | VCCAUX_IO = HIGH ; -NET "ddr3_dq[18]" LOC = "P30" | | VCCAUX_IO = HIGH ; -NET "ddr3_dq[19]" LOC = "P28" | | VCCAUX_IO = HIGH ; -NET "ddr3_dq[1]" LOC = "K25" | | VCCAUX_IO = HIGH ; -NET "ddr3_dq[20]" LOC = "N31" | | VCCAUX_IO = HIGH ; -NET "ddr3_dq[21]" LOC = "R28" | | VCCAUX_IO = HIGH ; -NET "ddr3_dq[22]" LOC = "R30" | | VCCAUX_IO = HIGH ; -NET "ddr3_dq[23]" LOC = "N30" | | VCCAUX_IO = HIGH ; -NET "ddr3_dq[24]" LOC = "U29" | | VCCAUX_IO = HIGH ; -NET "ddr3_dq[25]" LOC = "W31" | | VCCAUX_IO = HIGH ; -NET "ddr3_dq[26]" LOC = "V29" | | VCCAUX_IO = HIGH ; -NET "ddr3_dq[27]" LOC = "Y29" | | VCCAUX_IO = HIGH ; -NET "ddr3_dq[28]" LOC = "U31" | | VCCAUX_IO = HIGH ; -NET "ddr3_dq[29]" LOC = "Y30" | | VCCAUX_IO = HIGH ; -NET "ddr3_dq[2]" LOC = "G29" | | VCCAUX_IO = HIGH ; -NET "ddr3_dq[30]" LOC = "V30" | | VCCAUX_IO = HIGH ; -NET "ddr3_dq[31]" LOC = "W30" | | VCCAUX_IO = HIGH ; -NET "ddr3_dq[32]" LOC = "M24" | | VCCAUX_IO = HIGH ; -NET "ddr3_dq[33]" LOC = "J22" | | VCCAUX_IO = HIGH ; -NET "ddr3_dq[34]" LOC = "L25" | | VCCAUX_IO = HIGH ; -NET "ddr3_dq[35]" LOC = "K22" | | VCCAUX_IO = HIGH ; -NET "ddr3_dq[36]" LOC = "L24" | | VCCAUX_IO = HIGH ; -NET "ddr3_dq[37]" LOC = "M21" | | VCCAUX_IO = HIGH ; -NET "ddr3_dq[38]" LOC = "L26" | | VCCAUX_IO = HIGH ; -NET "ddr3_dq[39]" LOC = "J23" | | VCCAUX_IO = HIGH ; -NET "ddr3_dq[3]" LOC = "K24" | | VCCAUX_IO = HIGH ; -NET "ddr3_dq[40]" LOC = "N25" | | VCCAUX_IO = HIGH ; -NET "ddr3_dq[41]" LOC = "N26" | | VCCAUX_IO = HIGH ; -NET "ddr3_dq[42]" LOC = "P21" | | VCCAUX_IO = HIGH ; -NET "ddr3_dq[43]" LOC = "L27" | | VCCAUX_IO = HIGH ; -NET "ddr3_dq[44]" LOC = "N24" | | VCCAUX_IO = HIGH ; -NET "ddr3_dq[45]" LOC = "P26" | | VCCAUX_IO = HIGH ; -NET "ddr3_dq[46]" LOC = "N23" | | VCCAUX_IO = HIGH ; -NET "ddr3_dq[47]" LOC = "P25" | | VCCAUX_IO = HIGH ; -NET "ddr3_dq[48]" LOC = "L34" | | VCCAUX_IO = HIGH ; -NET "ddr3_dq[49]" LOC = "J35" | | VCCAUX_IO = HIGH ; -NET "ddr3_dq[4]" LOC = "K28" | | VCCAUX_IO = HIGH ; -NET "ddr3_dq[50]" LOC = "M34" | | VCCAUX_IO = HIGH ; -NET "ddr3_dq[51]" LOC = "J33" | | VCCAUX_IO = HIGH ; -NET "ddr3_dq[52]" LOC = "L35" | | VCCAUX_IO = HIGH ; -NET "ddr3_dq[53]" LOC = "H34" | | VCCAUX_IO = HIGH ; -NET "ddr3_dq[54]" LOC = "M33" | | VCCAUX_IO = HIGH ; -NET "ddr3_dq[55]" LOC = "K35" | | VCCAUX_IO = HIGH ; -NET "ddr3_dq[56]" LOC = "J30" | | VCCAUX_IO = HIGH ; -NET "ddr3_dq[57]" LOC = "J31" | | VCCAUX_IO = HIGH ; -NET "ddr3_dq[58]" LOC = "K30" | | VCCAUX_IO = HIGH ; -NET "ddr3_dq[59]" LOC = "L32" | | VCCAUX_IO = HIGH ; -NET "ddr3_dq[5]" LOC = "J25" | | VCCAUX_IO = HIGH ; -NET "ddr3_dq[60]" LOC = "H30" | | VCCAUX_IO = HIGH ; -NET "ddr3_dq[61]" LOC = "M32" | | VCCAUX_IO = HIGH ; -NET "ddr3_dq[62]" LOC = "K29" | | VCCAUX_IO = HIGH ; -NET "ddr3_dq[63]" LOC = "L31" | | VCCAUX_IO = HIGH ; -NET "ddr3_dq[6]" LOC = "J28" | | VCCAUX_IO = HIGH ; -NET "ddr3_dq[7]" LOC = "J27" | | VCCAUX_IO = HIGH ; -NET "ddr3_dq[8]" LOC = "H21" | | VCCAUX_IO = HIGH ; -NET "ddr3_dq[9]" LOC = "G24" | | VCCAUX_IO = HIGH ; -NET "ddr3_dqs_n[0]" LOC = "H29" | | VCCAUX_IO = HIGH ; -NET "ddr3_dqs_n[1]" LOC = "H26" | | VCCAUX_IO = HIGH ; -NET "ddr3_dqs_n[2]" LOC = "M29" | | VCCAUX_IO = HIGH ; -NET "ddr3_dqs_n[3]" LOC = "T30" | | VCCAUX_IO = HIGH ; -NET "ddr3_dqs_n[4]" LOC = "L22" | | VCCAUX_IO = HIGH ; -NET "ddr3_dqs_n[5]" LOC = "P23" | | VCCAUX_IO = HIGH ; -NET "ddr3_dqs_n[6]" LOC = "K34" | | VCCAUX_IO = HIGH ; -NET "ddr3_dqs_n[7]" LOC = "L30" | | VCCAUX_IO = HIGH ; -NET "ddr3_dqs_p[0]" LOC = "H28" | | VCCAUX_IO = HIGH ; -NET "ddr3_dqs_p[1]" LOC = "H25" | | VCCAUX_IO = HIGH ; -NET "ddr3_dqs_p[2]" LOC = "M28" | | VCCAUX_IO = HIGH ; -NET "ddr3_dqs_p[3]" LOC = "T29" | | VCCAUX_IO = HIGH ; -NET "ddr3_dqs_p[4]" LOC = "M22" | | VCCAUX_IO = HIGH ; -NET "ddr3_dqs_p[5]" LOC = "P22" | | VCCAUX_IO = HIGH ; -NET "ddr3_dqs_p[6]" LOC = "K33" | | VCCAUX_IO = HIGH ; -NET "ddr3_dqs_p[7]" LOC = "L29" | | VCCAUX_IO = HIGH ; -NET "ddr3_odt[0]" LOC = "E39" | | VCCAUX_IO = HIGH ; -NET "ddr3_ras_n" LOC = "E33" | | VCCAUX_IO = HIGH ; -NET "ddr3_reset_n" LOC = "B37" | | VCCAUX_IO = HIGH ; -NET "ddr3_we_n" LOC = "A34" | | VCCAUX_IO = HIGH ; diff --git a/ddr3_general_design.srcs/sources_1/ip/ddr3_ctrl_0/ddr3_ctrl_0.xci b/ddr3_general_design.srcs/sources_1/ip/ddr3_ctrl_0/ddr3_ctrl_0.xci deleted file mode 100644 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3 - TRUE - . - - . - 2018.3 - OUT_OF_CONTEXT - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - diff --git a/ddr3_general_design.srcs/sources_1/ip/fifo_wr_mask_data/fifo_wr_mask_data.xci b/ddr3_general_design.srcs/sources_1/ip/fifo_wr_mask_data/fifo_wr_mask_data.xci deleted file mode 100644 index e3b1442..0000000 --- a/ddr3_general_design.srcs/sources_1/ip/fifo_wr_mask_data/fifo_wr_mask_data.xci +++ /dev/null @@ -1,564 +0,0 @@ - - - xilinx.com - xci - unknown - 1.0 - - - fifo_wr_mask_data - - - - - - 100000000 - 0 - 0.000 - - - 100000000 - 0 - 0.000 - 1 - 0 - 0 - 0 - - 1 - 100000000 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 1 - 1 - 1 - 1 - 1 - 0.000 - AXI4LITE - READ_WRITE - 0 - 0 - 0 - 0 - 0 - - 100000000 - 0 - 0 - 0 - 0 - 0 - undef - 0.000 - 0 - 0 - 0 - 0 - - - - 100000000 - 0 - 0.000 - - 100000000 - 0 - 0.000 - 0 - 1 - 0 - 0 - 0 - - 1 - 100000000 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 1 - 1 - 1 - 1 - 1 - 0.000 - AXI4LITE - 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- 16 - 1024 - 16 - 1 - 6 - 10 - 4 - 10 - 4 - 10 - 4 - 1 - 32 - 0 - 0 - false - false - false - 0 - 0 - Slave_Interface_Clock_Enable - Common_Clock - fifo_wr_mask_data - 64 - false - 6 - false - false - 0 - 2 - 1022 - 1022 - 1022 - 1022 - 1022 - 1022 - 3 - false - false - false - false - false - false - false - false - false - Hard_ECC - false - false - false - false - false - false - true - false - false - true - Data_FIFO - Data_FIFO - Data_FIFO - Data_FIFO - Data_FIFO - Data_FIFO - Common_Clock_Block_RAM - Common_Clock_Block_RAM - Common_Clock_Block_RAM - Common_Clock_Block_RAM - Common_Clock_Block_RAM - Common_Clock_Block_RAM - Common_Clock_Block_RAM - 0 - 62 - 1023 - 1023 - 1023 - 1023 - 1023 - 1023 - 61 - false - false - false - 0 - Native - false - false - false - false - false - false - false - false - false - false - false - false - false - false - 576 - 64 - 1024 - 16 - 1024 - 16 - 1024 - 16 - false - 576 - 64 - Embedded_Reg - false - false - Active_High - Active_High - AXI4 - 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TRUE - IP_Flow - 3 - TRUE - . - - . - 2018.3 - OUT_OF_CONTEXT - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - diff --git a/ddr3_general_design.srcs/sources_1/new/ddr3_rw_in_ctrl.v b/ddr3_general_design.srcs/sources_1/new/ddr3_rw_in_ctrl.v deleted file mode 100644 index 3dd3d15..0000000 --- a/ddr3_general_design.srcs/sources_1/new/ddr3_rw_in_ctrl.v +++ /dev/null @@ -1,119 +0,0 @@ -`timescale 1ns / 1ps -////////////////////////////////////////////////////////////////////////////////// -// Company: -// Engineer: -// -// Create Date: 2025/01/13 19:28:48 -// Design Name: -// Module Name: ddr3_rw_in_ctrl -// Project Name: -// Target Devices: -// Tool Versions: -// Description: -// -// Dependencies: -// -// Revision: -// Revision 0.01 - File Created -// Additional Comments: -// -////////////////////////////////////////////////////////////////////////////////// - - -module ddr3_rw_in_ctrl( - input ui_clk_i, - input ui_rst_i, - - input app_rdy_i, - - input fifo_rw_in_empty_i, - output fifo_rw_in_re_o, - output app_en_1d_o - ); - - localparam [2:0] - S_IDLE = 3'b001, - S_WAIT = 3'b100, - S_ACC = 3'b100; - - reg [2:0] c_state; - reg [2:0] n_state; - - reg fifo_rw_in_re; - reg fifo_rw_in_re_1d; - reg app_en; - - assign fifo_rw_in_re_o = fifo_rw_in_re; - assign app_en_1d_o = app_en; - - always @(posedge ui_clk_i or negedge ui_rst_i) begin - if(ui_rst_i) begin - c_state <= S_IDLE; - end else begin - c_state <= n_state; - end - end - - always @(*) begin - fifo_rw_in_re = 1'b0; - app_en = 1'b0; - n_state = S_IDLE; - case(c_state) - S_IDLE: begin - if(!fifo_rw_in_empty_i) begin - fifo_rw_in_re = 1'b1; - n_state = S_WAIT; - end - else begin - n_state = S_IDLE; - end - end - S_WAIT: begin - if(!fifo_rw_in_empty_i) begin - fifo_rw_in_re = 1'b1; - end - n_state = S_ACC; - end - S_ACC: begin - if(app_rdy_i) begin - app_en = 1'b1; - end - - casex({app_rdy_i, !fifo_rw_in_empty_i, fifo_rw_in_re_1d}) - 3'b0xx: begin - n_state = S_ACC; - end - 3'b100: begin - n_state = S_IDLE; - end - 3'b101: begin - n_state = S_ACC; - end - 3'b110: begin - fifo_rw_in_re = 1'b1; - n_state = S_WAIT; - end - 3'b111: begin - fifo_rw_in_re = 1'b1; - n_state = S_ACC; - end - default: begin - n_state = S_IDLE; - end - endcase - end - default: begin - n_state = S_IDLE; - end - endcase - end - - always @(posedge ui_clk_i or negedge ui_rst_i) begin - if(ui_rst_i) begin - fifo_rw_in_re_1d <= 1'b0; - end else begin - fifo_rw_in_re_1d <= fifo_rw_in_re; - end - end - -endmodule diff --git a/ddr3_general_design.srcs/sources_1/new/ddr3_rw_module.v b/ddr3_general_design.srcs/sources_1/new/ddr3_rw_module.v deleted file mode 100644 index c7404cb..0000000 --- a/ddr3_general_design.srcs/sources_1/new/ddr3_rw_module.v +++ /dev/null @@ -1,279 +0,0 @@ -`timescale 1ns / 1ps -////////////////////////////////////////////////////////////////////////////////// -// Company: -// Engineer: -// -// Create Date: 2025/01/13 18:26:30 -// Design Name: -// Module Name: ddr3_rw_module -// Project Name: -// Target Devices: -// Tool Versions: -// Description: -// -// Dependencies: -// -// Revision: -// Revision 0.01 - File Created -// Additional Comments: -// -////////////////////////////////////////////////////////////////////////////////// - - -module ddr3_rw_module( - // Clock and reset signals - input sys_clk_i, - input sys_rst_i, - input ui_clk_i, - input ui_rst_i, - - // Read & Write interface signals - input ddr3_rw_en_i, - input [ 2:0] ddr3_rw_cmd_i, - input [ 28:0] ddr3_rw_addr_i, - input [ 63:0] ddr3_wr_mask_i, - input [511:0] ddr3_wr_data_i, - input [ 34:0] ddr3_rd_info_i, - input ddr3_rd_rdy_i, - - output ddr3_rw_full_o, - output [ 28:0] ddr3_rd_addr_o, - output [511:0] ddr3_rd_data_o, - output [ 5:0] ddr3_rd_info_o, - output ddr3_rd_valid_o, - output ddr3_rd_full_o, - output ddr3_rd_empty_o, - - // User interface signals - output [ 28:0] app_addr_o, - output [ 2:0] app_cmd_o, - output app_en_o, - output [511:0] app_wdf_data_o, - output app_wdf_end_o, - output [ 63:0] app_wdf_mask_o, - output app_wdf_wren_o, - input [511:0] app_rd_data_i, - input app_rd_data_end_i, - input app_rd_data_valid_i, - input app_rdy_i, - input app_wdf_rdy_i - ); - - reg fifo_rw_in_re_1d; - reg [ 2:0] fifo_rw_cmd_dout_1d; - reg [ 28:0] fifo_rw_addr_dout_1d; - reg fifo_rw_out_re; - - wire fifo_rw_in_re; - wire app_en_1d; - wire app_rdy; - wire fifo_rw_in_empty; - - wire [ 2:0] fifo_rw_cmd_din; - wire fifo_rw_cmd_we; - wire fifo_rw_cmd_full; - wire [ 2:0] fifo_rw_cmd_dout; - wire fifo_rw_cmd_re; - wire fifo_rw_cmd_empty; - - wire [ 28:0] fifo_rw_addr_in_din; - wire fifo_rw_addr_in_we; - wire fifo_rw_addr_in_full; - wire [ 28:0] fifo_rw_addr_in_dout; - wire fifo_rw_addr_in_re; - wire fifo_rw_addr_in_empty; - - wire [575:0] fifo_wr_mask_data_din; - wire fifo_wr_mask_data_we; - wire fifo_wr_mask_data_full; - wire [575:0] fifo_wr_mask_data_dout; - wire fifo_wr_mask_data_re; - wire fifo_wr_mask_data_empty; - - wire fifo_rw_out_empty; - //wire fifo_rw_out_re; - wire fifo_rw_out_valid; - - wire [511:0] fifo_rd_data_din; - wire fifo_rd_data_we; - wire fifo_rd_data_full; - wire [511:0] fifo_rd_data_dout; - wire fifo_rd_data_re; - wire fifo_rd_data_empty; - wire fifo_rd_data_valid; - - wire [ 28:0] fifo_rw_addr_out_din; - wire fifo_rw_addr_out_we; - wire fifo_rw_addr_out_full; - wire [ 28:0] fifo_rw_addr_out_dout; - wire fifo_rw_addr_out_re; - wire fifo_rw_addr_out_empty; - wire fifo_rw_addr_out_valid; - - wire [ 5:0] fifo_rd_info_din; - wire fifo_rd_info_we; - wire fifo_rd_info_full; - wire [ 5:0] fifo_rd_info_dout; - wire fifo_rd_info_re; - wire fifo_rd_info_empty; - wire fifo_rd_info_valid; - - assign ddr3_rw_full_o = fifo_rw_cmd_full || fifo_rw_addr_in_full || fifo_wr_mask_data_full || fifo_rd_info_full; - assign ddr3_rd_addr_o = fifo_rw_addr_out_dout; - assign ddr3_rd_data_o = fifo_rd_data_dout; - assign ddr3_rd_info_o = fifo_rd_info_dout; - assign ddr3_rd_valid_o = fifo_rd_data_valid; - assign ddr3_rd_full_o = fifo_rd_data_full || fifo_rw_addr_out_full || fifo_rd_info_full; - assign ddr3_rd_empty_o = fifo_rd_data_empty && fifo_rd_info_empty && fifo_rw_addr_out_empty; - - assign app_addr_o = fifo_rw_addr_dout_1d; - assign app_cmd_o = fifo_rw_cmd_dout_1d; - assign app_en_o = app_en_1d; - assign app_wdf_data_o = fifo_wr_mask_data_dout[511:0]; - assign app_wdf_end_o = app_en_1d && (fifo_rw_cmd_dout_1d == 3'b000); - assign app_wdf_mask_o = fifo_wr_mask_data_dout[575:511]; - assign app_wdf_wren_o = app_en_1d && (fifo_rw_cmd_dout_1d == 3'b000); - assign fifo_rd_out_valid_o = fifo_rd_data_valid && fifo_rw_addr_out_valid && fifo_rd_info_valid ; - - assign fifo_rw_cmd_we = ddr3_rw_en_i; - assign fifo_rw_cmd_din = ddr3_rw_cmd_i; - assign fifo_rw_addr_in_we = ddr3_rw_en_i; - assign fifo_rw_addr_in_din = ddr3_rw_addr_i; - assign fifo_wr_mask_data_we = ddr3_rw_en_i && (ddr3_rw_cmd_i == 3'b000); - assign fifo_wr_mask_data_din = {ddr3_wr_mask_i, ddr3_wr_data_i}; - assign fifo_rd_info_we = ddr3_rw_en_i && (ddr3_rw_cmd_i == 3'b001); - assign fifo_rd_info_din = ddr3_rd_info_i; - - assign app_rdy = app_rdy_i && app_wdf_rdy_i; - assign fifo_rw_in_empty = fifo_rw_cmd_empty && fifo_rw_addr_in_empty; - assign fifo_rw_cmd_re = fifo_rw_in_re; - assign fifo_rw_addr_in_re = fifo_rw_in_re; - assign fifo_wr_mask_data_re = fifo_rw_in_re_1d && (fifo_rw_cmd_dout == 3'b000); - - assign fifo_rd_data_we = app_rd_data_valid_i; - assign fifo_rd_data_din = app_rd_data_i; - - assign fifo_rd_data_re = fifo_rw_out_re; - assign fifo_rd_info_re = fifo_rw_out_re; - - always @(posedge ui_clk_i or negedge ui_rst_i) begin - if(ui_rst_i) begin - fifo_rw_in_re_1d <= 1'b0; - end else begin - fifo_rw_in_re_1d <= fifo_rw_in_re; - end - end - - always @(posedge ui_clk_i or negedge ui_rst_i) begin - if(ui_rst_i) begin - fifo_rw_cmd_dout_1d <= 3'b000; - fifo_rw_addr_dout_1d <= 29'b0; - end - else begin - if(fifo_rw_in_re_1d) begin - fifo_rw_cmd_dout_1d <= fifo_rw_cmd_dout; - end - else begin - fifo_rw_cmd_dout_1d <= fifo_rw_cmd_dout_1d; - end - - if(fifo_rw_in_re_1d) begin - fifo_rw_addr_dout_1d <= fifo_rw_addr_in_dout; - end - else begin - fifo_rw_addr_dout_1d <= fifo_rw_addr_dout_1d; - end - end - end - - // Instantiate the module - ddr3_rw_in_ctrl ddr3_rw_in_ctrl_inst( - .ui_clk_i (ui_clk_i), - .ui_rst_i (ui_rst_i), - .app_rdy_i (app_rdy), - .fifo_rw_in_empty_i (fifo_rw_in_empty), - .fifo_rw_in_re_o (fifo_rw_in_re), - .app_en_1d_o (app_en_1d) - ); - - // Instantiate the module - fifo_rw_cmd fifo_rw_cmd_inst ( - .wr_clk (sys_clk_i), - .rd_clk (ui_clk_i), - .rst (sys_rst_i), - .din (fifo_rw_cmd_din), - .wr_en (fifo_rw_cmd_we), - .full (fifo_rw_cmd_full), - .dout (fifo_rw_cmd_dout), - .rd_en (fifo_rw_cmd_re), - .empty (fifo_rw_cmd_empty) - ); - - // Instantiate the module - fifo_rw_addr fifo_rw_rw_addr_in_inst ( - .wr_clk (sys_clk_i), - .rd_clk (ui_clk_i), - .rst (sys_rst_i), - .din (fifo_rw_addr_in_din), - .wr_en (fifo_rw_addr_in_we), - .full (fifo_rw_addr_in_full), - .dout (fifo_rw_addr_in_dout), - .rd_en (fifo_rw_addr_in_re), - .empty (fifo_rw_addr_in_empty), - .valid () - ); - - - // Instantiate the module - fifo_wr_mask_data fifo_wr_mask_data_inst ( - .wr_clk (sys_clk_i), - .rd_clk (ui_clk_i), - .rst (sys_rst_i), - .din (fifo_wr_mask_data_din), - .wr_en (fifo_wr_mask_data_we), - .full (fifo_wr_mask_data_full), - .dout (fifo_wr_mask_data_dout), - .rd_en (fifo_wr_mask_data_re), - .empty (fifo_wr_mask_data_empty) - ); - - // Instantiate the module - fifo_rd_data fifo_rd_data_inst ( - .wr_clk (ui_clk_i), - .rd_clk (sys_clk_i), - .rst (ui_rst_i), - .din (fifo_rd_data_din), - .wr_en (fifo_rd_data_we), - .full (fifo_rd_data_full), - .dout (fifo_rd_data_dout), - .rd_en (fifo_rd_data_re), - .empty (fifo_rd_data_empty), - .valid (fifo_rd_data_valid) - ); - - fifo_rw_addr fifo_rw_rw_addr_out_inst( - .wr_clk (ui_clk_i), - .rd_clk (sys_clk_i), - .rst (ui_rst_i), - .din (fifo_rw_addr_out_din), - .wr_en (fifo_rw_addr_out_we), - .full (fifo_rw_addr_out_full), - .dout (fifo_rw_addr_out_dout), - .rd_en (fifo_rw_addr_out_re), - .empty (fifo_rw_addr_out_empty), - .valid (fifo_rw_addr_out_valid) - ); - - // Instantiate the module - fifo_rd_info fifo_rd_info_inst ( - .wr_clk (sys_clk_i), - .rst (sys_rst_i), - .din (fifo_rd_info_din), - .wr_en (fifo_rd_info_we), - .full (fifo_rd_info_full), - .dout (fifo_rd_info_dout), - .rd_en (fifo_rd_info_re), - .empty (fifo_rd_info_empty), - .valid (fifo_rd_info_valid) - ); -endmodule diff --git a/ddr3_general_design.srcs/sources_1/new/ddr3_rw_out_ctrl.v b/ddr3_general_design.srcs/sources_1/new/ddr3_rw_out_ctrl.v deleted file mode 100644 index 025e067..0000000 --- a/ddr3_general_design.srcs/sources_1/new/ddr3_rw_out_ctrl.v +++ /dev/null @@ -1,26 +0,0 @@ -`timescale 1ns / 1ps -////////////////////////////////////////////////////////////////////////////////// -// Company: -// Engineer: -// -// Create Date: 2025/01/13 18:31:58 -// Design Name: -// Module Name: ddr3_rw_out_ctrl -// Project Name: -// Target Devices: -// Tool Versions: -// Description: -// -// Dependencies: -// -// Revision: -// Revision 0.01 - File Created -// Additional Comments: -// -////////////////////////////////////////////////////////////////////////////////// - - -module ddr3_rw_out_ctrl( - - ); -endmodule diff --git a/ddr3_general_design.srcs/sources_1/new/ddr3_top.v b/ddr3_general_design.srcs/sources_1/new/ddr3_top.v deleted file mode 100644 index 30bace6..0000000 --- a/ddr3_general_design.srcs/sources_1/new/ddr3_top.v +++ /dev/null @@ -1,242 +0,0 @@ -`timescale 1ns / 1ps -////////////////////////////////////////////////////////////////////////////////// -// Company: -// Engineer: -// -// Create Date: 2025/01/13 18:25:16 -// Design Name: -// Module Name: ddr3_top -// Project Name: -// Target Devices: -// Tool Versions: -// Description: -// -// Dependencies: -// -// Revision: -// Revision 0.01 - File Created -// Additional Comments: -// -////////////////////////////////////////////////////////////////////////////////// - -module ddr3_top( - // Clock and reset signals - input sys_clk_i, // 200MHz - input sys_rst_i, // Active high - - // System signals - output init_calib_complete_0_o, // Once the DDR initialization is complete, the signal will be set to 1 - output init_calib_complete_1_o, // same as above - - // User interface signals - input ddr3_0_rw_en_i, - input [ 2:0] ddr3_0_rw_cmd_i, - input [ 28:0] ddr3_0_rw_addr_i, - input [ 63:0] ddr3_0_wr_mask_i, - input [511:0] ddr3_0_wr_data_i, - input [ 34:0] ddr3_0_rw_info_i, - output ddr3_0_rw_full_o, - - output [511:0] ddr3_0_rd_data_o, - output [ 34:0] ddr3_0_rd_info_o, - output ddr3_0_rd_valid_o, - output ddr3_0_rd_empty_o, - - input ddr3_1_rw_en_i, - input [ 2:0] ddr3_1_rw_cmd_i, - input [ 28:0] ddr3_1_rw_addr_i, - input [ 63:0] ddr3_1_wr_mask_i, - input [511:0] ddr3_1_wr_data_i, - input [ 34:0] ddr3_1_rw_info_i, - output ddr3_1_rw_full_o, - - output [511:0] ddr3_1_rd_data_o, - output [ 34:0] ddr3_1_rd_info_o, - output ddr3_1_rd_valid_o, - output ddr3_1_rd_empty_o, - - // DDR3 interface signals - inout [ 63:0] ddr3_0_dq_io, - inout [ 7:0] ddr3_0_dqs_n_io, - inout [ 7:0] ddr3_0_dqs_p_io, - output [ 14:0] ddr3_0_addr_o, - output [ 2:0] ddr3_0_ba_o, - output ddr3_0_ras_n_o, - output ddr3_0_cas_n_o, - output ddr3_0_we_n_o, - output ddr3_0_reset_n_o, - output [ 0:0] ddr3_0_ck_p_o, - output [ 0:0] ddr3_0_ck_n_o, - output [ 0:0] ddr3_0_cke_o, - output [ 0:0] ddr3_0_cs_n_o, - output [ 7:0] ddr3_0_dm_o, - output [ 0:0] ddr3_0_odt_o, - - - inout [ 63:0] ddr3_1_dq_io, - inout [ 7:0] ddr3_1_dqs_n_io, - inout [ 7:0] ddr3_1_dqs_p_io, - output [ 14:0] ddr3_1_addr_o, - output [ 2:0] ddr3_1_ba_o, - output ddr3_1_ras_n_o, - output ddr3_1_cas_n_o, - output ddr3_1_we_n_o, - output ddr3_1_reset_n_o, - output [ 0:0] ddr3_1_ck_p_o, - output [ 0:0] ddr3_1_ck_n_o, - output [ 0:0] ddr3_1_cke_o, - output [ 0:0] ddr3_1_cs_n_o, - output [ 7:0] ddr3_1_dm_o, - output [ 0:0] ddr3_1_odt_o - ); - - // Internal DDR3 user interface signals - wire ui_0_clk; - wire ui_0_clk_sync_rst; - wire [ 28:0] app_0_addr; - wire [ 2:0] app_0_cmd; - wire app_0_en; - wire [511:0] app_0_wdf_data; - wire app_0_wdf_end; - wire [ 63:0] app_0_wdf_mask; - wire app_0_wdf_wren; - wire [511:0] app_0_rd_data; - wire app_0_rd_data_end; - wire app_0_rd_data_valid; - wire app_0_rdy; - wire app_0_wdf_rdy; - - wire app_0_sr_req; - wire app_0_ref_req; - wire app_0_zq_req; - wire app_0_sr_active; - wire app_0_ref_ack; - wire app_0_zq_ack; - - wire ui_1_clk; - wire ui_1_clk_sync_rst; - wire [ 28:0] app_1_addr; - wire [ 2:0] app_1_cmd; - wire app_1_en; - wire [511:0] app_1_wdf_data; - wire app_1_wdf_end; - wire [ 63:0] app_1_wdf_mask; - wire app_1_wdf_wren; - wire [511:0] app_1_rd_data; - wire app_1_rd_data_end; - wire app_1_rd_data_valid; - wire app_1_rdy; - wire app_1_wdf_rdy; - - wire app_1_sr_req; - wire app_1_ref_req; - wire app_1_zq_req; - wire app_1_sr_active; - wire app_1_ref_ack; - wire app_1_zq_ack; - - assign app_0_sr_req = 1'b0; - assign app_0_ref_req = 1'b0; - assign app_0_zq_req = 1'b0; - - assign app_1_sr_req = 1'b0; - assign app_1_ref_req = 1'b0; - assign app_1_zq_req = 1'b0; - - // Instantiate the module - ddr3_rw_module ddr3_rw_module_0_inst(); - - // Instantiate the DDR3 controller - ddr3_ctrl_0 ddr3_ctrl_0_inst ( - .sys_clk_i (sys_clk_i ), - .sys_rst (sys_rst_i ), - - .ddr3_addr (ddr3_0_dq_io ), - .ddr3_ba (ddr3_0_dqs_n_io ), - .ddr3_cas_n (ddr3_0_dqs_p_io ), - .ddr3_ck_n (ddr3_0_addr_o ), - .ddr3_ck_p (ddr3_0_ba_o ), - .ddr3_cke (ddr3_0_ras_n_o ), - .ddr3_ras_n (ddr3_0_cas_n_o ), - .ddr3_reset_n (ddr3_0_we_n_o ), - .ddr3_we_n (ddr3_0_reset_n_o ), - .ddr3_dq (ddr3_0_ck_p_o ), - .ddr3_dqs_n (ddr3_0_ck_n_o ), - .ddr3_dqs_p (ddr3_0_cke_o ), - .ddr3_cs_n (ddr3_0_cs_n_o ), - .ddr3_dm (ddr3_0_dm_o ), - .ddr3_odt (ddr3_0_odt_o ), - - .init_calib_complete (init_calib_complete_0_o), - .ui_clk (ui_0_clk ), - .ui_clk_sync_rst (ui_0_clk_sync_rst ), - - .app_addr (app_0_addr ), - .app_cmd (app_0_cmd ), - .app_en (app_0_en ), - .app_wdf_data (app_0_wdf_data ), - .app_wdf_end (app_0_wdf_end ), - .app_wdf_mask (app_0_wdf_mask ), - .app_wdf_wren (app_0_wdf_wren ), - .app_rd_data (app_0_rd_data ), - .app_rd_data_end (app_0_rd_data_end ), - .app_rd_data_valid (app_0_rd_data_valid ), - .app_rdy (app_0_rdy ), - .app_wdf_rdy (app_0_wdf_rdy ), - .app_sr_req (app_0_sr_req ), - .app_ref_req (app_0_ref_req ), - .app_zq_req (app_0_zq_req ), - .app_sr_active (app_0_sr_active ), - .app_ref_ack (app_0_ref_ack ), - .app_zq_ack (app_0_zq_ack ) - ); - - // Instantiate the module - ddr3_rw_module ddr3_rw_module_1_inst(); - - // Instantiate the DDR3 controller - ddr3_ctrl_1 ddr3_ctrl_1_inst ( - .sys_clk_i (sys_clk_i ), - .sys_rst (sys_rst_i ), - - .ddr3_addr (ddr3_1_dq_io ), - .ddr3_ba (ddr3_1_dqs_n_io ), - .ddr3_cas_n (ddr3_1_dqs_p_io ), - .ddr3_ck_n (ddr3_1_addr_o ), - .ddr3_ck_p (ddr3_1_ba_o ), - .ddr3_cke (ddr3_1_ras_n_o ), - .ddr3_ras_n (ddr3_1_cas_n_o ), - .ddr3_reset_n (ddr3_1_we_n_o ), - .ddr3_we_n (ddr3_1_reset_n_o ), - .ddr3_dq (ddr3_1_ck_p_o ), - .ddr3_dqs_n (ddr3_1_ck_n_o ), - .ddr3_dqs_p (ddr3_1_cke_o ), - .ddr3_cs_n (ddr3_1_cs_n_o ), - .ddr3_dm (ddr3_1_dm_o ), - .ddr3_odt (ddr3_1_odt_o ), - - .init_calib_complete (init_calib_complete_1_o), - .ui_clk (ui_1_clk ), - .ui_clk_sync_rst (ui_1_clk_sync_rst ), - - .app_addr (app_1_addr ), - .app_cmd (app_1_cmd ), - .app_en (app_1_en ), - .app_wdf_data (app_1_wdf_data ), - .app_wdf_end (app_1_wdf_end ), - .app_wdf_mask (app_1_wdf_mask ), - .app_wdf_wren (app_1_wdf_wren ), - .app_rd_data (app_1_rd_data ), - .app_rd_data_end (app_1_rd_data_end ), - .app_rd_data_valid (app_1_rd_data_valid ), - .app_rdy (app_1_rdy ), - .app_wdf_rdy (app_1_wdf_rdy ), - .app_sr_req (app_1_sr_req ), - .app_ref_req (app_1_ref_req ), - .app_zq_req (app_1_zq_req ), - .app_sr_active (app_1_sr_active ), - .app_ref_ack (app_1_ref_ack ), - .app_zq_ack (app_1_zq_ack ) - ); - -endmodule diff --git a/ddr3_general_design.xpr b/ddr3_general_design.xpr deleted file mode 100644 index 26e9edc..0000000 --- a/ddr3_general_design.xpr +++ /dev/null @@ -1,505 +0,0 @@ - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - Vivado Synthesis Defaults - - - - - - - - - - - - - - - - - - - Vivado Synthesis Defaults - - - - - - - - - - - Vivado Synthesis Defaults - - - - - - - - - - - Vivado Synthesis Defaults - - - - - - - - - - - Vivado Synthesis Defaults - - - - - - - - - - - Vivado Synthesis Defaults - - - - - - - - - - - Vivado Synthesis Defaults - - - - - - - - - - - Default settings for Implementation. - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - Default settings for Implementation. - - - - - - - - - - - - - - - - - - Default settings for Implementation. - - - - - - - - - - - - - - - - - - Default settings for Implementation. - - - - - - - - - - - - - - - - - - Default settings for Implementation. - - - - - - - - - - - - - - - - - - Default settings for Implementation. - - - - - - - - - - - - - - - - - - Default settings for Implementation. - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - default_dashboard - - - - - - diff --git a/ddr_general_design.srcs/sources_1/new/dimm_8G.ucf b/ddr_general_design.srcs/sources_1/new/dimm_8G.ucf new file mode 100644 index 0000000..fbaf97a --- /dev/null +++ b/ddr_general_design.srcs/sources_1/new/dimm_8G.ucf @@ -0,0 +1,240 @@ +NET "ddr3_dq[0]" LOC = "L15" | IOSTANDARD = SSTL15 ; +NET "ddr3_dq[1]" LOC = "K14" | IOSTANDARD = SSTL15 ; +NET "ddr3_dq[2]" LOC = "J14" | IOSTANDARD = SSTL15 ; +NET "ddr3_dq[3]" LOC = "L11" | IOSTANDARD = SSTL15 ; +NET "ddr3_dq[4]" LOC = "K15" | IOSTANDARD = SSTL15 ; +NET "ddr3_dq[5]" LOC = "L16" | IOSTANDARD = SSTL15 ; +NET "ddr3_dq[6]" LOC = "J13" | IOSTANDARD = SSTL15 ; +NET "ddr3_dq[7]" LOC = "K16" | IOSTANDARD = SSTL15 ; +NET "ddr3_dq[8]" LOC = "J12" | IOSTANDARD = SSTL15 ; +NET "ddr3_dq[9]" LOC = "J11" | IOSTANDARD = SSTL15 ; +NET "ddr3_dq[10]" LOC = "H15" | IOSTANDARD = SSTL15 ; +NET "ddr3_dq[11]" LOC = "G14" | IOSTANDARD = SSTL15 ; +NET "ddr3_dq[12]" LOC = "H11" | IOSTANDARD = SSTL15 ; +NET "ddr3_dq[13]" LOC = "H12" | IOSTANDARD = SSTL15 ; +NET "ddr3_dq[14]" LOC = "G13" | IOSTANDARD = SSTL15 ; +NET "ddr3_dq[15]" LOC = "G15" | IOSTANDARD = SSTL15 ; +NET "ddr3_dq[16]" LOC = "D12" | IOSTANDARD = SSTL15 ; +NET "ddr3_dq[17]" LOC = "A11" | IOSTANDARD = SSTL15 ; +NET "ddr3_dq[18]" LOC = "D13" | IOSTANDARD = SSTL15 ; +NET "ddr3_dq[19]" LOC = "E13" | IOSTANDARD = SSTL15 ; +NET "ddr3_dq[20]" LOC = "F11" | IOSTANDARD = SSTL15 ; +NET "ddr3_dq[21]" LOC = "E11" | IOSTANDARD = SSTL15 ; +NET "ddr3_dq[22]" LOC = "A12" | IOSTANDARD = SSTL15 ; +NET "ddr3_dq[23]" LOC = "F12" | IOSTANDARD = SSTL15 ; +NET "ddr3_dq[24]" LOC = "B13" | IOSTANDARD = SSTL15 ; +NET "ddr3_dq[25]" LOC = "A13" | IOSTANDARD = SSTL15 ; +NET "ddr3_dq[26]" LOC = "B15" | IOSTANDARD = SSTL15 ; +NET "ddr3_dq[27]" LOC = "C15" | IOSTANDARD = SSTL15 ; +NET "ddr3_dq[28]" LOC = "B14" | IOSTANDARD = SSTL15 ; +NET "ddr3_dq[29]" LOC = "A15" | IOSTANDARD = SSTL15 ; +NET "ddr3_dq[30]" LOC = "E15" | IOSTANDARD = SSTL15 ; +NET "ddr3_dq[31]" LOC = "F15" | IOSTANDARD = SSTL15 ; +NET "ddr3_dq[32]" LOC = "A23" | IOSTANDARD = SSTL15 ; +NET "ddr3_dq[33]" LOC = "D24" | IOSTANDARD = SSTL15 ; +NET "ddr3_dq[34]" LOC = "E24" | IOSTANDARD = SSTL15 ; +NET "ddr3_dq[35]" LOC = "E26" | IOSTANDARD = SSTL15 ; +NET "ddr3_dq[36]" LOC = "E23" | IOSTANDARD = SSTL15 ; +NET "ddr3_dq[37]" LOC = "B23" | IOSTANDARD = SSTL15 ; +NET "ddr3_dq[38]" LOC = "D23" | IOSTANDARD = SSTL15 ; +NET "ddr3_dq[39]" LOC = "G23" | IOSTANDARD = SSTL15 ; +NET "ddr3_dq[40]" LOC = "B24" | IOSTANDARD = SSTL15 ; +NET "ddr3_dq[41]" LOC = "C24" | IOSTANDARD = SSTL15 ; +NET "ddr3_dq[42]" LOC = "C26" | IOSTANDARD = SSTL15 ; +NET "ddr3_dq[43]" LOC = "A27" | IOSTANDARD = SSTL15 ; +NET "ddr3_dq[44]" LOC = "A25" | IOSTANDARD = SSTL15 ; +NET "ddr3_dq[45]" LOC = "A26" | IOSTANDARD = SSTL15 ; +NET "ddr3_dq[46]" LOC = "B27" | IOSTANDARD = SSTL15 ; +NET "ddr3_dq[47]" LOC = "D26" | IOSTANDARD = SSTL15 ; +NET "ddr3_dq[48]" LOC = "D27" | IOSTANDARD = SSTL15 ; +NET "ddr3_dq[49]" LOC = "A30" | IOSTANDARD = SSTL15 ; +NET "ddr3_dq[50]" LOC = "C30" | IOSTANDARD = SSTL15 ; +NET "ddr3_dq[51]" LOC = "D29" | IOSTANDARD = SSTL15 ; +NET "ddr3_dq[52]" LOC = "C27" | IOSTANDARD = SSTL15 ; +NET "ddr3_dq[53]" LOC = "B30" | IOSTANDARD = SSTL15 ; +NET "ddr3_dq[54]" LOC = "E29" | IOSTANDARD = SSTL15 ; +NET "ddr3_dq[55]" LOC = "E28" | IOSTANDARD = SSTL15 ; +NET "ddr3_dq[56]" LOC = "F28" | IOSTANDARD = SSTL15 ; +NET "ddr3_dq[57]" LOC = "F30" | IOSTANDARD = SSTL15 ; +NET "ddr3_dq[58]" LOC = "H30" | IOSTANDARD = SSTL15 ; +NET "ddr3_dq[59]" LOC = "G28" | IOSTANDARD = SSTL15 ; +NET "ddr3_dq[60]" LOC = "H24" | IOSTANDARD = SSTL15 ; +NET "ddr3_dq[61]" LOC = "G29" | IOSTANDARD = SSTL15 ; +NET "ddr3_dq[62]" LOC = "H27" | IOSTANDARD = SSTL15 ; +NET "ddr3_dq[63]" LOC = "H26" | IOSTANDARD = SSTL15 ; +NET "ddr3_dm[0]" LOC = "K13" | IOSTANDARD = SSTL15 ; +NET "ddr3_dm[1]" LOC = "H14" | IOSTANDARD = SSTL15 ; +NET "ddr3_dm[2]" LOC = "D11" | IOSTANDARD = SSTL15 ; +NET "ddr3_dm[3]" LOC = "E14" | IOSTANDARD = SSTL15 ; +NET "ddr3_dm[4]" LOC = "F26" | IOSTANDARD = SSTL15 ; +NET "ddr3_dm[5]" LOC = "C25" | IOSTANDARD = SSTL15 ; +NET "ddr3_dm[6]" LOC = "D28" | IOSTANDARD = SSTL15 ; +NET "ddr3_dm[7]" LOC = "G30" | IOSTANDARD = SSTL15 ; +NET "ddr3_dqs_p[0]" LOC = "L12" | IOSTANDARD = DIFF_SSTL15 ; +NET "ddr3_dqs_n[0]" LOC = "L13" | IOSTANDARD = DIFF_SSTL15 ; +NET "ddr3_dqs_p[1]" LOC = "J16" | IOSTANDARD = DIFF_SSTL15 ; +NET "ddr3_dqs_n[1]" LOC = "H16" | IOSTANDARD = DIFF_SSTL15 ; +NET "ddr3_dqs_p[2]" LOC = "C12" | IOSTANDARD = DIFF_SSTL15 ; +NET "ddr3_dqs_n[2]" LOC = "B12" | IOSTANDARD = DIFF_SSTL15 ; +NET "ddr3_dqs_p[3]" LOC = "D14" | IOSTANDARD = DIFF_SSTL15 ; +NET "ddr3_dqs_n[3]" LOC = "C14" | IOSTANDARD = DIFF_SSTL15 ; +NET "ddr3_dqs_p[4]" LOC = "F25" | IOSTANDARD = DIFF_SSTL15 ; +NET "ddr3_dqs_n[4]" LOC = "E25" | IOSTANDARD = DIFF_SSTL15 ; +NET "ddr3_dqs_p[5]" LOC = "B28" | IOSTANDARD = DIFF_SSTL15 ; +NET "ddr3_dqs_n[5]" LOC = "A28" | IOSTANDARD = DIFF_SSTL15 ; +NET "ddr3_dqs_p[6]" LOC = "C29" | IOSTANDARD = DIFF_SSTL15 ; +NET "ddr3_dqs_n[6]" LOC = "B29" | IOSTANDARD = DIFF_SSTL15 ; +NET "ddr3_dqs_p[7]" LOC = "G27" | IOSTANDARD = DIFF_SSTL15 ; +NET "ddr3_dqs_n[7]" LOC = "F27" | IOSTANDARD = DIFF_SSTL15 ; +NET "ddr3_addr[13]" LOC = "G22" | IOSTANDARD = SSTL15 ; +NET "ddr3_addr[12]" LOC = "K18" | IOSTANDARD = SSTL15 ; +NET "ddr3_addr[11]" LOC = "G18" | IOSTANDARD = SSTL15 ; +NET "ddr3_addr[10]" LOC = "K19" | IOSTANDARD = SSTL15 ; +NET "ddr3_addr[9]" LOC = "C16" | IOSTANDARD = SSTL15 ; +NET "ddr3_addr[8]" LOC = "J18" | IOSTANDARD = SSTL15 ; +NET "ddr3_addr[7]" LOC = "C17" | IOSTANDARD = SSTL15 ; +NET "ddr3_addr[6]" LOC = "J19" | IOSTANDARD = SSTL15 ; +NET "ddr3_addr[5]" LOC = "B17" | IOSTANDARD = SSTL15 ; +NET "ddr3_addr[4]" LOC = "H17" | IOSTANDARD = SSTL15 ; +NET "ddr3_addr[3]" LOC = "F18" | IOSTANDARD = SSTL15 ; +NET "ddr3_addr[2]" LOC = "E21" | IOSTANDARD = SSTL15 ; +NET "ddr3_addr[1]" LOC = "D21" | IOSTANDARD = SSTL15 ; +NET "ddr3_addr[0]" LOC = "F21" | IOSTANDARD = SSTL15 ; +NET "ddr3_ba[2]" LOC = "J17" | IOSTANDARD = SSTL15 ; +NET "ddr3_ba[1]" LOC = "H20" | IOSTANDARD = SSTL15 ; +NET "ddr3_ba[0]" LOC = "H19" | IOSTANDARD = SSTL15 ; +NET "ddr3_ck_p[0]" LOC = "D17" | IOSTANDARD = DIFF_SSTL15 ; +NET "ddr3_ck_n[0]" LOC = "D18" | IOSTANDARD = DIFF_SSTL15 ; +NET "ddr3_ck_p[1]" LOC = "E19" | IOSTANDARD = DIFF_SSTL15 ; +NET "ddr3_ck_n[1]" LOC = "D19" | IOSTANDARD = DIFF_SSTL15 ; +NET "ddr3_ras_n" LOC = "G20" | IOSTANDARD = SSTL15 ; +NET "ddr3_cas_n" LOC = "K20" | IOSTANDARD = SSTL15 ; +NET "ddr3_we_n" LOC = "H21" | IOSTANDARD = SSTL15 ; +NET "ddr3_reset_n" LOC = "F17" | IOSTANDARD = LVCMOS15 ; +NET "ddr3_cke[0]" LOC = "L17" | IOSTANDARD = SSTL15 ; +NET "ddr3_cke[1]" LOC = "G17" | IOSTANDARD = SSTL15 ; +NET "ddr3_odt[0]" LOC = "D22" | IOSTANDARD = SSTL15 ; +NET "ddr3_odt[1]" LOC = "H22" | IOSTANDARD = SSTL15 ; +NET "ddr3_cs_n[0]" LOC = "F22" | IOSTANDARD = SSTL15 ; +NET "ddr3_cs_n[1]" LOC = "C21" | IOSTANDARD = SSTL15 ; +NET "ddr3_addr[0]" LOC = "F21" | IOSTANDARD = SSTL15 ; +NET "ddr3_addr[10]" LOC = "K19" | IOSTANDARD = SSTL15 ; +NET "ddr3_addr[11]" LOC = "G18" | IOSTANDARD = SSTL15 ; +NET "ddr3_addr[12]" LOC = "K18" | IOSTANDARD = SSTL15 ; +NET "ddr3_addr[13]" LOC = "G22" | IOSTANDARD = SSTL15 ; +NET "ddr3_addr[14]" LOC = "D16" | IOSTANDARD = SSTL15 ; +NET "ddr3_addr[15]" LOC = "L18" | IOSTANDARD = SSTL15 ; +NET "ddr3_addr[1]" LOC = "D21" | IOSTANDARD = SSTL15 ; +NET "ddr3_addr[2]" LOC = "E21" | IOSTANDARD = SSTL15 ; +NET "ddr3_addr[3]" LOC = "F18" | IOSTANDARD = SSTL15 ; +NET "ddr3_addr[4]" LOC = "H17" | IOSTANDARD = SSTL15 ; +NET "ddr3_addr[5]" LOC = "B17" | IOSTANDARD = SSTL15 ; +NET "ddr3_addr[6]" LOC = "J19" | IOSTANDARD = SSTL15 ; +NET "ddr3_addr[7]" LOC = "C17" | IOSTANDARD = SSTL15 ; +NET "ddr3_addr[8]" LOC = "J18" | IOSTANDARD = SSTL15 ; +NET "ddr3_addr[9]" LOC = "C16" | IOSTANDARD = SSTL15 ; +NET "ddr3_ba[0]" LOC = "H19" | IOSTANDARD = SSTL15 ; +NET "ddr3_ba[1]" LOC = "H20" | IOSTANDARD = SSTL15 ; +NET "ddr3_ba[2]" LOC = "J17" | IOSTANDARD = SSTL15 ; +NET "ddr3_cas_n" LOC = "K20" | IOSTANDARD = SSTL15 ; +NET "ddr3_ck_n[0]" LOC = "D18" | IOSTANDARD = DIFF_SSTL15 ; +NET "ddr3_ck_n[1]" LOC = "D19" | IOSTANDARD = DIFF_SSTL15 ; +NET "ddr3_ck_p[0]" LOC = "D17" | IOSTANDARD = DIFF_SSTL15 ; +NET "ddr3_ck_p[1]" LOC = "E19" | IOSTANDARD = DIFF_SSTL15 ; +NET "ddr3_cke[0]" LOC = "L17" | IOSTANDARD = SSTL15 ; +NET "ddr3_cke[1]" LOC = "G17" | IOSTANDARD = SSTL15 ; +NET "ddr3_cs_n[0]" LOC = "F22" | IOSTANDARD = SSTL15 ; +NET "ddr3_cs_n[1]" LOC = "C21" | IOSTANDARD = SSTL15 ; +NET "ddr3_dm[0]" LOC = "K13" | IOSTANDARD = SSTL15 ; +NET "ddr3_dm[1]" LOC = "H14" | IOSTANDARD = SSTL15 ; +NET "ddr3_dm[2]" LOC = "D11" | IOSTANDARD = SSTL15 ; +NET "ddr3_dm[3]" LOC = "E14" | IOSTANDARD = SSTL15 ; +NET "ddr3_dm[4]" LOC = "F26" | IOSTANDARD = SSTL15 ; +NET "ddr3_dm[5]" LOC = "C25" | IOSTANDARD = SSTL15 ; +NET "ddr3_dm[6]" LOC = "D28" | IOSTANDARD = SSTL15 ; +NET "ddr3_dm[7]" LOC = "G30" | IOSTANDARD = SSTL15 ; +NET "ddr3_dq[0]" LOC = "L15" | IOSTANDARD = SSTL15 ; +NET "ddr3_dq[10]" LOC = "H15" | IOSTANDARD = SSTL15 ; +NET "ddr3_dq[11]" LOC = "G14" | IOSTANDARD = SSTL15 ; +NET "ddr3_dq[12]" LOC = "H11" | IOSTANDARD = SSTL15 ; +NET "ddr3_dq[13]" LOC = "H12" | IOSTANDARD = SSTL15 ; +NET "ddr3_dq[14]" LOC = "G13" | IOSTANDARD = SSTL15 ; +NET "ddr3_dq[15]" LOC = "G15" | IOSTANDARD = SSTL15 ; +NET "ddr3_dq[16]" LOC = "D12" | IOSTANDARD = SSTL15 ; +NET "ddr3_dq[17]" LOC = "A11" | IOSTANDARD = SSTL15 ; +NET "ddr3_dq[18]" LOC = "D13" | IOSTANDARD = SSTL15 ; +NET "ddr3_dq[19]" LOC = "E13" | IOSTANDARD = SSTL15 ; +NET "ddr3_dq[1]" LOC = "K14" | IOSTANDARD = SSTL15 ; +NET "ddr3_dq[20]" LOC = "F11" | IOSTANDARD = SSTL15 ; +NET "ddr3_dq[21]" LOC = "E11" | IOSTANDARD = SSTL15 ; +NET "ddr3_dq[22]" LOC = "A12" | IOSTANDARD = SSTL15 ; +NET "ddr3_dq[23]" LOC = "F12" | IOSTANDARD = SSTL15 ; +NET "ddr3_dq[24]" LOC = "B13" | IOSTANDARD = SSTL15 ; +NET "ddr3_dq[25]" LOC = "A13" | IOSTANDARD = SSTL15 ; +NET "ddr3_dq[26]" LOC = "B15" | IOSTANDARD = SSTL15 ; +NET "ddr3_dq[27]" LOC = "C15" | IOSTANDARD = SSTL15 ; +NET "ddr3_dq[28]" LOC = "B14" | IOSTANDARD = SSTL15 ; +NET "ddr3_dq[29]" LOC = "A15" | IOSTANDARD = SSTL15 ; +NET "ddr3_dq[2]" LOC = "J14" | IOSTANDARD = SSTL15 ; +NET "ddr3_dq[30]" LOC = "E15" | IOSTANDARD = SSTL15 ; +NET "ddr3_dq[31]" LOC = "F15" | IOSTANDARD = SSTL15 ; +NET "ddr3_dq[32]" LOC = "A23" | IOSTANDARD = SSTL15 ; +NET "ddr3_dq[33]" LOC = "D24" | IOSTANDARD = SSTL15 ; +NET "ddr3_dq[34]" LOC = "E24" | IOSTANDARD = SSTL15 ; +NET "ddr3_dq[35]" LOC = "E26" | IOSTANDARD = SSTL15 ; +NET "ddr3_dq[36]" LOC = "E23" | IOSTANDARD = SSTL15 ; +NET "ddr3_dq[37]" LOC = "B23" | IOSTANDARD = SSTL15 ; +NET "ddr3_dq[38]" LOC = "D23" | IOSTANDARD = SSTL15 ; +NET "ddr3_dq[39]" LOC = "G23" | IOSTANDARD = SSTL15 ; +NET "ddr3_dq[3]" LOC = "L11" | IOSTANDARD = SSTL15 ; +NET "ddr3_dq[40]" LOC = "B24" | IOSTANDARD = SSTL15 ; +NET "ddr3_dq[41]" LOC = "C24" | IOSTANDARD = SSTL15 ; +NET "ddr3_dq[42]" LOC = "C26" | IOSTANDARD = SSTL15 ; +NET "ddr3_dq[43]" LOC = "A27" | IOSTANDARD = SSTL15 ; +NET "ddr3_dq[44]" LOC = "A25" | IOSTANDARD = SSTL15 ; +NET "ddr3_dq[45]" LOC = "A26" | IOSTANDARD = SSTL15 ; +NET "ddr3_dq[46]" LOC = "B27" | IOSTANDARD = SSTL15 ; +NET "ddr3_dq[47]" LOC = "D26" | IOSTANDARD = SSTL15 ; +NET "ddr3_dq[48]" LOC = "D27" | IOSTANDARD = SSTL15 ; +NET "ddr3_dq[49]" LOC = "A30" | IOSTANDARD = SSTL15 ; +NET "ddr3_dq[4]" LOC = "K15" | IOSTANDARD = SSTL15 ; +NET "ddr3_dq[50]" LOC = "C30" | IOSTANDARD = SSTL15 ; +NET "ddr3_dq[51]" LOC = "D29" | IOSTANDARD = SSTL15 ; +NET "ddr3_dq[52]" LOC = "C27" | IOSTANDARD = SSTL15 ; +NET "ddr3_dq[53]" LOC = "B30" | IOSTANDARD = SSTL15 ; +NET "ddr3_dq[54]" LOC = "E29" | IOSTANDARD = SSTL15 ; +NET "ddr3_dq[55]" LOC = "E28" | IOSTANDARD = SSTL15 ; +NET "ddr3_dq[56]" LOC = "F28" | IOSTANDARD = SSTL15 ; +NET "ddr3_dq[57]" LOC = "F30" | IOSTANDARD = SSTL15 ; +NET "ddr3_dq[58]" LOC = "H30" | IOSTANDARD = SSTL15 ; +NET "ddr3_dq[59]" LOC = "G28" | IOSTANDARD = SSTL15 ; +NET "ddr3_dq[5]" LOC = "L16" | IOSTANDARD = SSTL15 ; +NET "ddr3_dq[60]" LOC = "H24" | IOSTANDARD = SSTL15 ; +NET "ddr3_dq[61]" LOC = "G29" | IOSTANDARD = SSTL15 ; +NET "ddr3_dq[62]" LOC = "H27" | IOSTANDARD = SSTL15 ; +NET "ddr3_dq[63]" LOC = "H26" | IOSTANDARD = SSTL15 ; +NET "ddr3_dq[6]" LOC = "J13" | IOSTANDARD = SSTL15 ; +NET "ddr3_dq[7]" LOC = "K16" | IOSTANDARD = SSTL15 ; +NET "ddr3_dq[8]" LOC = "J12" | IOSTANDARD = SSTL15 ; +NET "ddr3_dq[9]" LOC = "J11" | IOSTANDARD = SSTL15 ; +NET "ddr3_dqs_n[0]" LOC = "L13" | IOSTANDARD = DIFF_SSTL15 ; +NET "ddr3_dqs_n[1]" LOC = "H16" | IOSTANDARD = DIFF_SSTL15 ; +NET "ddr3_dqs_n[2]" LOC = "B12" | IOSTANDARD = DIFF_SSTL15 ; +NET "ddr3_dqs_n[3]" LOC = "C14" | IOSTANDARD = DIFF_SSTL15 ; +NET "ddr3_dqs_n[4]" LOC = "E25" | IOSTANDARD = DIFF_SSTL15 ; +NET "ddr3_dqs_n[5]" LOC = "A28" | IOSTANDARD = DIFF_SSTL15 ; +NET "ddr3_dqs_n[6]" LOC = "B29" | IOSTANDARD = DIFF_SSTL15 ; +NET "ddr3_dqs_n[7]" LOC = "F27" | IOSTANDARD = DIFF_SSTL15 ; +NET "ddr3_dqs_p[0]" LOC = "L12" | IOSTANDARD = DIFF_SSTL15 ; +NET "ddr3_dqs_p[1]" LOC = "J16" | IOSTANDARD = DIFF_SSTL15 ; +NET "ddr3_dqs_p[2]" LOC = "C12" | IOSTANDARD = DIFF_SSTL15 ; +NET "ddr3_dqs_p[3]" LOC = "D14" | IOSTANDARD = DIFF_SSTL15 ; +NET "ddr3_dqs_p[4]" LOC = "F25" | IOSTANDARD = DIFF_SSTL15 ; +NET "ddr3_dqs_p[5]" LOC = "B28" | IOSTANDARD = DIFF_SSTL15 ; +NET "ddr3_dqs_p[6]" LOC = "C29" | IOSTANDARD = DIFF_SSTL15 ; +NET "ddr3_dqs_p[7]" LOC = "G27" | IOSTANDARD = DIFF_SSTL15 ; +NET "ddr3_odt[0]" LOC = "D22" | IOSTANDARD = SSTL15 ; +NET "ddr3_odt[1]" LOC = "H22" | IOSTANDARD = SSTL15 ; +NET "ddr3_ras_n" LOC = "G20" | IOSTANDARD = SSTL15 ; +NET "ddr3_reset_n" LOC = "F17" | IOSTANDARD = LVCMOS15 ; +NET "ddr3_we_n" LOC = "H21" | IOSTANDARD = SSTL15 ; diff --git a/ddr_general_design.xpr b/ddr_general_design.xpr new file mode 100644 index 0000000..4438490 --- /dev/null +++ b/ddr_general_design.xpr @@ -0,0 +1,179 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + default_dashboard + + + diff --git a/others/wavedrom.com.txt b/others/wavedrom.com.txt deleted file mode 100644 index 4e5f77a..0000000 --- a/others/wavedrom.com.txt +++ /dev/null @@ -1,31 +0,0 @@ -{ - signal: [ - {}, - {name: 'clk', wave: 'p........|........'}, - {name: 'rw_req_i', wave: 'x=43=....|.......x', data: ['idle', 'read', 'write', 'idle', ]}, - {name: 'rw_addr_i', wave: 'x=43=....|.......x', data: ['29\'h0000', '29\'h0008', '29\'h000a', '29\'h0000', ]}, - {name: 'wr_data_i', wave: 'x=.3=....|.......x', data: [ '512\'h0000', '512\'hxxxx', '512\'h0000' ]}, - {name: 'rd_src_id_i', wave: 'x=43=....|.......x', data: ['5\'h00', '5\'h01', '5\'h02', '5\'h00', ]}, - {name: 'rd_len_i', wave: 'x=4==....|.......x', data: ['5h\'h00', '5h\'h04', '5\'h01', '5h\'h00', ]}, - {name: 'rw_ack_o', wave: '0..10..10|........'}, - {name: 'rd_addr_o', wave: 'x=.......|..4444=x', data: [ '29\'h0000', '29\'h0008', '29\'h0009', '29\'h000a', '29\'h000b', '29\'h0000' ]}, - {name: 'rd_src_id_o', wave: 'x=.......|..4444=x', data: [ '5\'h00', '5\'h01', '5\'h01', '5\'h01', '5\'h01', '5\'h00' ]}, - {name: 'rd_data_o', wave: 'x=.......|..4444=x', data: [ '512h\'h0000', '512h\'hxxxx', '512\'hxxxx', '512h\'hxxxx', '512h\'hxxxx', '512h\'h0000' ]}, - {name: 'rd_valid_o', wave: '0........|..1...0.', }, - {}, - {}, - {name: 'clk', wave: 'p........|........'}, - {name: 'rw_req_i', wave: 'x=44443=.|.......x', data: ['idle', 'read', 'read', 'read', 'read', 'write', 'idle', ]}, - {name: 'rw_addr_i', wave: 'x=44443=.|.......x', data: ['29\'h0000', '29\'h0008', '29\'h0009', '29\'h000a', '29\'h000b', '29\'h000a', '29\'h0000', ]}, - {name: 'wr_data_i', wave: 'x=....3=.|.......x', data: [ '512\'h0000', '512\'hxxxx', '512\'h0000' ]}, - {name: 'rd_src_id_i', wave: 'x=44443=.|.......x', data: ['5\'h00', '5\'h01', '5\'h01', '5\'h01', '5\'h01', '5\'h02', '5\'h00', ]}, - {name: 'rw_ack_o', wave: '0..1....0|........'}, - {name: 'rd_addr_o', wave: 'x=.......|..4444=x', data: [ '29\'h0_0000', '29\'h0008', '29\'h0009', '29\'h000a', '29\'h000b', '29\'h0000' ]}, - {name: 'rd_src_id_o', wave: 'x=.......|..4444=x', data: [ '5\'h00', '5\'h01', '5\'h01', '5\'h01', '5\'h01', '5\'h00' ]}, - {name: 'rd_data_o', wave: 'x=.......|..4444=x', data: [ '512h\'h0000', '512h\'hxxxx', '512\'hxxxx', '512h\'hxxxx', '512h\'hxxxx', '512h\'h0000' ]}, - {name: 'rd_valid_o', wave: '0........|..1...0.', }, - {}, -], - config: { hscale: 3 } -} - diff --git a/others/~$$ddr3_top.~vsdx b/others/~$$ddr3_top.~vsdx deleted file mode 100644 index de52353..0000000 Binary files a/others/~$$ddr3_top.~vsdx and /dev/null differ